TW200408050A - Method and structure for a wafer level packaging - Google Patents

Abstract

A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

Description

200408050

1. [Technical field to which the invention belongs] The present invention relates to a wafer-level packaging method and a round-level packaging method and structure on a wafer or a transparent frame adhesive, especially to form a spacer on a light substrate. Wall and closed its structure. 2. [Previous Technology] Tian Tiannian, because the fabrication of microcircuits for chips is developing towards a high degree of integration, "chip fabrication also requires high-power, high-density, and lightweight processes. Wafer configuration is the completion of the wafer manufacturing process, with plastic: Ge material, "grains are enclosed in it to achieve the purpose of protecting the crystal grains, so that the crystal grains are not exposed to external water and oxygen and mechanical damage. The main functions of wafer fabrication There are electric transmission (P〇wer Distribution), signal transmission ('i ^ al > DlstribUti〇n), heat dissipation (Heat Dissipati〇n /, protection, protection and support). Due to the integration The development of the circuit manufacturing process will affect the technology of integrated circuit packaging. Today's electronic products require thin, short, and high integrated I. Therefore, the integrated circuit manufacturing process will be miniaturized, which will increase the number of logic circuits included in the chip. This further increases the number of chip I / OC input / output pins. In order to meet these needs, many different packaging methods have been generated, such as ball grid array (BGA), chip size package (Chip Scau Package) , CSP), Multi Chip Module Package (MCM package), Flip Chip Package, Tape Carrier Package (TCp), and wafer-level package Wafer Level Package, WLP) and so on.

200408050 V. Description of the invention (2) Regardless of the shape, the wafer is separated into bracelets, and the f-side ^ 'most of the packaging methods are semiconductor packaging. The packaging is a semiconductor dream: the process of sealing is completed afterwards. While wafer-level wafers are a packaging trend, wafer-level packaging is based on the entire package label: because of 4 packaging :::: == is a single-wafer as a highly integrated encapsulation. Before die-cutting the wafer, complete the second and second technology such as die bonding and wire bonding, which can save glue filling, assembly, low labor costs, and substrate manufacturing, so it can greatly reduce electroplating and inspection 4: die bonding, wire bonding, sealing Gluing, cutting, printing, Αϋ the first-C, the first C is a schematic diagram of traditional packaging technology. For example, first, Γ, first, a semiconductor wafer 101 and a light-transmissive substrate are provided, and the cattle V-body wafer 101 includes a plurality of dies 1 0 3, and moreover, the plurality Each die 103 is formed by a semiconductor process to form a plurality of microcircuits on this die 103 (not shown in the figure). Then, as shown in the first figure b, the semiconductor wafer 1 Each die i 03 is cut and separated by a wafer cutting machine to obtain a plurality of independent die 103, and then the independent die 103 is placed in an The semiconductor substrate 105 is adhered by an epoxy (not shown). The semiconductor substrate 105 includes a bezel 107 (border). The bezel 107 is obtained by using a stencil with a specific pattern and semiconductor process technology, and because a die mount step uses a die attacher Place each independent grain 103 in half

Page 6 200408050 V. Description of the invention (3) On the conductive substrate 1 05, it is easy for the independent die 1 103 to fall, which leads to the number of grains that can be cut out of the semiconductor wafer 101 (gross die). ) 'So the yield will decrease. Then, a wireb process is performed to transmit the circuit signal of each independent die 103 to the outside. This wire-manufacturing process includes wire bonding a gold wire 109 to this separate die 1 0 3 on. Next, as shown in the first C diagram, after each independent die 103 is adhered and placed on the semiconductor substrate 105, a mold process is performed to coat the border 107. Distribute a frame adhesive i 丨 1 and cover a light-transmissive substrate 11 3, so that the crystal grains 10 on the semiconductor substrate 105 are covered with a solid shell to prevent moisture from invading from the outside and can be effectively bonded Upper and lower substrates. Another type of frame adhesive manufacturing process is to randomly mix a plurality of Spacer Bal Is (not shown in the figure) with the frame adhesive 1 1 1 (Sea lan〇) in the process of thin film liquid crystal (TFT-LCD) display. The purpose of the frame adhesive 11 1 is to make the upper and lower substrates in the liquid crystal panel adhere tightly and block the liquid crystal molecules in the panel from the outside. The gap squash ball mainly provides support for the upper and lower substrates. When the light-transmitting substrate 11 is covered and laminated, 'this gap squash will form a flat shape, and because the size and shape of this gap squash are not the same', it is easy to cause the width of the frame 111 to be difficult to control, and at the same time, it is impossible to maintain the two substrates Appropriate gaps (G ap) cause the phenomenon of uneven electric field distribution, which in turn affects the grayscale performance of the liquid crystal. And because the frame adhesive 1 is a polymer material, it is easy to chemically react with the liquid crystal, or when coating Easy to overflow into the display area (Sensor Area) containing a chip 103. In order to

Page 7 200408050 V. Description of the invention (4) Make the frame adhesive 1 1 1 have a large safety distance from the display area, that is, the size of the component (Di mens ion) is not easy to shrink, and the number of grains that can be cut out of a wafer is also Reduced, making it impossible to increase productivity. In the aforementioned conventional packaging process or thin film liquid crystal display process, since the position and width of the plastic frame cannot be effectively and accurately controlled, it is urgent to provide an improved packaging process to overcome the problems faced by the conventional packaging process. III. [Content of the Invention] One object of the present invention is to provide a wafer-level packaging method and structure, which uses a semiconductor process to generate a gap wall step (Spacer Wa 1 1), and can be placed in a closed frame adhesive The inner side wall or the outer side wall of the gap wall accurately controls the position and range of the sealant frame. Therefore, the distance between the sealant frame and the display area is shortened to further control the size of the component, so that the crystal produced by a wafer The number of grains increases, thus increasing productivity. Another object of the present invention is to provide a wafer-level packaging method and structure, which uses a semiconductor process to generate a gap wall (Spacer fall). The semiconductor crystal can be effectively maintained by accurately controlling the height of the gap wall The uniformity of the gap between the circle and the light-transmitting substrate 'and when performing the bonding of the semiconductor wafer and the light-transmitting substrate' can increase the yield by controlling the stability of the width of the closed frame adhesive through the gap wall.

Page 8 200408050 V. Description of the invention (5) Another object of the present invention is to provide a wafer-level packaging method and structure, which uses a semiconductor process to generate a gap wall. Therefore, the semiconductor wafer and transparent After the light substrates are bonded, damage to the crystal grains caused by external moisture entering the display area can be prevented, and heat generated internally can be effectively discharged to the outside. Another object of the present invention is to provide a wafer-level packaging method and structure. The wafer-level packaging method uses the entire wafer and a light-transmissive substrate to be bonded, and then cuts the entire wafer. Therefore, the probability of falling crystal grains and particles falling on the crystal grains during the semiconductor manufacturing process can be reduced, and the yield can be improved. According to the above-mentioned purpose, the present invention provides a wafer-level packaging method and structure. First, a semiconductor wafer and a light-transmissive substrate are provided, wherein the semiconductor wafer includes a plurality of dies and uses a semiconductor process. A plurality of microcircuits are formed on the plurality of grains. The semiconductor wafer system includes Shi Xi (Si) or other semiconductor materials, such as gallium arsenide (GaAs) 4 indium phosphide (I nP), and the plurality of crystal grains on the semiconductor wafer system includes a photosensitive element In addition, the light-transmissive substrate includes a glass or quartz with an optical coating, such as an anti-reflective (AR) layer, an indium tin oxide (ITO) conductive layer, and an infrared cut (IR cut) Layer or a UV cut layer. Next, a dielectric layer, such as a silicon oxide layer, a silicon nitride layer, or a polymer layer, is deposited on the light-transmissive substrate. The polymer layer may include polyimide (Polyimide).

Page 9 200408050

A mask is used to deposit a photoresist layer on a wide dielectric layer, and the photoresist is stretched: the process exposes the dielectric layer, and then the photoresist is used as the photoresist. The electrical layer is subjected to an etching process. The 2 丨 layer is formed into a plurality of η ^ including a dielectric layer, and the photoresist layer is stripped to form a gap wall. The wall structure is on a light-transmissive substrate. The position and geometric shape of the particles refer to the ηt shape on the semiconductor wafer. The size of the Λ gap wall is slightly smaller than: V ', and the shape of the eight corners can be an arm, and its position can be opposite. The two sides or the surroundings form a pair, which may be L-shaped. Rectangular shape, or

In the development process described above, the reference pattern on the semiconductor wafer is used: ί ^ and an automatic frame adhesive machine is used to close and close the frame adhesive 3 cloth next to the outer or inner side walls of the plurality of gap walls. The closed frame rubber system can be selected from epoxy resin, UV adhesive, or thermo-plastic adhesive. Then, the light-transmissive substrate is covered on the semiconductor wafer, and the plurality of crystals on the semiconductor wafer are aligned with the plurality of gap walls on the light-transmissive substrate to complete the process of sealing. The above-mentioned wafer-level packaging method and structure can also use a semiconductor wafer as a substrate, and a structure of a gap wall and a closed frame adhesive can be formed on the semiconductor wafer. In addition, a gap wall structure can also be formed on a semiconductor wafer or a light-transmissive substrate, and a closed frame glue can be formed on a corresponding other semiconductor wafer or a light-transmissive substrate, and the same packaging as described above can be performed. program.

Page 10 200408050 V. Description of the invention (7) IV. [Embodiment] The following is a detailed description of the present invention. The description of the process and structure in the following description does not include the complete process of production. The prior art techniques used in the present invention are only cited in detail here to help explain the present invention. The content of the present invention can be disclosed through the following description of the first preferred embodiment and its related diagrams (second A to second f). First, referring to the second diagram A, a semiconductor wafer 2000 and a light-transmissive substrate 200 are provided. The semiconductor wafer 2000 includes a semiconductor material, such as silicon (s 丨), indium phosphide. (InP) or gallium arsenide (GaAs). Each semiconductor wafer 2000 includes a plurality of dies 2 (die) having a proper shape next to each other, such as a rectangle or a square. Each of these dies 2 includes a light-sensitive element, For example, 'Complementary Oxide Metal Semiconductor Image Sensor (CM0s image sensor), Liquid Crystal on Silicon (LCoS), Charge Coupled Device (CCD), etc. The grain 2 0 1 has a photosensitive area (not shown). In addition, the fabrication of multiple microcircuits is included on the plurality of grains 201 (not shown), and moreover, one side of the mother grains 2 01 or the opposite sides includes a plurality of microcircuits. 201A (Bonding Pads), such as an aluminum pad, is used as a soldering point for the semiconductor wafer 2000 to complete the packaging process and perform a cutting process to electrically connect to another substrate. This pad 20 1 A is formed by chemical vapor deposition or physical vapor deposition. In addition, the light-transmissive substrate 2 0 includes an optical coating 2 0 3 A, such as a transparent indium tin oxide with excellent conductive properties.

Page 11 200408050 V. Description of the invention (8) (Indium Tin Oxide, ITO) layer or an anti-reflection layer 'an infrared cut (IR cut) layer, an ultraviolet cut (UV cut) layer. Next, referring to FIG. 2B, first, a light-transmissive substrate 203, such as a quartz or a glass substrate, is provided. The light-transmissive substrate 20 3 includes an optical coating layer 203A, and then, the optical coating layer is provided. A dielectric layer 205 is deposited on 2 03 A. The material of the dielectric layer 20 5 may be oxidized stone, nitrided stone, or a polymer film (such as polyimide). The dielectric layer 205 may Formed by chemical vapor deposition (Chemical Vapor Deposition, CVD). Next, as shown in FIG. 2C, a photoresist layer 207 is coated on the dielectric layer 205, and a gap wall structure 209 is obtained by using semiconductor processes such as exposure, development, and etching. The formation of the gap wall 209 is performed by the following steps: First, an exposure process is performed, and a photomask (not shown in the figure) with a specific pattern is transferred to the photoresist layer 2 by pattern transfer. 〇7 上. Then ’post-exposure bake this exposed photoresist layer 20 7 (post

Exposure Bake) procedure to reduce the standing wave phenomenon. Then, a developing process is performed to remove the exposed photoresist layer 20 7 to expose a part of the dielectric layer 20 5, and then use the unremoved photoresist layer 2 07 as a photomask and use wet etching. Or dry etching, for example, wet etching of hydrofluoric acid (Hydrofluoric Ac id) wet etching method 'Plasma Etching' or Reactive Ion Etch (RIE) dry etching Way, remove the exposed dielectric layer 20 5 and the optical coating layer 203A below it, and finally, peel

Page 12 200408050

V. Description of the invention (9) The photoresist layer 2 that has not been removed is stripped, 209 is placed on the light-transmitting substrate 203, and a gap wall structure formed as described in the second includes a dielectric layer 205. And optical coating layer 203A, the 209 degree of the gap wall is determined by the material of the gap wall 209, which is generally tens of micrometers (j cr gap wall). And ° 's south is from 0.1 to more, the position of the gap wall 209, the position, size, and geometry of the photosensitive area of the geometry disc 201; the inch can be based on the position of the grain gap wall 209, Geometry depends on shape. What's more, it depends on the location, size and geometry. In the present invention, it is also possible to have an arm geometry ^ according to the gap wall 209 of the crystal grains 201. In the embodiment, the unit structure that is continuous or partially continuous is arranged to 3 疋 to Several independent. The above-mentioned arm-shaped gap wall 2009 can be referred to the two sides of the arm geometry, and the size is slightly smaller than the grain edge; the gap wall 2_geometry on the stand 2 0 1 It can be similar to the semiconductor Y in another embodiment, the = = shape is similar, and the size is = long. The right-to-dry distance is reserved for subsequent use. It is to be noted that the K wall! 0 is in place: what shape and size are not limited to the above-mentioned V embodiment 0, without departing from the scope of the present invention. Distance, for example, L-shaped, etc. 200408050 V. Description of the invention (10) The wall is formed with a width less than 100%. Ancient times ^ 91, _. Closed frame adhesive 2 1 1 with a micro-interval of less than 200 microns. This closed frame adhesive 2 can be used for mounting epoxy resin glue, ultraviolet glue or hot melt glue. The material used for selecting λ λ and the closed frame rubber 211 is determined by the material of the gap wall 209. For example, after the M insurance, "" the material is bought and relied on. Wl taken from; n; wj such as the gap wall When the wall 2 0 9 is a polymer film, such as poly Saimide, it can be used as a UV curing adhesive with fast curing speed and no heating characteristics. When the main π π yintian gap wall 20 9 is an oxide or nitride 溥 film, the frame adhesive of any material can be specified.

Because the position of the gap wall 2 0 9 can be determined according to the size of each grain 2 0 丨 or the photosensitive area on the grain, and the closed frame 2 2 1 adjoins the gap wall 2 9 9 The inner side wall or the outer side wall, so the position of the closed frame rubber 211 can be controlled, and the distance between the display area (photosensitive area) of a die 201 and the closed frame rubber 2 can be effectively shortened, thereby increasing a The number of dies in the wafer is increased to increase its production capacity. Next, a curing process' such as an ultraviolet or thermal curing process is performed on the sealant 2 1 1, and then the sealant 2 11 on the light-transmissive substrate 2 03 is ground using a grinding process. Next, a semiconductor wafer 200 including a plurality of crystal grains 201 is covered on the light-transmitting substrate 20 3 and aligned with a plurality of gap walls 20 9 on the light-transmitting substrate 230. So that each die 2 01 can be located in the structure of the gap wall 2 0 9, and then the semiconductor wafer 2 0 0 and the light-transmissive substrate 2 3 are bonded by the sealant 2 11 to complete the present invention. Invented wafer-level packaging process. Since the present invention uses a semiconductor process to form the gap wall 209,

Page 14 200408050 V. Description of the invention (11) Flat, timely and high-quality board control base light is indeed transparent and can be achieved, round the crystal body, the base light is re-transmissible, and the homogeneous and uniform crystal The body gap between the guide plate and the semi-balanced flat plate and the light support tank can be penetrated by the plate, which is semi-feasible and rounded into the crystal. The body is guided by the half, the emperor controls the branch} Ξ and is 1 or 2 The seal is good. 1X 〇 2 degrees plus glue to increase the frame flat and closed. The seal is high. The stability is controlled by mixing the wide materials. The glue is fine and the ball is used to make the wall. There are steps to follow, because it can be transmitted and you need to make sure that you do n’t have a problem, and) f The outside rate can be sensed, and the full-size plastic frame can be filled into the area. The light sense can be stopped and glue-proof. The frame can be combined and produced. This step is due to high steps, in-process manufacturing into a small area, dimming and lifting. After the wafer-level packaging of the present invention is completed, the gap wall 209 is used as a cutting path. (Scribe Line), execute a scribe procedure, such as laser cutting, wafer cutting (Wafer Saw), etc. When dicing is performed, the entire semiconductor wafer 2000 is diced to obtain a plurality of independent crystal grains 021. When one of the plurality of grains 201 or one of the opposite sides includes a plurality of pads 201 A, the cutting method for the side including the one of the plurality of pads 201A is used. Bevel cutting method, so that welding pad 2 q 1 a is exposed and serves as a contact point with the external electrical connection. Since the present invention is to perform a dicing process after the semiconductor wafer 200 is packaged, the manufacturing time can be shortened, and the chip falling and dust (partic 1 e) due to chip dropping during the manufacturing process can be reduced. The probability of the grains is 201, so the yield of the product can be effectively improved. 200408050 V. Description of the invention (12) The second F diagram is a schematic diagram for explaining the bonding situation of a semiconductor wafer 200 and a light-transmissive substrate 230 in the second E diagram. The content of the present invention can be disclosed through the following description of the second preferred embodiment and its related diagrams (third A to third E). First, referring to FIG. 3A, a semiconductor wafer 300 and a light-transmitting substrate 300 are provided. The semiconductor wafer 300 includes a semiconductor material, such as silicon, indium phosphide, or gallium arsenide. Wait. Each semiconductor wafer 300 includes a plurality of crystal grains 301 having a proper shape and being close to each other, such as a rectangle or a square. Each of the plurality of crystal grains 301 includes a light-sensitive element. For example, complementary metal-oxide semiconductor image sensors, Shi Xiji liquid crystals, charge-coupled devices, etc., that is, each grain 301 has a photosensitive area (not shown). In addition, 'the production of a plurality of microcircuits including a plurality of grains 3 0 1 (not shown)' more 'includes a plurality on one side of each plurality of grains 3 0 1 or on opposite sides Each pad 3 0 1 A, for example, an aluminum pad, is used as a soldering point for electrically connecting another substrate after the semiconductor wafer 300 completes the packaging process and performs a cutting process. This pad 3 0 A is Formed by chemical vapor deposition or physical vapor deposition. In addition, the light-transmissive substrate 3 includes an optical forging film 3 0 3 A ', such as a transparent Indium Tin Oxide (ITO) layer with excellent conductive properties, an anti-reflection layer, and an infrared resistance (IR cut) layer or a UV cut layer. . . Next, referring to FIG. 3B, a dielectric layer 305 is deposited on the semiconductor wafer 300. The semiconductor wafer 300 includes a plurality of grains 3101.

Page 16 200408050 V. Description of the invention (13) The material of the dielectric layer 305 can be an oxide film (such as polyimide), and then, a siliconized rat or a thin polymer layer ... This dielectric layer 3.5;: Light ;; the formation of the product method. The chemical vapor deposition can be used to deposit on the dielectric layer 3 0__yang as shown in Q n, using exposure, development and etching 'and other half' body g: two such as f three C, ::: Each of the plurality of Geely 309 on the semiconductor wafer 300 :: ,, opposite sides of the bull head. The formation of this gap wall 3 09 is performed by the following steps: first: A, execute-micro In the film production process, a mask with a specific pattern is not shown.) The pattern is transferred to the photoresist layer by pattern transfer. Then, the exposed photoresist layer 307 is subjected to a post-exposure baking process to Reducing the occurrence of standing wave phenomenon. Then, the exposed photoresist layer 37 is removed to expose a part of the dielectric layer 305, and then the unresisted photoresist layer 3 07 is used as a photomask, and the wet method is used. Etching or dry etching methods, such as' hydrofluoric acid aqueous solution (Hydrofluoric Ac id) wet etching method, plasma etching (Plasma Etching) or reactive ion etching (Reactive Ion Etch, RIE) dry etching method , The exposed dielectric layer 305 is removed, and finally, the unremoved photoresist layer 3 7 is stripped to form a gap The wall structure 3 0 9 is on the surface of each of the plurality of grains 3 0 1 on the semiconductor wafer 300, for example, two opposite sides. The gap wall 3 0 9 includes a dielectric layer 3 05, and the gap The height of the wall 309 is determined by the material of the gap wall 309. In general, the height is between 0.1 and several tens of micrometers.

Page 17 200408050 V. Description of the invention (14) Furthermore, the position, geometry and size of the gap wall 309 can be determined according to the position, size and geometry of the photosensitive area of the crystal grains 301. Furthermore, the position, geometry and size of the gap wall 309 can also be determined according to the position, size and geometry of the grain 301. In one embodiment of the present invention, the partition wall 309 has an arm-shaped geometry, or an arm-shaped geometric shape arranged in a unit structure that is independent or continuous or partially continuous. The above-mentioned arm-shaped gap wall 309 can be on opposite sides of the grain 3001, and the size is slightly smaller than the length of the side of the grain. In another embodiment, the geometry of the gap wall 309 may be similar to the geometry of the crystal grains, and the size is slightly smaller than the perimeter of the crystal grains to retain a certain distance for subsequent use. It should be noted that the position and size of the gap wall 3 0 9 of the present invention are not limited to those described in the above embodiment, as long as it can be fabricated by using the semiconductor lithography step, it can serve as a balance and support for the light-transmitting substrate 3 0 Those with a fixed distance between 3 and the subsequent grains, such as the shape, etc., do not depart from the scope of the present invention. Next, as shown in Figure 3D, an automatic frame glue machine is used to form a seal with a width of less than 丨 00 ^ m and a height of less than 200 microns on the inner side wall or the outer side wall of the gap wall 309. Frame rubber 311. The material of this closed frame rubber 311 can be epoxy resin, UV glue or hot melt. The material of the selected closed frame rubber 3 1 1 is determined by the partition wall 3 〇 9 material, for example, when the gap wall 3 0 9 is a polymer film, such as polyimide, UV glue with fast curing speed and no heating characteristics can be selected, although the gap wall 3 9 9 is rolled. And nitride films, can be used with any of the aforementioned materials

200408050 V. Description of the invention (15) Frame rubber. Because the position of the gap wall 3 0 9 is determined according to the size of each grain 3 01, and the closed frame adhesive 3 丨 丨 is close to the inner or outer side wall of the gap wall 3 09, so the closed frame adhesive The position of 3 丨 丨 can be controlled, which effectively shortens the distance between the photosensitive area containing a die 3 01 and the sealant 3 丨 1, thereby increasing the number of die obtained from a wafer to increase its productivity. Next, the “closed frame adhesive 3 11” performs a curing process, such as a UV or thermal curing process, and then uses a grinding process to grind the closed frame adhesive 311 on the semiconductor wafer 300 ′ and then “covers an optical coating film 3 〇3A light-transmissive substrate 303 on the semiconductor wafer 300, such as a glass or a quartz substrate, and a plurality of gap wall structures on the semiconductor wafer, 309 'makes the mother a die 301 Both can be located at the Γ of the gap wall 3009; SIT1 pastes the two-conductor crystal H30 ° with the light-transmissive substrate 3.3

To complete the wafer-level package 葙 & L semiconductor process of the present invention to form the gap wall 309. Therefore, in the present invention, the height of the gap 309 and its flatness are used to precisely control the circle and the transparent substrate. During lamination, semi-conductive can be controlled to order between semiconductor wafers. Γ :: ν controls its glue = = two., The other: two ^ 1々 拉 瞍 艺 Λ π on r step 'and can prevent the traditional packaging method The frame adhesive overflows into the sensitive area, and the households can avoid the need for a large safety distance between the frame adhesive and the photosensitive area. Because of &, the production capacity can be increased.

200408050 V. Description of the invention (16) After the wafer-level packaging process, the gap-cutting process, such as laser cutting, is used to grain 3 0 1 of the entire semiconductor wafer 3 0 0, when a plurality of grains 3 0 When there are a plurality of pads 3 0 1 A in 1, the cutting method of the package is to use a bevel cutting method as one of the electrical connections with the outside to contact the conductor wafer 3 0 0, and then the manufacturing time is performed, and It can reduce the probability of yield due to dust falling on the grain 301 due to dust during the process. Then, after completing the present invention, the wall 309 is a dicing path, and wafer cutting is performed. When performing the cutting, the cutting is performed to obtain a plurality of independent crystal sides or the opposite sides include a side containing a plurality of pads 3 0 1 A so that the pads 3 0 A are exposed. Since the present invention is to complete the half-cutting process, it is possible to shorten the drop and decrease of the crystal grains in the production process. Therefore, the third E picture is used to help explain the third j) picture. A schematic diagram of the bonding situation of the semiconductor wafer 300 and a light-transmissive substrate 303. After the first and second preferred embodiments are described above, it can be clearly understood that the present invention also has other implementations. For example, the gap structure can be formed on a semiconductor wafer or transparent It can also be coated on the light substrate, and its sealant can also be coated on the corresponding other semiconductor wafer or light substrate, and then a cutting process is performed to obtain a separated independent wafer completed by the seal. According to the above description of the preferred embodiment of the present invention, one of the advantages of the invention is the formation of a gap wall structure. The gap solution • ’T, the main structure of 200408050

V. Description of the invention (17) The formation can precisely control the position of the sealing frame glue, and then control the size of the component. Therefore, the number of crystal grains obtained after dicing of a wafer can be increased. In addition, by precisely controlling the height of the gap wall, the uniformity of the gap between the semiconductor wafer and the light-transmittable substrate and the stability of the width of the sealant can be controlled. After the substrates are bonded together, a cutting process is performed, so that the productivity can be increased. D The above is only a patent application for the comparative invention of the present invention. At the same time, experts in the field should be able to understand and implement the scope of equivalent patent application under the spirit of disclosure. The preferred embodiment is not intended to limit the private description of this. For those familiar with the technical field: Therefore, other changes or modifications that do not depart from the present invention should be included in the following.

Page 21, 200408050 Brief description of the drawings [Simplified illustration of the drawings] Figures A to C are the schematic diagrams of the semiconductor structure corresponding to each step of the traditional packaging technology process; Figures A to F are based on A schematic diagram of a semiconductor structure junction surface corresponding to each step of a preferred embodiment of a wafer electrode packaging method of the present invention, wherein a spacer structure is formed on a light-transmissive substrate; and FIGS. 3A to 3E It is a schematic diagram of a semiconductor structure corresponding to each step of another preferred embodiment of a wafer electrode packaging method according to the present invention. The spacer structure is formed on a semiconductor wafer. Representative symbols of the main part 101

Page 22 200408050 Brief description of the drawing 20 3A optical coating 205 dielectric layer 207 photoresist layer 209 gap wall 212 sealing frame 300 semiconductor wafer 301 die 301A pad 303 light-transmissive substrate 305 dielectric layer 307 photoresist Layer 309 Clearance wall 311 Closure «

Page 23

Claims (1)

200408050 6. Scope of patent application1. A wafer-level light-emitting area of a plurality of grains; a plurality of gaps; the light-sensitive area; a plurality of closed areas; a plurality of closed frames; The plurality of spacers in the application scope 3 · As the plurality of spacers in the application scope 4 · The plurality of spacers 5 in the application scope · The polymer film system 6 in the application scope · The transparent in the application scope Of light substrate The installed structure includes: next to each other, the mother-the plurality of grains have a sensible wall structure on the plurality of grains, each of which is between the plurality of interstitial wall structures; On the ancestor, each of the names (adjoining) on each of the gap wall junctions, 1 1 η adjacent to wa 1 1); and the board is located on the plurality of gap wall structures, and the material of the wall structure is an oxidation; e 夕 物,. In the wafer-level package described in 1 above, the material of the wall structure is a nitrided compound. The structure of the wafer-level package described in item 1 above is made of a thin polymer. The structure of the wafer-level package described in item 4 above includes a polyimide. / 、 The structure of the wafer-level package described in 1 above is made of glass. Among them, the above-mentioned 200408050 6. Scope of patent application 7. The structure of the wafer-level package as described in item 1 of the application scope, wherein the above-mentioned closed frame adhesive material is an epoxy resin adhesive. 8. The structure of the wafer-level package according to item 1 of the application scope, wherein the above-mentioned closed frame adhesive material is a UV adhesive 9. The structure of the wafer-level package according to the application area, wherein the above The closed frame adhesive material is a hot melt adhesive. 10. The structure of the wafer-level package according to item 1 of the application scope, wherein any one of the above-mentioned side walls is an inner side wall. 11. The structure of the wafer-level package according to item 1 of the application scope, wherein any one of the side walls is an outer side wall. 12. The structure of the wafer-level package according to item 1 of the application scope, wherein the plurality of gap wall structures described above include at least two unit structures. 1 3. The structure of the wafer-level package as described in item 12 of the scope of application, wherein the plurality of gap wall structures further includes two opposite sides on the plurality of grains. 1 4. The structure of the wafer-level package as described in item 12 of the application scope, wherein the above Page 25 200408050 VI. Scope of Patent Application The plurality of gap wall structures described above further include two adjacent sides on the plurality of grains. 1 5. The structure of the wafer-level package according to item 1 of the scope of application, wherein the plurality of gap wall structures further include geometric shapes arranged in an arm shape by a plurality of independent unit structures. 16. The structure of the wafer-level package according to item 1 of the scope of application, wherein the plurality of gap wall structures further includes a geometric shape arranged in an arm shape by a plurality of continuous unit structures. 1 7. A method for wafer-level packaging, comprising: providing a semiconductor wafer, wherein the semiconductor wafer includes a plurality of dies; depositing a dielectric layer on the semiconductor wafer, and covering the plurality of dies Grains, removing a part of the dielectric layer to form a plurality of gap wall structures on each of the plurality of grain surfaces; forming a plurality of closed frame adhesives adjacent to any one of the side walls of the plurality of gap wall structures; And covering a light transmissive substrate on the semiconductor wafer. 18. The method of wafer-level packaging as described in item 17 of the scope of application, wherein any one of the plurality of dies described above includes a light-sensitive area. Page 26 200408050 6. Scope of Patent Application 19. The method of wafer-level packaging as described in scope 17 of the application, wherein the step of removing the dielectric layer includes exposing a photosensitive area. 20. The method of wafer-level packaging as described in the scope of application 19, wherein the above-mentioned photosensitive area further includes being surrounded by any four of the plurality of gap wall structures. 2 1. The method of wafer level packaging as described in item 17 of the scope of application, wherein any one of the side walls is an inner side wall. 2 2. The method of wafer level packaging as described in item 17 of the scope of application, wherein any one of the side walls is an outer side wall. 2 3. The method of wafer-level packaging as described in item 17 of the scope of application, wherein the material of the light-transmittable substrate is quartz. 2 4. A method for wafer-level packaging, including: providing a semiconductor wafer and a light-transmissive substrate, wherein the semiconductor wafer includes a plurality of dies, and depositing a dielectric layer on the light-transmissive substrate Depositing a photoresist layer on the dielectric layer; removing part of the photoresist layer to expose part of the dielectric layer; removing part of the exposed dielectric layer, using the photoresist layer as a photomask, Page 27, 200408050 6. Applying for a patent to form a plurality of gap wall structures on the light-transmissive substrate; forming a plurality of closed frame adhesives adjacent to any side wall of the plurality of gap wall structures; and covering the semiconductor A wafer is on the light-transmissive substrate. 25. The method for wafer-level packaging as described in item 24 of the scope of application, wherein the step of removing a part of the exposed dielectric layer includes using the plurality of dies of the semiconductor wafer as a reference pattern. 26. The method of wafer level packaging as described in item 24 of the scope of application, wherein any one of the side walls is an inner side wall. 27. The method of wafer level packaging according to item 24 of the scope of application, wherein any one of the side walls is an outer side wall. 28. The method of wafer level packaging according to item 24 of the scope of application, wherein any one of the plurality of dies mentioned above includes a photosensitive area. Page 28