CN105185798B - A kind of wafer-level packaging method and its encapsulating structure of back side illumination image sensor - Google Patents
A kind of wafer-level packaging method and its encapsulating structure of back side illumination image sensor Download PDFInfo
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- CN105185798B CN105185798B CN201510412091.4A CN201510412091A CN105185798B CN 105185798 B CN105185798 B CN 105185798B CN 201510412091 A CN201510412091 A CN 201510412091A CN 105185798 B CN105185798 B CN 105185798B
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Abstract
The present invention relates to a kind of wafer-level packaging method of back side illumination image sensor and its encapsulating structures, it includes the following steps：It is that CIS wafers are thinned in support, and add optical filtering and lenticule at the back side of CIS wafers to load wafer in the front bonding load wafer of CIS wafers；It is covered with light transmission glue at the back side of CIS wafers, optical filtering and lenticule is protected by light transmission glue；It is that load wafer is thinned in support with light transmission glue；Lead is made at the back side of load wafer；Light transmission glue is thinned, is cut after being thinned and obtains one chip, packaging method terminates.Directly be covered in photosensitive region with one layer of light transmission glue does protection enclosure cover to the present invention; and support is done to do subsequent lead technique with this, light transmission glue is polished by grinding and polishing, last cutting crystal wafer is at single chip; present invention reduces technology difficulties and cost, while reducing the thickness of chip.
Description
Technical field
The present invention does not only disclose a kind of wafer-level packaging method of back side illumination image sensor, and the invention also discloses one
The wafer level packaging structure of kind back side illumination image sensor, the invention belongs to technical field of semiconductor encapsulation.
Background technology
In recent years with imaging sensor（CIS）Increasing, the physics of sensor single pixel of chip pixel value
Size is smaller and smaller, also becomes increasingly complex for the integrated circuit fabrication process of Sensor section in chip in this way, so that should
Part has been difficult to be manufactured in the technique with along with signal processing module.Additionally due to the photosensitive region of single pixel
Smaller and smaller, image fault in order to prevent, to the amount of incident photon, there has also been stringenter limitations.
Wafer-level packaging before is to do interconnection line from the back of wafer, and photon penetrates metal interconnection from the front of wafer
Layer enters photosensitive regions of pixels, and complicated metal interconnection layer often blocks a part of photon, the light for causing photosensitive region to obtain
Subnumber mesh cannot meet the requirement of imaging.Described above in order to solve the problems, such as, current encapsulation is all gradually intended to using the back of the body
Illuminated technique（BSI）, will the original circuit part between camera lens and light receiving semiconductor be transferred to around light receiving semiconductor or
Below so that light can directly enter photosensitive region, it is therefore prevented that blocking of the interconnection circuit to light greatly improves single pixel
Utilization ratio of the unit to light.Even more photosensitive areas are made in image sensing module in design chips in order to obtain
In one chip, is produced, the module of processing signal is accomplished in another chip, the more economical technique of use with compared with high technology level
Production, realizes the interconnection of two chips by way of encapsulation after finishing.
One sheet glass all first can be done protection enclosure cover and be used for protecting photosensitive region from envelope by traditional wafer-level packaging mode
The pollution and damage of processing procedure are filled, and this layer of glass is often cut off the part as chip in last cutting, affects light
The transmission ability of son, while also adding the thickness and cost of chip.
Invention content
An object of the present invention is to overcome the deficiencies in the prior art, provide one kind can reduce technology difficulty and
Cost reduces a kind of wafer-level packaging method of back side illumination image sensor of the thickness of chip simultaneously.
It is a further object of the present invention to provide a kind of wafer level packaging structures of back side illumination image sensor.
According to technical solution provided by the invention, a kind of wafer-level packaging method of back side illumination image sensor includes
Following steps：
A, it takes and makes the CIS wafers of lead and imaging sensor in its front, in the front bonding load of CIS wafers
Wafer is that CIS wafers are thinned in support, and add optical filtering and lenticule at the back side of CIS wafers to load wafer；
B, it is covered with light transmission glue at the back side of CIS wafers, optical filtering and lenticule is protected by light transmission glue；
C, it is that load wafer is thinned in support with light transmission glue；
D, conductive column is made in load wafer, and conductive layer is deposited in the upper end of conductive column；
E, light transmission glue is thinned, is cut after being thinned and obtain one chip, packaging method terminates.
Preferably, the material of the CIS wafers is silicon, and the thickness of CIS wafers is 200 ~ 600 μm.
Preferably, the material of the load wafer is organic glass, unorganic glass, resin, semi-conducting material, oxide
Crystal, ceramics, metal, organic plastics, inorganic oxide or ceramic material, and the thickness for loading wafer is 300 ~ 800 μm.
The material of the conductive column is copper, aluminium or copper and tin.
The material of the conductive layer is copper, aluminium, nickel or gold, and the thickness of conductive layer is 0.4 ~ 30 μm.
Preferably, the material of the light transmission glue is heat-sensitive glue or light-sensitive emulsion, the thickness of light transmission glue is 10 ~ 300 μm, thoroughly
The gluing mode of optical cement includes coating gluing mode, spraying gluing mode, pad pasting gluing mode or injection molding gluing mode, light transmission
The performance parameter and kind of glue.
Preferably, in step a, closes or use by Si-Si bonding, silica bonding, oxygen-oxygen bond in the front of CIS wafers
Glue bond mode is bonded load wafer.
It is that load wafer to thickness is thinned is 80 ~ 120 μm for support with light transmission glue preferably, in step c.
A kind of wafer level packaging structure of back side illumination image sensor, it includes CIS wafers, load wafer, optical filtering, micro-
Lens, light transmission glue, conductive column, lead, imaging sensor and conductive layer；The front of CIS wafers is connected with the back side of load wafer,
The front of light transmission glue is connected with the back side of CIS wafers, and optical filtering, lead and imaging sensor are equipped in CIS wafers, and image passes
The front of sensor is connected with the lower end of lead, and the back side of imaging sensor is connected with optical filtering, is corresponded at the back side of optical filtering
Position is equipped with lenticule, and lenticule is located in light transmission glue, and conductive column, the lower end of conductive column and lead are equipped in load wafer
Upper end be connected, conductive column upper surface corresponding position be equipped with conductive layer.
The upper surface of the conductive column is concordant with the front of load wafer.
The present invention is directly covered in photosensitive region with one layer of light transmission glue and does protection enclosure cover, and it is subsequent to do with this to do support
Lead technique polishes glue by grinding and polishing, and last cutting crystal wafer is at single chip, and present invention reduces technology difficulties
And cost, while reducing the thickness of chip.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described.It should be evident that the accompanying drawings in the following description is only this
Some embodiments described in invention, for those of ordinary skill in the art, without creative efforts,
Other drawings may also be obtained based on these drawings.
Fig. 1 is the structural schematic diagram of CIS in the present invention.
Fig. 2 is the structural schematic diagram of the obtained packaging bodies of step a of the present invention.
Fig. 3 is the structural schematic diagram of the obtained packaging bodies of step b of the present invention.
Fig. 4 is the structural schematic diagram of the obtained packaging bodies of step c of the present invention.
Fig. 5 is the structural schematic diagram of the obtained packaging bodies of step d of the present invention.
Fig. 6 is the structural schematic diagram of the obtained packaging bodies of step e of the present invention.
Specific implementation mode
The present invention is further explained in the light of specific embodiments.
Below with reference to specific implementation mode shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that those skilled in the art are made according to these embodiments, method or functionally
Transformation is included within the scope of protection of the present invention.
In addition, the label repeated or mark may be used in various embodiments.These are repeated only for simple clear
The ground narration present invention, not representing has any relevance between the different embodiments and/or structure discussed.
The label about step mentioned in the embodiments of the present invention, it is only for the convenience of description, and do not have
There is the contact of substantial sequencing.Different step in each specific implementation mode can carry out the combination of different sequencings,
Realize the goal of the invention of the present invention.
Embodiment 1
A kind of wafer-level packaging method of back side illumination image sensor of the present invention includes the following steps：
A, it takes and makes the CIS wafers 1 of lead 7 and imaging sensor 8 in its front, CIS wafers 1 are that thickness is 200 μ
The silicon chip of m is bonded load wafer 2 by conventional Si-Si bonding mode in the front of CIS wafers 1, is support to load wafer 2
CIS wafers 1 are thinned, and optical filtering 3 and lenticule 4 are added at the back side of CIS wafers 1, as shown in Figure 2；
B, it is covered by light transmission glue 5 in conventional coating gluing mode at the back side of CIS wafers 1, the material of light transmission glue 5
Matter is thermosetting epoxy resin, is protected to optical filtering 3 and lenticule 4 by light transmission glue 5, as shown in Figure 3；
C, it is that load wafer 2 is thinned in support with light transmission glue 5, as shown in Figure 4；
D, conductive column 6 is made in load wafer 2, and deposits copper conductive layer 9 in the upper end of conductive column 6, such as
Shown in Fig. 5；
E, light transmission glue 5 is carried out being thinned to thickness being 80 ~ 120 μm, is cut after being thinned and obtains one chip, packaging method knot
Beam, as shown in Figure 6.
Embodiment 2
A kind of wafer-level packaging method of back side illumination image sensor of the present invention includes the following steps：
A, it takes and makes the CIS wafers 1 of lead 7 and imaging sensor 8 in its front, CIS wafers 1 are that thickness is 600 μ
The silicon chip of m is support to load wafer 2 in the front of CIS wafers 1 by conventional silica bonding pattern bonding load wafer 2
CIS wafers 1 are thinned, and optical filtering 3 and lenticule 4 are added at the back side of CIS wafers 1, as shown in Figure 2；
B, it is covered by light transmission glue 5 in conventional spraying gluing mode at the back side of CIS wafers 1, the material of light transmission glue 5
Matter is light curable type epoxy resin, is protected to optical filtering 3 and lenticule 4 by light transmission glue 5, as shown in Figure 3；
C, it is that load wafer 2 is thinned in support with light transmission glue 5, as shown in Figure 4；
D, conductive column 6 is made in load wafer 2, and the conductive layer 9 of aluminum is deposited in the upper end of conductive column 6, such as
Shown in Fig. 5；
E, light transmission glue 5 is carried out being thinned to thickness being 80 ~ 120 μm, is cut after being thinned and obtains one chip, packaging method knot
Beam, as shown in Figure 6.
Embodiment 3
A kind of wafer-level packaging method of back side illumination image sensor of the present invention includes the following steps：
A, it takes and makes the CIS wafers 1 of lead 7 and imaging sensor 8 in its front, CIS wafers 1 are that thickness is 300 μ
The silicon chip of m is bonded load wafer 2 in the front of CIS wafers 1 by way of conventional oxygen-oxygen bond conjunction, is support to load wafer 2
CIS wafers 1 are thinned, and optical filtering 3 and lenticule 4 are added at the back side of CIS wafers 1, as shown in Figure 2；
B, it is covered by light transmission glue 5 in conventional pad pasting mode at the back side of CIS wafers 1, the material of light transmission glue 5 is
Thermosetting epoxy resin is protected optical filtering 3 and lenticule 4 by light transmission glue 5, as shown in Figure 3；
C, it is that load wafer 2 is thinned in support with light transmission glue 5, as shown in Figure 4；
D, conductive column 6 is made in load wafer 2, and the conductive layer 9 of nickel matter is deposited in the upper end of conductive column 6, such as
Shown in Fig. 5；
E, light transmission glue 5 is carried out being thinned to thickness being 80 ~ 120 μm, is cut after being thinned and obtains one chip, packaging method knot
Beam, as shown in Figure 6.
Embodiment 4
A kind of wafer-level packaging method of back side illumination image sensor of the present invention includes the following steps：
A, it takes and makes the CIS wafers 1 of lead 7 and imaging sensor 8 in its front, CIS wafers 1 are that thickness is 400 μ
The silicon chip of m is bonded load wafer 2 in the front of CIS wafers 1 by way of conventional oxygen-oxygen bond conjunction, is support to load wafer 2
CIS wafers 1 are thinned, and optical filtering 3 and lenticule 4 are added at the back side of CIS wafers 1, as shown in Figure 2；
B, it is covered by light transmission glue 5 in conventional injection molding gluing mode at the back side of CIS wafers 1, the material of light transmission glue 5
Matter is light curable type epoxy resin, is protected to optical filtering 3 and lenticule 4 by light transmission glue 5, as shown in Figure 3；
C, it is that load wafer 2 is thinned in support with light transmission glue 5, as shown in Figure 4；
D, conductive column 6 is made in load wafer 2, and deposits golden conductive layer 9 in the upper end of conductive column 6, such as
Shown in Fig. 5；
E, light transmission glue 5 is carried out being thinned to thickness being 80 ~ 120 μm, is cut after being thinned and obtains one chip, packaging method knot
Beam, as shown in Figure 6.
The one chip that above example 1, embodiment 2, embodiment 3 and embodiment 4 obtain, it includes CIS wafers 1, bears
Carry wafer 2, optical filtering 3, lenticule 4, light transmission glue 5, conductive column 6, lead 7, imaging sensor 8 and conductive layer 9；CIS wafers 1
Front is connected with the back side of load wafer 2, and the front of light transmission glue 5 is connected with the back side of CIS wafers 1, is equipped in CIS wafers 1
The front of optical filtering 3, lead 7 and imaging sensor 8, imaging sensor 8 is connected with the lower end of lead 7, imaging sensor 8
The back side is connected with optical filtering 3, and lenticule 4 is equipped in the back side corresponding position of optical filtering 3, and lenticule 4 is located in light transmission glue 5,
It loads and is equipped with conductive column 6 in wafer 2, the lower end of conductive column 6 is connected with the upper end of lead 7, in the upper surface pair of conductive column 6
Position is answered to be equipped with conductive layer 9.
The upper surface of the conductive column 6 is concordant with the front of load wafer 2；The material of the conductive column 6 be copper, aluminium or
Copper and tin.
The material of the conductive layer 9 is copper, aluminium, nickel or gold, and the thickness of conductive layer 9 is 0.4 ~ 30 μm.
The logical process wafer for loading wafer 2 and being involved in stack BSI techniques, can also be naked silicon
Wafer, organic glass, unorganic glass, resin, semi-conducting material, oxide crystal, ceramics, metal, organic plastics, inorganic oxide
Object, ceramic material etc.；It can be transparent can also be opaque, can be the thin slice of one layer of single substance composition, also may be used
To be thin slice that multilayer same substance or different material form.
The thickness of the light transmission glue 5 is 10 ~ 300 μm, and the gluing mode of light transmission glue 5 is including in coating gluing mode, spraying
It is heat-sensitive glue or light-sensitive emulsion that glue mode, pad pasting gluing mode, which are either molded gluing mode and light transmission glue 5,.
In step a, CIS wafers 1 front can directly Si-Si bonding, silica bonding or oxygen-oxygen bond close etc. hot pressing work
The bonding pattern of skill etc, the mode that can also be glued are bonded load wafer 2.
In step c, with light transmission glue 5 be support be thinned load wafer 2 to thickness be 80 ~ 120 μm, be thinned mode include grinding
And polishing step, thickness thinning are determined according to the thickness of optical property and chip.
For those skilled in the art, it is clear that invention is not limited to the details of the above exemplary embodiments, and is not carrying on the back
In the case of spirit or essential attributes from the present invention, the present invention can be realized in other specific forms.Therefore, no matter from which
From the point of view of a bit, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is wanted by appended right
Ask rather than above description limit, it is intended that by all changes that come within the meaning and range of equivalency of the claims
It is included within the present invention.Any reference signs in the claims should not be construed as limiting the involved claims.
In addition, it should be understood that although this specification is described in terms of embodiments, but not each embodiment is only wrapped
Containing an independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should
It considers the specification as a whole, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
The other embodiment being appreciated that.
Claims (6)
1. a kind of wafer-level packaging method of back side illumination image sensor, it is characterized in that this approach includes the following steps：
A, it takes and makes lead in its front（7）And imaging sensor（8）Imaging sensor wafer（1）, in image sensing
Device wafer（1）Front bonding load wafer（2）, to load wafer（2）Imaging sensor wafer is thinned to support（1）The back of the body
Face, and in imaging sensor wafer（1）The back side add optical filtering（3）And lenticule（4）；
B, in imaging sensor wafer（1）Back side light transmission glue（5）It is covered, passes through light transmission glue（5）To optical filtering（3）With
Lenticule（4）It is protected；
C, with light transmission glue（5）Load wafer is thinned to support（2）；
D, in load wafer（2）Inside make conductive column（6）, and in conductive column（6）Upper end deposit conductive layer（9）；It is described
Conductive column（6）Upper surface with load wafer（2）Front it is concordant；
E, light transmission glue（5）It is thinned, is cut after being thinned and obtain one chip, packaging method terminates；
In step a, in imaging sensor wafer（1）Front closed by Si-Si bonding, silica bonding, oxygen-oxygen bond or use gluing
Conjunction mode is bonded load wafer（2）；
In step c, with light transmission glue（5）Load wafer is thinned to support（2）It it is 80 ~ 120 μm to thickness.
2. a kind of wafer-level packaging method of back side illumination image sensor as described in claim 1, it is characterized in that：Described image
Sensor wafer（1）Thickness be 200 ~ 600 μm.
3. a kind of wafer-level packaging method of back side illumination image sensor as described in claim 1, it is characterized in that：The load
Wafer（2）Material be organic glass, unorganic glass, semi-conducting material, metal, organic plastics or ceramic material.
4. a kind of wafer-level packaging method of back side illumination image sensor as described in claim 1, it is characterized in that：The light transmission
Glue（5）Material be thermosetting epoxy resin or light curable type epoxy resin, light transmission glue（5）Gluing mode include coating glue
Mode, pad pasting gluing mode or injection molding gluing mode.
5. a kind of wafer-level packaging method of back side illumination image sensor as described in claim 1, it is characterized in that：The conduction
Column（6）Material be copper and tin.
6. a kind of wafer-level packaging method of back side illumination image sensor as described in claim 1, it is characterized in that：The conduction
Layer（9）Thickness be 0.4 ~ 30 μm.
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| CN107452636B (en) * | 2017-07-28 | 2022-11-29 | 盛合晶微半导体(江阴)有限公司 | Packaging structure and packaging method of face recognition chip |
| CN114628304A (en) * | 2020-12-10 | 2022-06-14 | 武汉新芯集成电路制造有限公司 | Chip bonding method |
| CN113990966A (en) * | 2021-12-01 | 2022-01-28 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure and packaging method |
| CN114669452B (en) * | 2022-03-26 | 2023-06-06 | 宁波芯健半导体有限公司 | Coating method, coating device and storage medium for back adhesive of ultrathin chip |
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| CN101752266A (en) * | 2008-12-22 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Chip scale package structure of CMOS (complementary metal-oxide-semiconductor) image sensor and packaging method |
| CN101996899A (en) * | 2009-08-14 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Cmos image sensor and manufacturing method thereof |
| CN104009052A (en) * | 2013-02-27 | 2014-08-27 | 精材科技股份有限公司 | Wafer packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101752266A (en) * | 2008-12-22 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Chip scale package structure of CMOS (complementary metal-oxide-semiconductor) image sensor and packaging method |
| CN101996899A (en) * | 2009-08-14 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Cmos image sensor and manufacturing method thereof |
| CN104009052A (en) * | 2013-02-27 | 2014-08-27 | 精材科技股份有限公司 | Wafer packaging method |
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