JP4632694B2 - Wafer level package method and structure - Google Patents

Description

  The present invention relates to a method and structure for a wafer level package, and more particularly, to a method and structure for a wafer level package in which a spacer wall and a sealant are formed on a wafer or a transparent substrate.

  In recent years, the fabrication of chip microcircuits has progressed toward higher integration, and therefore, the chip package also requires processes such as high efficiency, high density, light weight, thinness, and miniaturization. The chip package achieves the purpose of protecting the die by encapsulating the die in a material such as plastic or ceramic after the manufacture of the wafer is completed, so that the die is not subject to external moisture or mechanical damage. is there. The main functions of the chip package include electrical energy transmission (Power Distribution), signal transmission (Signal Distribution), heat dissipation (Heat Distribution), and protection and support (Protection and Support). The development of integrated circuit manufacturing processes has affected the technology of integrated circuit packages, and electronic products are currently required to be lightweight, thin, and highly integrated. Further, the number of input / output (I / O) pins of the chip increases. Many different packaging schemes to meet these requirements, such as ball grid array (BGA), chip scale package (CSP), multichip module package (MCM package), flip chip package, tape carrier package (TCP) and wafer level Package (WLP) etc. occurred.

  Regardless of the type of packaging method, most packaging methods complete the packaging process after making the wafer an independent chip. Wafer level packaging is a trend in the semiconductor packaging process, and wafer level packaging does not target the entire wafer, which is different from traditional packages where a single chip is the target of the package. The steps of resin filling, assembly, die mounting, and wire bonding can be omitted, and a lead frame or a substrate is not necessary, so that labor costs can be saved in large quantities and manufacturing time can be shortened. The main processes of traditional packaging technology include processes such as scribing, die mounting, wire bonding, inspection cutting, inspection, printing, electroplating and inspection.

  Figures 1 to 3 show traditional packaging techniques. First, a semiconductor wafer 101 and a translucent substrate 113 are provided. The semiconductor wafer 101 includes a plurality of dies 103, and a plurality of microcircuits are formed in the plurality of dies 103 using a semiconductor process. Subsequently, as shown in FIG. 2, each die 103 of the semiconductor wafer 101 is cut and separated by a chip cutting machine to obtain a plurality of independent dies 103. Thereafter, the independent die 103 is placed on the semiconductor substrate 105 by an arm of a die bonding machine, and bonded with epoxy (not shown). The semiconductor substrate 105 includes a border 107. The border 107 is obtained by using a specific pattern stencil and semiconductor process technology. In the die mount process, a die mount machine is used to place the individual dies 103 on the semiconductor substrate 105, and therefore, the situation in which the independent dies 103 drop off easily occurs. Therefore, the die scribed from the semiconductor wafer 101 is scribed. The number decreases, which reduces the yield. Thereafter, a wire bonding process is performed so that the circuit signal of each independent die 103 can be transmitted to the outside. In this wire bonding process, the gold wire 109 is bonded to the independent die 103.

  Subsequently, as shown in FIG. 3, after the independent dies 103 are bonded onto the semiconductor substrate 105, a molding process is performed. This is to apply a sealant 111 on the border 107 and coat with a transparent substrate 113 to form a strong case for covering the die 103 on the semiconductor substrate 105, preventing moisture from entering from the outside, In addition, the upper and lower substrates are effectively bonded.

  In addition, in the sealant process, a plurality of spacer balls (not shown) are mixed with the sealant 111 in the TFT-LCD manufacturing process. The use of the sealant 111 is to tightly bond the upper and lower two-layer substrates in the liquid crystal panel and to isolate the liquid crystal molecules in the panel from the outside world, and the spacer balls support the upper and lower two-layer substrates. When the upper transparent substrate 113 is covered and pressure-bonded, the spacer ball forms a flat state, and the size and shape of the spacer ball are not constant. Therefore, it is not easy to control the width of the sealant 111. An appropriate gap cannot be maintained between the upper and lower two-layer substrates, and therefore, a phenomenon in which the electric field distribution becomes non-uniform is formed, which affects the gray level expression of the liquid crystal. In addition, the sealant 111 is made of a high molecular material, so that it easily causes a chemical reaction with the liquid crystal or overflows during application and overflows into the sensor area including the die 103. Since a large safe distance is provided between the sealant 111 and the sensor area, it is difficult to reduce the size of the element, the number of dies that can be cut from the wafer is reduced, and the production rate is difficult to improve.

  In the above-described traditional packaging process or TFT-LCD manufacturing process, the position and width of the sealant cannot be controlled effectively and accurately, and therefore an improved sealant process that can overcome the problems of the known packaging process. The offer is awaited.

  It is an object of the present invention to provide a wafer level package method and structure, which uses a semiconductor process to form a spacer wall and place a sealant on the inner or outer side wall of the spacer wall to accurately It is a method and structure that can control the position and range of the sealant, thereby reducing the distance between the sealant and the sensor area, controlling the size of the apparatus, and increasing the number of dies that can be formed from the wafer, thereby increasing the production capacity. Shall.

  Another object of the present invention is to provide a wafer level package method and structure, in which a spacer wall is formed by a semiconductor process, and the height of the accurate spacer wall is controlled to effectively perform the semiconductor. A method and a structure capable of maintaining the uniformity of the gap between the wafer and the transparent substrate and controlling the stability of the sealant width by the spacer wall to increase the yield when performing the bonding of the semiconductor wafer and the transparent substrate. Shall.

  It is yet another object of the present invention to provide a wafer level package method and structure, which forms a spacer wall by a semiconductor process, and thus, after bonding of a semiconductor wafer and a light-transmitting substrate, the external environment. It is a method and apparatus that prevents damage caused by moisture entering the sensor area from forming on the die and allows the heat generated inside to be effectively discharged to the outside.

  Yet another object of the present invention is to provide a method and structure for wafer level packaging, which is performed during semiconductor processing by scribing the entire wafer after bonding the wafer and the transparent substrate. A method and apparatus for reducing the probability of dropout of a die and falling of a particle on the die and increasing the yield.

The invention of claim 1 comprises a wafer level package structure comprising a plurality of dies, a plurality of spacer wall structures, a plurality of sealants, and a translucent substrate.
The dies are close to each other, each having a sensor area,
The plurality of spacer wall structures are positioned on the plurality of dies, the plurality of spacer wall structures each include an optical plating film, and each sensor area is positioned between the plurality of spacer wall structures,
Sealant plurality of Situated above the plurality of dies, each sealant Supesawo - adjacent to the side wall of Le structure,
The light-transmitting substrate is located on a plurality of spacer wall structures, and the optical plating film is located between the spacer wall structure and the light- transmitting substrate .
According to a second aspect of the present invention, there is provided a wafer level package structure according to the first aspect, wherein a plurality of spacer wall structure materials are made of silicon oxide.
According to a third aspect of the present invention, there is provided a wafer level package structure according to the first aspect, wherein a plurality of spacer wall structure materials are made of silicon nitride.
According to a fourth aspect of the present invention, there is provided a wafer level package structure according to the first aspect, wherein a plurality of spacer wall structure materials are polymer thin films.
The invention of claim 5 is the structure of a wafer level package according to claim 4, wherein the polymer thin film comprises polyimide.
The invention of claim 6 is the structure of a wafer level package according to claim 1, wherein the material of the transparent substrate is glass.
The invention of claim 7 is the structure of the wafer level package according to claim 1, wherein the sealant material is an epoxy resin.
The invention of claim 8 is the structure of the wafer level package according to claim 1, wherein the sealant material is an ultraviolet adhesive.
The invention of claim 9 is the structure of the wafer level package according to claim 1, wherein the sealant material is a thermoplastic resin .
The invention according to claim 10 is the structure of the wafer level package according to claim 1, wherein each sealant is adjacent to a side wall approaching the sensor area in each spacer wall structure . It has a structure.
The invention of claim 11 is the structure of the wafer level package according to claim 1, wherein each of the sealants is adjacent to a side wall away from the sensor area in each of the spacer wall structures . It has a structure.
According to a twelfth aspect of the present invention, there is provided a wafer level package structure according to the first aspect, wherein each die includes at least two spacer wall structures .
The invention of claim 13 is the structure of a wafer level package according to claim 12, wherein the at least two spacer wall structures are located on two opposite sides of the die . .
The invention of claim 14 is the structure of a wafer level package according to claim 12, wherein the at least two spacer wall structures are located on two adjacent sides of the die . .
The invention according to claim 15 is the wafer level package structure according to claim 1, wherein each spacer wall structure includes an arm-like portion in which a plurality of independent unit structures are arranged. The package structure.
A sixteenth aspect of the present invention is the wafer level package structure according to the first aspect, wherein each spacer wall structure includes an arm-like portion in which a plurality of continuous unit structures are arranged. It has a level package structure.
The invention of claim 17 provides a wafer level package method,
Providing a semiconductor wafer having a plurality of dies, and a translucent substrate having an optical plating film;
Depositing a dielectric layer on the translucent substrate;
Depositing a photoresist layer on the dielectric layer;
Removing a portion of the photoresist layer to expose a portion of the dielectric layer;
The exposed dielectric layer is removed, and a plurality of spacer wall structures are formed on the light-transmitting substrate using the photoresist layer as a mask. The plurality of spacer wall structures are provided with the optical plating film, An optical plating film is located between the spacer wall structure and the translucent substrate;
Forming a plurality of sealants adjacent to sidewalls of a plurality of spacer wall structures;
Coating a transparent substrate with a semiconductor wafer;
The wafer level package method is characterized by comprising the above steps.
18. The wafer level package method according to claim 17, wherein each die includes a sensor area, and each sealant is adjacent to a side wall approaching the sensor area in each spacer wall structure. This is a method for wafer level packaging.
19. The wafer level package method according to claim 17, wherein each of the dies includes a sensor area, and each of the sealants is adjacent to a side wall of the spacer wall structure that is remote from the sensor area. This is a method for wafer level packaging.

  In the present invention, a spacer wall structure is formed, and by forming the spacer wall, the position of the sealant can be accurately controlled, and further, the element size can be controlled, thereby increasing the number of dies obtained after wafer scribing. it can. In addition, since the height of the spacer wall can be accurately controlled, the uniformity of the gap between the semiconductor wafer and the translucent substrate and the stability of the sealant width can be controlled, and the scribing process is performed after joining the semiconductor wafer and the translucent substrate. The production capacity can be increased by performing the above.

  The present invention provides a kind of wafer level package method and apparatus. According to the present invention, first, a semiconductor wafer and a translucent substrate are provided. Among them, the semiconductor wafer has a plurality of dies, and a plurality of microcircuits are formed on the plurality of dies by a semiconductor process. The semiconductor wafer comprises silicon or other semiconductor material, such as gallium arsenide (GaAs) or indium phosphide (InP), and a plurality of dies on the semiconductor wafer comprise elements having a photosensitive effect. In addition, the light-transmitting substrate is an optical plating film, for example, a glass having an antireflection (AR) layer, an indium tin oxide (ITO) conductive layer, an infrared cut (IR cut) layer, or an ultraviolet cut (UV cut) layer. Or it has quartz. Further, a dielectric layer such as a silicon oxide layer, a silicon nitride layer, or a polymer layer is deposited on the transparent substrate, and the polymer layer may be polyimide. Subsequently, a photoresist layer is deposited on the dielectric layer, and a lithography process is performed on the photoresist layer to expose the dielectric layer, and then etching is performed on the dielectric layer using the photoresist layer as a mask. A plurality of spacer wall structures having dielectric layers are formed on the light-transmitting substrate by finally removing the photoresist layer, and the position, size, and geometry of the spacer wall are defined on the semiconductor wafer. With reference to the position and geometry of multiple dies, the size of this spacer wall is slightly smaller than the size of the die, and the geometry is arm-shaped, either on opposite sides or on four sides. The shape is rectangular or quadrangular so as to surround, or L-shaped. During the above-described lithography process, a plurality of dies on a semiconductor wafer are used as a reference pattern, and a sealant is applied by an automatic sealing machine and is brought close to an outer side wall or an inner side wall of a plurality of spacer walls. UV adhesive (adhesive) or thermoplastic, and a plurality of dies on the semiconductor wafer are aligned with a plurality of spacer walls on the translucent substrate to complete the packaging process.

  According to the method and structure of the wafer level package described above, a semiconductor wafer can be used as a substrate, and a spacer wall and a sealant structure are formed on the semiconductor wafer. In addition, a spacer wall structure may be formed on the semiconductor wafer or the light transmitting substrate, a sealant is formed on the corresponding semiconductor wafer or the light transmitting substrate, and the same packaging process as described above is performed. .

  A first embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 4, a semiconductor wafer 200 and a translucent substrate 203 are provided. The semiconductor wafer 200 comprises a semiconductor material such as silicon, indium phosphide or gallium arsenide. A plurality of mutually adjacent dies 201 are formed on the semiconductor wafer 200. The dies 201 are, for example, rectangular or quadrangular, and each die 201 is a device having a photosensitive effect, such as a CMOS image sensor, LCoS, a charge coupled device (CCD). ), That is, each die 201 has a sensor area (not shown). In addition, a plurality of microcircuits (not shown) are formed on a plurality of dies 201, and a plurality of bonding pads 201A, for example, aluminum bonding pads are provided on one side of each die 201 or on both sides opposite to each other. This is a bonding point for electrically connecting the wafer 200 to another substrate after completion of the packaging process and execution of the scribing process. The bonding pad 201A is formed by chemical vapor deposition or physical vapor deposition. In addition, the translucent substrate 203 includes an optical plating film 203A, for example, a transparent indium tin oxide (ITO) layer or antireflection layer having good conductivity, an infrared cut layer, and an ultraviolet light cut layer.

  Subsequently, as shown in FIG. 5, a translucent substrate 203 is provided. The translucent substrate 203 is, for example, a quartz or glass substrate, and an optical plating film 203A is formed on the translucent substrate 203. A dielectric layer 205 is deposited on the optical plating film 203A, and the material of the dielectric layer 205 can be silicon oxide, silicon nitride, or a polymer thin film (for example, polyimide). This dielectric layer 205 is formed by chemical vapor deposition (CVD).

  Subsequently, as shown in FIG. 6, a photoresist layer 207 is applied on the dielectric layer 205, and a spacer wall 209 structure is formed by a semiconductor process such as exposure, development and etching. The shape of the spacer wall 209 is formed by the following process. First, an exposure process is performed, and a pattern (transfer pattern) is transferred to the photoresist layer 207 by a pattern transfer method using a mask (not shown) having a specific pattern. Subsequently, a post exposure bake process is performed on the exposed photoresist layer 207 to reduce the occurrence of a standing wave phenomenon. Thereafter, an exposure process is performed, and the exposed photoresist layer 207 is removed to expose a part of the dielectric layer 205. Thereafter, wet etching or dry etching using the unremoved photoresist layer 207 as a mask, for example, hydrofluoric acid wet etching, plasma etching or reactive ion etching (RIE) dry etching is used. Then, the exposed dielectric layer 205 and the optical plating film 203A thereunder are removed. Finally, when the unremoved photoresist layer 207 is stripped, a spacer wall 209 structure is formed on the transparent substrate 203, as shown in FIG. The spacer wall 209 includes a dielectric layer 205 and an optical plating film 203A. The height of the spacer wall 209 is determined by the material of the spacer wall 209, and the altitude is generally 0.1 to several tens of micrometers. .

  Further, the position, geometry and size of the spacer wall 209 are determined by the position, size and geometry of the sensor area of the die 201. In some embodiments of the present invention, the spacer wall 209 may have an arm-like geometry, or may be an arm-like geometry formed by arranging a plurality of independent or continuous or partially continuous unit structures. The The arm-shaped spacer wall 209 described above may be disposed on opposite sides of the die 201 so that the size is slightly smaller than the side length of the die. In another embodiment, the geometry of the spacer wall 209 is similar to the geometry of the die on the semiconductor wafer or the sensor area on the die, and the size is slightly smaller than the perimeter of the die for use in subsequent processes. The gap is reserved. In particular, the position, geometry, and size of the spacer wall 209 of the present invention are not limited to the above-described embodiments, but are formed using a semiconductor lithography process and the transparent substrate 203 and the subsequent substrate. That which can support a fixed distance between the dies on average, for example, L type, etc., does not depart from the scope of the present invention.

  Subsequently, as shown in FIG. 8, using an automatic sealant machine, a sealant 211 having a width smaller than 1000 micrometers and a height smaller than 200 micrometers is formed on the inner side wall or the outer side wall of the spacer wall 209. To do. The material of the sealant 211 can be an epoxy resin, a UV adhesive, or a thermoplastic. The material of the selected sealant 211 is determined by the material of the spacer wall 209. For example, when the spacer wall 209 is a polymer thin film, for example, polyimide, a UV adhesive that has a high curing speed and does not require heating is used. When the spacer wall 209 is an oxide and nitride thin film, any of the aforementioned sealants can be combined.

  The position of the spacer wall 209 is determined based on the size of each die 201 or the sensor area on the die and close to the inner or outer side wall of the spacer wall 209 of the sealant 211, thereby controlling the position of the sealant 211. In addition, the distance between the sensor area of the die 201 and the sealant 211 is effectively controlled, thereby increasing the number of dies obtained from the wafer and increasing the production capacity. Subsequently, a solidification process, for example, a solidification process using an ultraviolet light or a heat process, is performed on the sealant 211, and then the sealant 211 positioned on the light-transmitting substrate 203 is polished using a grinding process. Subsequently, the semiconductor wafer 200 having a plurality of dies 201 is coated on the transparent substrate 203 and aligned with the plurality of spacer walls 209 on the transparent substrate 203, whereby each die 201 is aligned with the spacer wall. 209 is located within the structure. Further, the semiconductor wafer 200 and the translucent substrate 203 are bonded by the sealant 211 to complete the wafer level package of the present invention.

  In the present invention, since the spacer wall 209 is formed using a semiconductor process, its height and flatness can be accurately controlled. Therefore, the uniformity of the gap between the semiconductor wafer and the light transmitting substrate can be controlled when the semiconductor wafer and the light transmitting substrate are bonded. Further, since the sealant 211 does not support the height (or distance) between the semiconductor wafer and the light transmitting substrate, the height and flatness can be accurately controlled by this, and the yield can be increased. In addition, the present invention can control the stability of the resin width, increase the yield, and reduce the number of steps because the traditional spacer ball material does not need to be mixed in the sealant 211. This prevents the sealant from overflowing into the sensor area in the traditional packaging method. This eliminates the need for a large safety distance between the sealant and the sensor area and increases its production capacity.

  After the wafer level package of the present invention is completed, the spacer wall 209 is used as a scribe line, and a scribe process, for example, a laser scribing process or a wafer cutting process is performed. When scribing is performed, the entire semiconductor wafer 200 is cut to obtain a plurality of independent dies 201. In the case where there are a plurality of bonding pads 201A on one side of the plurality of dies 201 or on both sides opposite to each other, a diagonal cutting method is adopted as the one side scribing method including the plurality of bonding pads 201A. 201A is exposed and used as a contact point for electrical connection with the outside world. Since the present invention further performs a scribing process after the package of the semiconductor wafer 200 is completed, the manufacturing time can be shortened, and the probability of chip falling and dust falling onto the die 201 during the manufacturing process can be reduced. Can be increased.

  FIG. 9 shows a bonding state of the semiconductor wafer 200 and the light transmitting substrate 203 in FIG. 8 of the present invention.

  The content of the present invention is also presented by FIGS. 10 to 14 relating to the following second embodiment. First, as shown in FIG. 10, a semiconductor wafer 300 and a translucent substrate 303 are provided. The semiconductor wafer 300 comprises a semiconductor material such as silicon, indium phosphide or gallium arsenide. A plurality of mutually adjacent dies 301 are formed on the semiconductor wafer 300, and the dies 301 are, for example, rectangular or quadrangular. Each die 301 is a device having a photosensitive effect, for example, a CMOS image sensor, LCoS, a charge coupled device (CCD). ), That is, each die 301 has a sensor area (not shown). In addition, a plurality of microcircuits (not shown) are formed on a plurality of dies 301, and a plurality of bonding pads 301A, for example, aluminum bonding pads are provided on one side of each die 301 or on both sides opposite to each other. This is a bonding point for electrically connecting the wafer 300 to another substrate after completion of the packaging process and execution of the scribing process. The bonding pad 301A is formed by chemical vapor deposition or physical vapor deposition. In addition, the translucent substrate 303 includes an optical plating film 303A, for example, a transparent indium tin oxide (ITO) layer having good conductivity or an antireflection layer, an infrared cut layer, and an ultraviolet light cut layer.

  Subsequently, as shown in FIG. 11, a dielectric layer 305 is deposited on the semiconductor wafer 300, and the semiconductor wafer 300 includes a plurality of dies 301, and the material of the dielectric layer 305 is silicon oxide, silicon nitride, or high It can be a molecular thin film (for example, polyimide). A photoresist layer 307 is applied on the dielectric layer 305, and the dielectric layer 305 and the photoresist layer 307 are formed by chemical vapor deposition.

  After the photoresist layer 307 is deposited on the dielectric layer 305, subsequently, as shown in FIG. 12, the spacer wall 309 structure is formed on the surface of each die 301 by a semiconductor process such as exposure, development and etching. Form on opposite sides. The spacer wall 309 is formed by the following steps. First, a lithography process is performed, and a pattern (not shown) having a specific pattern is used to transfer a pattern to the photoresist layer 307 by a pattern transfer method. Subsequently, a post-exposure bake process is performed on the exposed photoresist layer 307 to reduce the occurrence of a standing wave phenomenon. Thereafter, the exposed photoresist layer 307 is removed to expose a part of the dielectric layer 305. Then, using the unremoved photoresist layer 307 as a mask, a wet etching method or a dry etching method, for example, a hydrofluoric acid wet etching method, a plasma etching method or a reactive ion etching (RIE) dry etching method is used. The exposed dielectric layer 305 is removed. Finally, when the unremoved photoresist layer 307 is stripped, a spacer wall 309 structure is formed on the surface of each die 301 of the semiconductor wafer 300, for example, on opposite sides, and the spacer wall 309 is formed. The height of the spacer wall 309 is determined by the material of the spacer wall 309, and the altitude is generally 0.1 to several tens of micrometers.

  Further, the position, geometry and size of the spacer wall 309 are determined by the position, size and geometry of the sensor area of the die 301. Further, the position, geometry and size of the spacer wall 309 are determined by the size and geometry of the die 301. In some embodiments of the present invention, the spacer wall 309 may have an arm-like geometry, or may be an arm-like geometry in which a plurality of independent or continuous or partially continuous unit structures are arranged. The The arm-shaped spacer wall 309 described above may be disposed on opposite sides of the die 301 so that the size is slightly smaller than the side length of the die. In another embodiment, the geometry of the spacer wall 309 is similar to the geometry of the die on the semiconductor wafer or the sensor area on the die, and the size is slightly smaller than the perimeter of the die for use in subsequent processes. The gap is reserved. In particular, the position, geometry, and size of the spacer wall 309 according to the present invention are not limited to the above-described embodiments, but are formed using a semiconductor lithography process to form the transparent substrate 303 and the subsequent substrate. That which can support a fixed distance between the dies on average, for example, L type, etc., does not depart from the scope of the present invention.

  Subsequently, as shown in FIG. 13, by using an automatic sealant machine, a sealant 311 having a width smaller than 1000 micrometers and a height smaller than 200 micrometers is formed on the inner side wall or the outer side wall of the spacer wall 309. To do. The material of the sealant 311 can be an epoxy resin, a UV adhesive, or a thermoplastic. The material of the selected sealant 311 is determined by the material of the spacer wall 309. For example, when the spacer wall 309 is a polymer thin film, for example, polyimide, a UV adhesive that has a high curing speed and does not require heating is used. When the spacer wall 309 is an oxide and nitride thin film, any of the aforementioned sealants can be combined.

  The position of the spacer wall 309 is determined based on each die 301 or die size, and the sealant 311 is in close proximity to the inner or outer side wall of the spacer wall 309, thereby controlling the position of the sealant 311 and the die 301. The distance between the sensor area and the sealant 311 is effectively controlled, thereby increasing the number of dies obtained from the wafer and increasing the production capacity. Subsequently, a solidification process, for example, a solidification process using an ultraviolet light or a heat process, is performed on the sealant 311, and then the sealant 211 located on the semiconductor wafer 300 is polished using a grinding process. Subsequently, a transparent substrate 303 having an optical plating film 303A, for example, a glass or quartz substrate, is coated on the semiconductor wafer 300 and aligned with a plurality of spacer walls 309 on the semiconductor wafer 300. Both are positioned within the structure of the spacer wall 309. Further, the semiconductor wafer 300 and the translucent substrate 303 are bonded by the sealant 311 to complete the wafer level package of the present invention.

  In the present invention, since the spacer wall 309 is formed using a semiconductor process, its height and flatness can be accurately controlled. Therefore, it is possible to control the uniformity of the gap between the semiconductor wafer and the light transmissive substrate at the time of bonding the semiconductor wafer and the light transmissive substrate, and further to control the stability of the resin width, thereby increasing the yield of the product. . In addition, since it is not necessary to mix the traditional spacer ball material into the sealant 311, the number of processes can be reduced, and the sealant can be prevented from overflowing into the sensor area in the traditional packaging method. This eliminates the need for a large safety distance between the sealant and the sensor area and increases its production capacity.

  After the wafer level package of the present invention is completed, the spacer wall 309 is used as a scribe line, and a scribe process, for example, a laser scribing process or a wafer cutting process is performed. When scribing is performed, the entire semiconductor wafer 300 is cut to obtain a plurality of independent dies 301. In the case where there are a plurality of bonding pads 301A on one side of the plurality of dies 301 or on both sides opposite to each other, an oblique cutting method is adopted as the one-side scribing method including the plurality of bonding pads 301A. 301A is exposed and used as a contact point for electrical connection with the outside world. Since the present invention further performs a scribing process after the package of the semiconductor wafer 300 is completed, the manufacturing time can be shortened, and the probability of falling of the chip and falling of the dust onto the die 301 during the manufacturing process can be reduced. To increase.

  FIG. 14 shows a bonding state of the semiconductor wafer 300 and the transparent substrate 303 in FIG. 13 of the present invention.

  From the above description of the first and second embodiments, it can be seen that the present invention also has other embodiments. For example, the spacer wall structure can be formed on the semiconductor wafer and the light-transmitting substrate, respectively, and the sealant can also be formed. It can be applied to another corresponding semiconductor wafer or translucent substrate, and then a scribing process can be performed to obtain an independent chip having a completed package.

FIG. 6 is a cross-sectional view of a semiconductor structure corresponding to a traditional package technology process. FIG. 6 is a cross-sectional view of a semiconductor structure corresponding to a traditional package technology process. FIG. 6 is a cross-sectional view of a semiconductor structure corresponding to a traditional package technology process. 1 is a cross-sectional view of a semiconductor structure corresponding to a process of a wafer level packaging method according to a first embodiment of the present invention, and a spacer wall structure is formed on a translucent substrate. 1 is a cross-sectional view of a semiconductor structure corresponding to a process of a wafer level packaging method according to a first embodiment of the present invention, and a spacer wall structure is formed on a translucent substrate. 1 is a cross-sectional view of a semiconductor structure corresponding to a process of a wafer level packaging method according to a first embodiment of the present invention, and a spacer wall structure is formed on a translucent substrate. 1 is a cross-sectional view of a semiconductor structure corresponding to a process of a wafer level packaging method according to a first embodiment of the present invention, and a spacer wall structure is formed on a translucent substrate. 1 is a cross-sectional view of a semiconductor structure corresponding to a process of a wafer level packaging method according to a first embodiment of the present invention, and a spacer wall structure is formed on a translucent substrate. 1 is a cross-sectional view of a semiconductor structure corresponding to a process of a wafer level packaging method according to a first embodiment of the present invention, and a spacer wall structure is formed on a translucent substrate. FIG. 6 is a cross-sectional view of a semiconductor structure corresponding to a wafer level package method according to a second embodiment of the present invention, and the spacer wall structure is formed on a semiconductor wafer. FIG. 6 is a cross-sectional view of a semiconductor structure corresponding to a wafer level package method according to a second embodiment of the present invention, and the spacer wall structure is formed on a semiconductor wafer. FIG. 6 is a cross-sectional view of a semiconductor structure corresponding to a wafer level package method according to a second embodiment of the present invention, and the spacer wall structure is formed on a semiconductor wafer. FIG. 6 is a cross-sectional view of a semiconductor structure corresponding to a wafer level package method according to a second embodiment of the present invention, and the spacer wall structure is formed on a semiconductor wafer. FIG. 6 is a cross-sectional view of a semiconductor structure corresponding to a wafer level package method according to a second embodiment of the present invention, and the spacer wall structure is formed on a semiconductor wafer.

Explanation of symbols

101 Semiconductor wafer 103 Die 105 Semiconductor substrate 107 Border 109 Gold wire 111 Sealant 113 Translucent substrate 200 Semiconductor wafer 201 Die 201A Bonding pad 203 Translucent substrate 203A Optical plating film 205 Dielectric layer 207 Photoresist layer 209 Spacer wall 211 Sealant 300 Semiconductor wafer 301A Bonding pad 303 Translucent substrate 305 Dielectric layer 307 Photoresist layer 309 Spacer wall 311 Sealant

Claims (17)

A wafer level package structure comprising a plurality of dies, a plurality of spacer wall structures, a plurality of sealants, and a translucent substrate,
The dies are close to each other, each having a sensor area,
The plurality of spacer wall structures are located on the plurality of dies and are discontinuously arranged. Each of the plurality of spacer wall structures includes an optical plating film, and each sensor area has the plurality of spacer wall structures. Located between
The plurality of sealants are located on the plurality of dies, each sealant adjacent to a sidewall of the spacer wall structure;
A structure of a wafer level package, wherein the translucent substrate is located on a plurality of spacer wall structures, and the optical plating film is located between the spacer wall structure and the translucent substrate.   2. The wafer level package structure according to claim 1, wherein a material of the plurality of spacer wall structures is silicon oxide.   2. The wafer level package structure according to claim 1, wherein a material of the plurality of spacer wall structures is silicon nitride.   2. The wafer level package structure according to claim 1, wherein a plurality of spacer wall structure materials are polymer thin films.   5. The structure of a wafer level package according to claim 4, wherein the polymer thin film comprises polyimide.   2. The wafer level package structure according to claim 1, wherein the material of the light transmitting substrate is glass.   2. The wafer level package structure according to claim 1, wherein the sealant material is an epoxy resin.   2. The wafer level package structure according to claim 1, wherein the sealant material is an ultraviolet adhesive.   2. The wafer level package structure according to claim 1, wherein the sealant material is a thermoplastic resin.   2. The wafer level package structure of claim 1, wherein each sealant is adjacent to a side wall of the spacer wall structure that approaches the sensor area.   2. The wafer level package structure of claim 1, wherein each sealant is adjacent to a sidewall of each spacer wall structure remote from the sensor area.   2. The wafer level package structure of claim 1, wherein each die comprises at least two spacer wall structures.   13. The wafer level package structure according to claim 12, wherein the at least two spacer wall structures are located on two opposite sides of the die.   13. The wafer level package structure of claim 12, wherein the at least two spacer wall structures are located on two adjacent sides of the die. In the method of wafer level packaging,
Providing a semiconductor wafer having a plurality of dies, and a translucent substrate having an optical plating film;
Depositing a dielectric layer on the translucent substrate;
Depositing a photoresist layer on the dielectric layer;
Removing a portion of the photoresist layer to expose a portion of the dielectric layer;
The exposed dielectric layer and the underlying optical plating film are removed, and a plurality of spacer wall structures are formed on the light-transmitting substrate using the photoresist layer as a mask. The plurality of spacer wall structures are discontinuously arranged. And comprising the optical plating film, the optical plating film being located between the spacer wall structure and the translucent substrate,
Forming a plurality of sealants adjacent to sidewalls of a plurality of spacer wall structures;
Coating a transparent substrate with a semiconductor wafer;
A wafer level package method comprising the above steps. 16. The wafer level package method of claim 15 , wherein each die includes a sensor area, and each sealant is adjacent to a sidewall in proximity to the sensor area in each spacer wall structure. Level package method. 16. The wafer level package method of claim 15 , wherein each die includes a sensor area, and each sealant is adjacent to a sidewall remote from the sensor area in each spacer wall structure. Level package method.

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