JP4899548B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor equipment, a semiconductor device and a manufacturing method thereof in which a semiconductor element is packaged in high density and high accuracy with a particularly fine connecting pads.

  In recent years, with the increase in speed and multifunction of semiconductor elements, the number of power lines, ground lines, signal lines, and the like drawn from the semiconductor elements has been increasing. On the other hand, in the semiconductor element itself, the element size tends to decrease due to the miniaturization of the internal wiring, and accordingly, the area of the connection pad provided on the surface of the semiconductor element to connect the semiconductor element and the package substrate is reduced. Narrow pitch is progressing.

  As a result, the wiring of the package substrate on which the semiconductor element is mounted needs to be miniaturized and the pitch is narrowed. However, the miniaturization and the pitch are not catching up from the viewpoint of process and cost, and an expensive build is required. There is a need to use an up substrate. When a build-up board is used, bumps are generally used to connect the semiconductor element to the build-up board. However, from the viewpoint of electrical characteristics and connection reliability, the semiconductor element and the package are not used. A structure for connecting a substrate is desired.

  Under such circumstances, a semiconductor device has been devised in which an insulating layer is formed on a semiconductor element and a package wiring is directly drawn out via a via hole (for example, Patent Documents 1, 2, 3, and 4).

  Also, a so-called system-in-package (SiP) in which a plurality of semiconductor elements are accommodated in a single package has been devised to draw out package wiring directly from the semiconductor elements (Patent Documents 4, 5 and 6).

Japanese Patent Laid-Open No. 10-313074 JP 2001-339165 A JP 2005-045277 A Japanese Patent Laid-Open No. 2004-071998 JP 2001-217381 A JP 2002-359341 A

  However, these conventional techniques require high precision in the mounting positions of the semiconductor elements. Particularly, a plurality of semiconductor elements are mounted on a single large package substrate, and a large number of semiconductor devices are manufactured simultaneously. When a semiconductor device is manufactured by cutting into individual semiconductor devices, the semiconductor elements in which the mounting is shifted are discarded after cutting, and the mounting accuracy of each semiconductor element determines the manufacturing yield. Restricting the miniaturization of wiring, limiting the number of layers of package wiring and increasing the cost. In the case of manufacturing an SiP that accommodates a plurality of semiconductor elements 120 in one package substrate 110, for example, even one of the plurality of semiconductor elements is displaced in the mounting position of the semiconductor elements, and the connection pad When a connection failure between the via and the via occurs, the entire SiP becomes a defective product, and the cost increases remarkably.

  FIG. 4 is a schematic diagram showing a cross-sectional structure of a conventional semiconductor device 200. A semiconductor element 220 having a connection pad 221 on the surface is mounted on the package substrate 210, and an interlayer insulating film 230 including an insulating layer 234 and a via 232 is formed on the package substrate 210 and the semiconductor element 220. A first wiring layer 240 including a wiring 243, a via 242 and an insulating layer 244 is formed on the interlayer insulating film 230. The connection pad 221 of the semiconductor element 220 and the wiring 243 of the first wiring layer 240 are electrically connected by the via 232. Connected. A second wiring layer 250 is formed on the first wiring layer 240, and the wiring 243 of the first wiring layer 240 and the wiring 253 of the second wiring layer 253 are connected by a via 242.

  The via 232 connecting the connection pad 221 of the semiconductor element 220 and the wiring 243 of the first wiring layer 240 and the via 242 connecting the wiring 243 of the first wiring layer 240 and the wiring 253 of the second wiring layer 250 are all. The center line is formed so as to be substantially perpendicular to the surface of the package substrate 210. Therefore, as shown in FIG. 4, when the mounting position of the semiconductor element 220 in the horizontal direction is shifted with respect to the package substrate 210, a connection failure between the connection pad 221 and the via 232 of the semiconductor element 220 may occur. There is. In general, since the via 232 connected to the connection pad 221 of the semiconductor element 220 has a smaller diameter than the via formed in a layer above this, a slight shift in the mounting position of the semiconductor element 220 in the horizontal direction. May cause a problem.

  If the mounting accuracy of the semiconductor element 220 is poor, a connection failure between the connection pad 221 and the via 232 of the semiconductor element 220 may occur. Therefore, in order to avoid this connection failure, the wiring 243 is used to connect the via 232. There is a problem in that the land diameter of the connection land provided in the case must be increased more than necessary.

  Further, since there is a limit to miniaturization in the method of forming a via hole by laser processing, it is preferable to form a via hole by a photo via forming method using an exposure machine, but a glass mask or a film mask is used for the photo via forming method. Therefore, the position of each via cannot be controlled unlike a laser. As a result, a higher mounting accuracy of the semiconductor element 220 is required, and a connection land having a large land diameter needs to be provided in the wiring 243, which causes a problem that a wiring accommodation rate is lowered.

The present invention has been made in view of such problems, and in order to connect vias without causing contact failure of the connection pads of the semiconductor element even when the mounting position of the semiconductor element is shifted with respect to the package substrate. and to provide a method of manufacturing a semiconductor equipment is not necessary to increase the land diameter of the connection lands provided on wiring.

A method of manufacturing a semiconductor device according to the present invention includes a step of mounting a semiconductor element on a substrate, a step of forming an insulating layer on the substrate and the semiconductor element, and at least one via in the insulating layer. Forming an inclined layer with respect to the surface of the substrate, and forming a wiring connected to the via on the insulating layer, and the insulating layer on which the inclined via is to be formed includes: A plurality of photoreactive resin layers are laminated while shifting the cured portion by light irradiation, and the photoreactive resin layer is formed by an optical modeling method that removes a via hole portion .

  The insulating layer is an interlayer insulating film in contact with the substrate, and has a step of forming at least one wiring layer comprising a wiring, an insulating layer, and a via on the interlayer insulating film, and is formed on the wiring layer. The via is preferably formed so that the center line is perpendicular to the surface of the substrate.

Another method of manufacturing a semiconductor device according to the present invention includes a step of mounting a semiconductor element on a substrate, and a step of forming a plurality of wiring layers comprising an insulating layer and wiring thereon on the substrate and the semiconductor element. And forming a wiring layer closest to the semiconductor element among the wiring layers includes: forming the insulating layer; forming a via in the insulating layer; and connecting to the via. Forming at least one of the vias such that a center line is inclined with respect to the surface of the substrate, and forming the inclined vias. The insulating layer is formed by an optical modeling method in which a plurality of photoreactive resin layers are stacked while shifting a cured portion by light irradiation, and a via hole portion of the photoreactive resin layer is removed .

According to the stereolithography described above , the thermal influence on the transistor device of the semiconductor element is reduced and the deterioration of the transistor can be suppressed as compared with the method of forming the via hole by tilting by laser processing.

  According to the present invention, even when the mounting position of the semiconductor element is shifted with respect to the substrate, the connection pad of the semiconductor element does not cause poor contact, so it is not necessary to strictly control the mounting position of the semiconductor element, This eliminates the need for a highly accurate mounting machine, reduces the manufacturing cost, and improves the manufacturing yield of the semiconductor device. Furthermore, since it is not necessary to increase the land diameter of the connection land provided in the wiring for connecting the via, the wiring accommodation rate can be increased. Further, since there is no need to increase the connection pad of the semiconductor element, a general-purpose semiconductor element can be used, and it is easy to increase the number of products as SiP.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device according to the present embodiment has a package substrate 110 having a recess formed on the surface as a substrate, and a semiconductor element 120 having a connection pad 121 on the surface is mounted in the recess of the package substrate 110. . Usually, the connection pad 121 is provided with a diameter of 100 μm or less.

  An insulating layer 134 is formed on the package substrate 110 and the semiconductor element 120. A wiring 143 is formed on the insulating layer 134, the first via hole 131 for connecting the connection pad 121 of the semiconductor element 120 and the wiring 143 is formed on the insulating layer 134, and the bottom surface 131 a is a connection pad of the semiconductor element 120. An upper surface 131b is formed on 121 so as to be located at a design position of the wiring 143, and a first via 132 is formed by embedding a conductor in the first via hole 131. The connection pad 121 of the semiconductor element 120 and the wiring 143 are electrically connected by the first via 132. Here, a layer including the first via 132 and the insulating layer 134 is referred to as an interlayer insulating film 130. The interlayer insulating film 130 is in contact with the package substrate 110.

  As shown in FIG. 1A, when the mounting position of the semiconductor element 120 mounted on the package substrate 110 is shifted in the horizontal direction, the first via 132 has its center line at the center of the package substrate 110. It is formed with an inclination angle rather than perpendicular to the surface. That is, the bottom surface 131a and the top surface 131b do not completely overlap in a plan view.

  An insulating layer 144 is formed as another insulating layer on the wiring 143 formed on the interlayer insulating film 130. The wiring 153 is formed on the insulating layer 144. The wiring 143 and the wiring 153 are connected to the insulating layer 144. A via hole 141 for connection is formed. As described above, since the first via 132 is formed to be inclined, a shift in the mounting position of the semiconductor element 120 in the horizontal direction is corrected. Therefore, the mounting of the semiconductor element 120 in the horizontal direction in the via hole 141 is corrected. There is no influence of position shift. Therefore, the via hole 141 has a center line formed substantially perpendicular to the surface of the package substrate 110. A via 142 is formed by burying a conductor in the via hole 141. The wiring 143 and the wiring 153 are electrically connected by the via 142. Here, a layer including the via 142, the wiring 143, and the insulating layer 144 is referred to as a first wiring layer 140.

  Thereafter, an arbitrary number of wiring layers are formed by the same procedure. As a result, the interlayer insulating film 130 and one or more wiring layers (two layers in the illustrated example) are formed on the package substrate 110. As described above, the via formed in the layer above the first via 132, that is, the via formed in the wiring layer, is formed by tilting the first via 132 of the interlayer insulating film 130. Since the displacement of the mounting position of the element 120 in the horizontal direction is corrected, the center line is formed substantially perpendicular to the surface of the package substrate 110.

  An opening 151 reaching the wiring (wiring 153 in the illustrated example) inside the insulating layer is formed in the insulating layer (insulating layer 154 in the illustrated example) formed on the uppermost surface. A pad 160 is formed in the opening 151 by a pad base metal layer 161 and a pad upper metal layer 162, and an external terminal 170 is connected to the pad 160. The semiconductor device 100 is configured as described above. The semiconductor device 100 configured as described above is mounted on a substrate or the like via the external terminal 170.

  Next, the operation of the semiconductor device according to the first embodiment of the present invention configured as described above will be described. A semiconductor element 120 having a connection pad 121 on the surface is mounted in a recess provided on the surface of the package substrate 110, and an insulating layer 134 is formed on the package substrate 110 and the semiconductor element 120.

  Next, the first via hole 131 is formed in the insulating layer 134 so that the bottom surface 131 a is located at the design position of the wiring 143 formed on the connection pad 121 of the semiconductor element 120 and the top surface 131 b on the insulating layer 134. As shown in FIG. 1A, when the mounting position of the semiconductor element 120 mounted on the package substrate 110 is shifted in the horizontal direction, the first via hole 131 has the center line of the connection pad 121. The surface and the surface of the insulating layer 134 are not perpendicular to the surface but are formed with an inclination angle. That is, the bottom surface 131a and the top surface 131b of the first via hole 131 do not completely overlap in a plan view.

  As a method of forming a via hole having an inclination angle, for example, a method of forming by laser irradiation from an oblique direction or pushing a convex portion from an oblique direction can be used. The method is preferably used.

  Stereolithography creates a three-dimensional arbitrary shape as CAD (Computer Aided Design) data, creates slice data by cutting this CAD data parallel to the vertical direction (Z-axis direction) at regular intervals, and creates CAM (Computer Aided manufacturing) is a technique for forming a three-dimensional shape created by CAD data by irradiating and curing necessary portions of the photoreactive resin according to the slice data, repeating this process, and laminating.

  Conventionally, the slice interval in the Z-axis direction is at least 100 μm, but recently, a thin film of about several μm can be stacked, and a pattern can be formed with an accuracy of several μm even in the XY plane. A stereolithography method was developed. According to this technique, the first via hole 131 for connecting to the connection pad 121 having a diameter of 100 μm or less in the semiconductor device according to the first embodiment of the present invention can be formed.

  CAD data of the first via hole 131 connecting the actual position of the connection pad 121 formed on the surface of the semiconductor element 120 and the design position of the wiring 143 was created, and this was cut out at a constant interval parallel to the Z-axis direction. Slice data is created, light is irradiated to a portion of the photoreactive resin having insulation properties to be cured according to the slice data by CAM, and a plurality of photoreactive resin layers are stacked while shifting the cured portion by light irradiation. Thereafter, the photoreactive resin in the via hole portion is removed by etching or the like, thereby forming the insulating layer 134 having the first via hole 131. When the insulating layer 134 and the first via hole 131 are formed by stereolithography, the thermal influence on the transistor device of the semiconductor element is reduced as compared with the method of forming the first via hole 131 in the insulating layer 134 by laser processing. The deterioration of the transistor can be suppressed.

  Next, the first via 132 is formed by a method such as embedding a conductor in the first via hole 131. As a result, an interlayer insulating film 130 including the first via 132 and the insulating layer 134 is formed. The connection pad 121 of the semiconductor element 120 and the wiring 143 are electrically connected by the first via 132.

  FIG. 2 is an enlarged cross-sectional view of the first via 132 formed to be inclined by the optical modeling method described above. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. When viewed microscopically, the side surface of the first via 132 formed to be inclined by the stereolithography method has a plurality of steps in the longitudinal direction of the first via 132. At this time, the center line of the first via 132 does not need to be in one direction, the bottom surface 131a is on the connection pad 121 of the semiconductor element 120, and the upper surface 131b is not in contact with other wirings, and the design position of the wiring 143. As long as it has reached, it may face in any direction.

  Next, a wiring 143 is formed by patterning a conductive film on the interlayer insulating film 130 by plating or the like. The first via 132 can also be formed by embedding a conductive material for wiring in the first via hole 131 when the wiring 143 is formed.

  Next, the insulating layer 144 is formed over the wiring 143, and the via hole 141 is formed in the insulating layer 144. As described above, since the displacement of the mounting position of the semiconductor element 120 in the horizontal direction is corrected by forming the first via 132 in an inclined manner, the mounting of the semiconductor element 120 is performed when the via hole 141 is formed. There is no need to consider positional deviation. Therefore, the via hole 141 is formed so that its center line is substantially perpendicular to the surface of the package substrate 110.

  As a method of forming the via hole 141, for example, laser processing or a photo via forming method can be used. Since the first via 132 is formed in an inclined manner as described above, the displacement of the mounting position of the semiconductor element 120 in the horizontal direction is corrected. Therefore, even when a via hole is formed by laser processing, for example, it is provided in the wiring. Since it is not necessary to make the land diameter of the connecting lands larger than usual, the wiring accommodation rate can be increased. In addition, when forming a via hole by a photo via forming method using an exposure machine, a glass mask or a film mask produced as designed can be used, and both miniaturization and cost reduction can be achieved.

  Next, the via 142 is formed by a method such as embedding a conductor in the via hole 141. As a result, the first wiring layer 140 including the wiring 143, the via 142, and the insulating layer 144 is formed. The wiring 143 and the wiring 153 are electrically connected by the via 142.

  Next, a wiring 153 is formed by patterning a conductive film on the first wiring layer 140 by plating or the like. The via 142 can also be formed by embedding a wiring conductive material in the via hole 141 when forming the wiring 153.

  Thereafter, an arbitrary number of wiring layers are formed by the same procedure. Thus, the interlayer insulating film 130 and one or more wiring layers (two layers in the illustrated example) are formed on the package substrate 110. Vias formed in a layer above the first via 132, that is, vias formed in the wiring layer, the first via 132 of the interlayer insulating film 130 is formed in an inclined manner as described above, so that the semiconductor element 120 is formed. Since the displacement of the mounting position in the horizontal direction is corrected, the center line is formed so as to be substantially perpendicular to the surface of the package substrate 110.

  An opening 151 reaching the wiring (wiring 153 in the illustrated example) inside the insulating layer is formed in the insulating layer (insulating layer 154 in the illustrated example) formed on the uppermost surface. A pad 160 is formed in this opening 151 by forming a pad base metal layer 161 and a pad upper metal layer 162 by plating or the like, and an external terminal 171 is connected to the pad 160. The semiconductor device 100 is configured as described above. The semiconductor device 100 configured as described above is mounted on a substrate or the like via the external terminal 170.

  In the present embodiment, the semiconductor element 120 is installed in the recess of the package substrate 110 and embedded in the surface of the package substrate 110. However, the semiconductor element 120 is not necessarily installed in the recess of the package substrate 110. It is not necessary and may be mounted on a flat package substrate, or the package wiring may be formed directly on the semiconductor element 120. In this embodiment, an example is shown in which the package wiring includes three layers including the pad 160 connected to the external terminal 170, and the insulating layer includes three layers including the interlayer insulating film 130. It is not necessary that the wiring is a single layer.

  In the present embodiment, even when the mounting position of the semiconductor element 120 mounted on the package substrate 110 is shifted in the horizontal direction, the wiring 144 of the connection pad 121 and the first wiring layer 130 is provided. Are formed so as to be inclined with respect to the substrate from the connection pad 121 of the shifted semiconductor element 120, so that the upper surface 131 b of the first via 132 is positioned at the design position of the wiring 144. Thus, the first via 132 can be formed. As a result, since the displacement of the mounting position of the semiconductor element 120 in the horizontal direction is corrected, contact failure of the connection pads of the semiconductor element does not occur, and the land diameter of the connection land provided in the wiring 143 for connecting the via 132 is obtained. There is no need to increase the wiring capacity, and the wiring accommodation rate can be increased. In addition, since there is no need to increase the connection pads 121 of the semiconductor element 120, a general-purpose semiconductor element can be used, and a variety of SiPs can be easily produced.

  In addition, if the first via hole 131 and the insulating layer 134 are formed by an optical modeling method, the thermal effect on the transistor device of the semiconductor element is reduced as compared with a method in which the via hole is inclined in the insulating layer 134 by laser processing. The transistor can be reduced and deterioration of the transistor can be suppressed.

  Even if the package wiring is multi-layered, the via formed in the wiring layer is not affected by the shift of the mounting position of the semiconductor element 120 in the horizontal direction, and can be formed by a process such as a normal lithography process. This eliminates the need for significant changes in the production line.

  Next, a second embodiment of the present invention will be described. FIGS. 3A and 3B are schematic views showing a state in which the semiconductor device according to this embodiment is viewed from above. 3, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. 3, only the package substrate 110, the two semiconductor elements 120 and their connection pads 121, the first via 132, the bottom surface 131a, and the top surface 131b are shown, and the other components are not shown. .

  In the present embodiment, as shown in FIG. 3A, two semiconductor elements 120 a and 120 b are mounted side by side on one package substrate 110. With respect to the package substrate 110, one semiconductor element 120a does not shift in mounting position, and the other semiconductor element 120b has a large shifting in mounting position as shown by B in FIG. Has occurred.

  When two semiconductor elements are mounted on the package substrate 110, for example, even if one semiconductor element is mounted with high accuracy on the package substrate 110, the mounting position of the other one semiconductor element is shown in FIG. As shown by B, there may be a large shift in the mounting position.

  In the prior art, as shown in FIG. 4, the via 232 connecting the connection pad 221 of the semiconductor element 220 and the wiring 243 of the first wiring layer 240 has a center line that is substantially perpendicular to the surface of the package substrate 210. When the mounting position of the semiconductor element 220 is significantly displaced from the package substrate 210, as shown by B in FIG. 3A, the connection pad 221 and the package substrate 210 are formed. Connection failure with the via 232 occurs. That is, in FIG. 3A, a connection failure between the connection pad 121 and the via 132 occurs in the semiconductor element 120b.

  A case where a plurality of semiconductor elements 120a and 120b are mounted on one large package substrate 110 to simultaneously manufacture a large number of semiconductor devices 100 and then cut into individual semiconductor devices 100 to manufacture the semiconductor devices 100. The semiconductor element 120b in which the mounting deviation has occurred is discarded after cutting, and the mounting accuracy of each of the semiconductor elements 120a and 120b determines the manufacturing yield. If the mounting accuracy is low, miniaturization of the package wiring is restricted, and the package wiring Limit the number of layers and increase costs.

  Further, in the case of manufacturing a SiP that accommodates a plurality of semiconductor elements 120 in one package substrate 110, for example, even one of the plurality of semiconductor elements 120 is displaced in the mounting position of the semiconductor element 120, When a connection failure between the connection pad 121 and the via 132 occurs, the entire SiP becomes a defective product, and the cost increases remarkably.

  However, according to the present invention, as shown in FIG. 3B, even when a plurality of semiconductor elements 120 are mounted on the package substrate 110, the connection pads 121 of the semiconductor element 120 where the mounting position is shifted are changed. By forming the one via 132 inclined with respect to the package substrate 110, the upper surface 131 b of the first via 132 can be corrected to reach the design position of the wiring 143. Accordingly, a normal package substrate manufacturing process can be applied in the subsequent steps.

  In addition, if the above-described stereolithography is used, the insulating layer 134 can be three-dimensionally formed in an arbitrary shape. Therefore, even if the heights of the plurality of semiconductor elements 120 mounted on the package substrate 110 are different, It is possible to flatten when the resin is cured and laminated at the time of modeling. As a result, for example, in SiP, it is not necessary to align the height of a plurality of semiconductor elements, so that the thickness of a semiconductor element having particularly poor mechanical strength can be increased. As a result, the reliability of the entire SiP is improved. To do.

1 is a schematic diagram showing a cross-sectional structure of a semiconductor device 100 according to a first embodiment of the present invention. It is a cross-sectional enlarged view of the first via 132 formed by stereolithography. (A) And (b) is a schematic diagram which shows a mode that the semiconductor device which concerns on this embodiment was seen from the upper surface. It is a schematic diagram which shows the cross-section of the semiconductor device 200 of a prior art.

Explanation of symbols

100; semiconductor device 110; package substrate 120, 120a, 120b; semiconductor element 121; connection pad 130; interlayer insulating film 131; first via hole 131a; bottom surface 131b; top surface 132; 1 wiring layer 141; via hole 142; via 143; wiring 144; insulating layer 150; second wiring layer 151; opening 153; wiring 154; insulating layer 160; pad 161; pad base metal layer 162; Displacement 200 of the mounting position of the semiconductor element 120 in the horizontal direction; semiconductor device 210; package substrate 220; semiconductor element 221; connection pad 230; interlayer insulating film 232; first via 234; insulating layer 240; First wiring layer 242; via 243; wiring 244; insulation 250: second wiring layer 253; wiring

Claims (3)

A step of mounting a semiconductor element on a substrate, a step of forming an insulating layer on the substrate and the semiconductor element, and at least one via in the insulating layer so that a center line is inclined with respect to the surface of the substrate. And a step of forming a wiring connected to the via on the insulating layer, and a plurality of insulating layers in which the inclined via is to be formed are shifted while shifting a cured portion by light irradiation. A method of manufacturing a semiconductor device , wherein the photoreactive resin layer is laminated and the via hole portion of the photoreactive resin layer is removed . The insulating layer is an interlayer insulating film in contact with the substrate, and has a step of forming at least one wiring layer comprising a wiring, an insulating layer, and a via on the interlayer insulating film, and is formed on the wiring layer. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the via is formed so that a center line is perpendicular to the surface of the substrate. A step of mounting a semiconductor element on a substrate, and a step of forming a plurality of wiring layers comprising an insulating layer and wiring thereon on the substrate and the semiconductor element, and the semiconductor of the wiring layer The step of forming a wiring layer closest to the element includes the step of forming the insulating layer, the step of forming a via in the insulating layer, the step of forming a wiring connected to the via on the insulating layer, And at least one of the vias is formed so that a center line is inclined with respect to the surface of the substrate, and a plurality of insulating layers on which the inclined vias are to be formed are shifted while shifting a cured portion by light irradiation. A method for manufacturing a semiconductor device , comprising: a plurality of photoreactive resin layers; and a method of stereolithography for removing a via hole portion of the photoreactive resin layer .

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