JP2917537B2 - Mounting method of IC package for surface mounting - Google Patents

Mounting method of IC package for surface mounting

Info

Publication number
JP2917537B2
JP2917537B2 JP3015175A JP1517591A JP2917537B2 JP 2917537 B2 JP2917537 B2 JP 2917537B2 JP 3015175 A JP3015175 A JP 3015175A JP 1517591 A JP1517591 A JP 1517591A JP 2917537 B2 JP2917537 B2 JP 2917537B2
Authority
JP
Japan
Prior art keywords
package
land
mounting
wiring board
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3015175A
Other languages
Japanese (ja)
Other versions
JPH04254397A (en
Inventor
功 明石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3015175A priority Critical patent/JP2917537B2/en
Publication of JPH04254397A publication Critical patent/JPH04254397A/en
Application granted granted Critical
Publication of JP2917537B2 publication Critical patent/JP2917537B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、表面実装用ICパッケ
ージのプリント配線板への実装方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a surface mount IC package on a printed wiring board.

【0002】[0002]

【従来の技術】電子機器の小型化が促進される今日、プ
リント配線板への部品実装密度を高くするために、回路
部品として、リード線を有さない表面実装型の回路部品
を使用する例が多くなってきている。これらの表面実装
用回路部品には、抵抗,コンデンサー等の本体の両端に
電極を有するチッブ型のものや、二辺、あるいは四辺に
リード端子を持った各種ICパッケージ等がある。
2. Description of the Related Art Today, as electronic devices are being miniaturized, in order to increase the component mounting density on a printed wiring board, examples of using surface-mounted circuit components having no lead wires as circuit components. Are increasing. These surface mount circuit components include chip-type components having electrodes at both ends of a main body such as a resistor and a capacitor, and various IC packages having lead terminals on two or four sides.

【0003】これらの表面実装用部品のプリント配線板
への実装方法としては、主として、接着剤で部品を固定
した後、フローはんだによりプリント配線板のランドと
部品の電極をはんだ接合するフロー方法と、クリームは
んだをプリント配線板のランド部に塗布した後、部品を
装着し、クリームはんだを溶融、冷却・固着して、プリ
ント配線板のランドと部品の電極をはんだ接合するリフ
ロー方法とがある。表面実装用ICパッケージにおいて
は、主にクリームはんだリフローによる実装方法が用い
られることが多い。
[0003] As a method of mounting these surface mounting components on a printed wiring board, there are mainly a flow method of fixing a component with an adhesive and then soldering a land of the printed wiring board and an electrode of the component by flow soldering. There is a reflow method in which a cream solder is applied to a land portion of a printed wiring board, components are mounted, the cream solder is melted, cooled and fixed, and a land of the printed wiring board and an electrode of the component are soldered. In the surface mounting IC package, a mounting method mainly using cream solder reflow is often used.

【0004】すなわち、表面実装用ICパッケージのリ
ード端子に対応するプリント配線板のランド部分に、ス
クリーン版、あるいはディスペンサー等でクリームはん
だを塗布した後、ICパッケージを装着し、赤外線やホ
ットエアー、あるいはその他の加熱機器でクリームはん
だを溶融、冷却・固着し、ICパッケージのリード端子
とプリント配線板のランドをはんだ接合する方法であ
る。
That is, after applying cream solder to a land portion of a printed wiring board corresponding to a lead terminal of an IC package for surface mounting using a screen plate or a dispenser, the IC package is mounted, and infrared rays, hot air, or In this method, the cream solder is melted, cooled, and fixed by other heating equipment, and the lead terminals of the IC package and the lands of the printed wiring board are soldered.

【0005】この場合、一般的にはプリント配線板の各
ランドひとつひとつに対応させて、独立した開口部を持
つクリームはんだ印刷用マスクを作製し、これを用いて
個々のランドにクリームはんだを印刷・塗布するが、I
Cパッケージのリード端子のピッチが狭くなり、対応す
るランドの幅も狭くなってくると、クリームはんだ印刷
用マスクの独立した開口部も小さくなり、印刷時にクリ
ームはんだが開口部から十分転写されず、必要なクリー
ムはんだの厚み、すなわち量の確保が困難になる。さら
に、リード端子ピッチが0.5mmのICパッケージに対
応するプリント配線板のランドにおいてはクリームはん
だの量を確保するマスク厚での独立した開口部を印刷用
マスクに形成することさえ極めて困難である。
In this case, generally, a cream solder printing mask having an independent opening is prepared in correspondence with each land of the printed wiring board, and the cream solder is printed on each land using the mask. Apply, but I
When the pitch of the lead terminals of the C package becomes narrower and the width of the corresponding land becomes narrower, the independent opening of the cream solder printing mask also becomes smaller, and the cream solder is not sufficiently transferred from the opening during printing. It becomes difficult to secure the required thickness of the cream solder, that is, the amount. Furthermore, it is extremely difficult to form an independent opening in a mask having a mask thickness that secures the amount of cream solder on a land of a printed wiring board corresponding to an IC package having a lead terminal pitch of 0.5 mm. .

【0006】このため従来は、図2(a)に示すよう
に、ICパッケージの各辺のリード端子に対応したプリ
ント配線板のランド1a,1b,1c,1d,1e及び
ランド間隙を含む特定の領域すべての部分に印刷・塗布
できるようなクリームはんだ印刷用マスク7を作製し、
これを用いてクリームはんだ4を塗布し、ICパッケー
ジ装着後、リフロー時にはんだ6をランド上に凝集させ
ることにより、ICパッケージのリード端子5とプリン
ト配線板のランド1a,1b,1c,1d,1eを接合
する方法が用いられている。
For this reason, conventionally, as shown in FIG. 2A, a specific part including lands 1a, 1b, 1c, 1d, 1e of a printed wiring board corresponding to lead terminals on each side of an IC package and land gaps. A mask 7 for cream solder printing that can be printed and applied to all parts of the area is produced,
Using this, the cream solder 4 is applied, and after the IC package is mounted, the solder 6 is agglomerated on the lands during reflow, so that the lead terminals 5 of the IC package and the lands 1a, 1b, 1c, 1d, 1e of the printed wiring board are formed. Is used.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、ICパ
ッケージのリード端子に対応するプリント配線板のラン
ド形状は同一であるが、図3に示すように、プリント配
線板の表面実装用ICパッケージ用のランド1a,1
b,1c,1d,1eには長さや幅、形状の異なる種々
の導体パターン2が接続され、ソルダレジスト3が形成
されているため、ランドを含めた1導体パターン当りの
熱の伝導性は導体パターン毎に異なり、リフロー時の
際、各ランドにおける加熱状態が均一でなくなる。この
ため、図2(b)に示すようにクリームはんだ4を塗布
し、表面実装用ICパッケージのリード5を装着し、リ
フローさせる方法においては、図2(c)に示すよう
に、溶融、冷却、固着後の各ランド1a,1b,1c,
1d,1e上のはんだ6の厚みがランド毎に大きく異な
り、その接合強度にバラツキが生じ、はんだ接合の信頼
性が低下し、さらに加熱状態によっては、ランド間隙に
凝集されずに残ったはんだやはんだボールが絶縁性を劣
下させたり、電子機器の輸送や作動時の振動等で剥離
し、電子機器の作動に影響をもたらすという問題点があ
った。
However, although the land shape of the printed wiring board corresponding to the lead terminal of the IC package is the same, as shown in FIG. 3, the land for the surface mounting IC package of the printed wiring board is used. 1a, 1
Various conductive patterns 2 having different lengths, widths, and shapes are connected to b, 1c, 1d, and 1e, and a solder resist 3 is formed. Different for each pattern, the heating state in each land is not uniform during reflow. Therefore, in a method of applying the cream solder 4 as shown in FIG. 2B, mounting the leads 5 of the surface mounting IC package, and reflowing, as shown in FIG. , The fixed lands 1a, 1b, 1c,
The thickness of the solder 6 on 1d and 1e varies greatly from land to land, and the bonding strength varies, reducing the reliability of solder bonding. There has been a problem that the solder ball deteriorates the insulation property, or peels off due to vibration during transportation or operation of the electronic device, which affects the operation of the electronic device.

【0008】本発明は上記従来の問題点を解決するもの
で、クリームはんだのリフロー時にプリント配線板のI
Cパッケージ用ランドのはんだ厚みを均一にする実装方
法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems.
An object of the present invention is to provide a mounting method for making the solder thickness of a land for a C package uniform.

【0009】[0009]

【課題を解決するための手段】上記の課題を解決するた
めに本発明は、表面実装用ICパッケージの各辺のリー
ド端子に対応するプリント配線板のランド及びランド間
隙を含む特定の領域のすべての部分にクリームはんだを
塗布し、ICパッケージの装着後、クリームはんだを溶
融・固着し、ICパッケージのリード端子とプリント配
線板のランドとを接続する実装方法を用いる場合、個々
のランドに接続している導体パターンの長さ,幅,形状
の違いに応じて部分的に面積を変えてクリームはんだを
塗布する実装方法としたものである。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a method of manufacturing a printed circuit board, which corresponds to a lead terminal on each side of a surface mounting IC package. After applying the cream solder to the part, and after mounting the IC package, melting and fixing the cream solder, and using the mounting method of connecting the lead terminals of the IC package and the lands of the printed wiring board, connect to each land. This is a mounting method in which cream solder is applied while partially changing the area according to the length, width and shape of the conductor pattern.

【0010】[0010]

【作用】この方法によると、プリント配線板のランドが
接続している導体パターンの長さや幅、形状の違いによ
り、ランドを含めた1導体パターン当りの熱の伝導性が
パターン毎に異なり、リフロー時の際、各ランドにおけ
る加熱状態が均一にならない場合においても、1導体パ
ターンの熱の伝導性に応じてランド部のクリームはんだ
の塗布面積が変わり、リフローの際、独立したランドで
は熱の伝導性がよく、クリームはんだの溶融までの時間
は短く、隣接したランドが熱の伝導性のわるい場合、先
に溶融を開始し、本来隣接ランドに凝集すべきクリーム
はんだをも独立ランドが凝集するが熱の伝導性がわるい
ランドには多くのクリームはんだが塗布されているた
め、冷却・固化後の各ランドのはんだの厚みを均一化す
ることができる。
According to this method, the heat conductivity per conductor pattern including the land differs for each pattern due to the difference in length, width and shape of the conductor pattern to which the land of the printed wiring board is connected. Even when the heating condition in each land is not uniform, the area of the cream solder applied on the land changes according to the heat conductivity of one conductor pattern. The time required for melting the cream solder is short, and if the adjacent lands have poor heat conductivity, the melting lands are started first, and the independent lands agglomerate the cream solder that should be agglomerated in the adjacent lands. Since many cream solders are applied to the lands having poor heat conductivity, the thickness of the solder on each land after cooling and solidification can be made uniform.

【0011】[0011]

【実施例】以下、本発明の実施例について、図面を参照
しながら説明する。図1は、本発明の実施例の説明図で
あり、図1(a)は、プリント配線板の表面実装用IC
パッケージ用ランド部とクリームはんだ印刷用マスクと
を重ね合わせたクリームはんだ印刷直前の状態の平面
図、図1(b)は、クリームはんだを塗布し、表面実装
用ICパッケージを装着したランド部の断面図、図1
(c)は、リフロー後のランド部の断面図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory view of an embodiment of the present invention. FIG. 1 (a) shows an IC for surface mounting of a printed wiring board.
FIG. 1B is a plan view of a state immediately before the printing of the cream solder in which the package land and the cream solder printing mask are superimposed, and FIG. 1B is a cross-section of the land where the cream solder is applied and the surface mounting IC package is mounted. Figure, Figure 1
(C) is a sectional view of a land portion after reflow.

【0012】図1において、図2と同一箇所には同一番
号を付与し説明は略する。8は本発明の実装方法を可能
とするクリームはんだ印刷用マスク、8aはクリームは
んだ印刷用マスクの切り欠き部である。
In FIG. 1, the same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 8 denotes a cream solder printing mask that enables the mounting method of the present invention, and reference numeral 8a denotes a cutout portion of the cream solder printing mask.

【0013】以上のように構成された表面実装用ICパ
ッケージの実装方法について、図1(a),(b),
(c)を用いて説明をする。まず、従来の製造方法によ
り絶縁基板上に導体パターン2、ランド1a,1b,1
c,1d,1eやソルダレジスト3を形成し、プリント
配線板を得る。次に、ランド1a,1b,1c,1d,
1e及びランド間隙を含む特定の領域において幅の広い
回路と接続しているランド1aや長さの長い導体パター
ン2と接続しているランド1eに対応する部分を除いた
部分に切り欠き部8aを設けたアートワークフィルムを
用いることにより部分的に面積を変えたクリームはんだ
印刷用マスク8を作製する。ランドのピッチが0.5m
m、ランド幅が0.25mm、ランド間隙が0.25mmの
表面実装用ランドに対して、クリームはんだ印刷用マス
ク8の領域としては、ランド列の外周部より、片側に
0.2mm大きく、切り欠き部8aは、片側に0.15mm
だけ切り欠いた形状のクリームはんだ印刷用マスク8と
している。このクリームはんだ印刷用マスク8を用いて
クリームはんだ4を印刷・塗布した後、表面実装用IC
パッケージのリード端子5をランド1a,1b,1c,
1d,1eに位置合わせ後、装着し、赤外線リフロー方
式等の方法によりクリームはんだ4を溶融させ、冷却・
固化し、表面実装用ICパッケージのリード端子5とプ
リント配線板のランド1a,1b,1c,1d,1eと
をはんだ接合し、ICパッケージの実装を完了する。図
1(c)に示すように、その接合部は、従来の方法では
ランド表面からのはんだ厚みが最小のランドと最大のラ
ンドとの厚み差は約80μmあったが、本発明の方法で
は、30〜40μmとより均一な厚みのはんだ10で接
合することを実現させることができた。
FIGS. 1 (a), 1 (b), and 1 (b) show a method of mounting the surface mounting IC package configured as described above.
This will be described with reference to FIG. First, a conductor pattern 2 and lands 1a, 1b, 1 are formed on an insulating substrate by a conventional manufacturing method.
The printed wiring board is obtained by forming c, 1d, 1e and the solder resist 3. Next, the lands 1a, 1b, 1c, 1d,
In a specific region including the land 1e and the land gap, a cutout 8a is formed in a portion excluding a portion corresponding to the land 1a connected to the wide circuit and the land 1e connected to the conductor pattern 2 having a long length. The cream solder printing mask 8 whose area is partially changed by using the provided artwork film is manufactured. Land pitch 0.5m
For a surface mounting land having a land width of 0.25 mm and a land gap of 0.25 mm, the area of the mask 8 for cream solder printing is 0.2 mm larger on one side than the outer periphery of the land row. Notch 8a is 0.15mm on one side
The cream solder printing mask 8 has a notched shape. After printing and applying the cream solder 4 using the cream solder printing mask 8, the surface mounting IC
The lead terminals 5 of the package are connected to the lands 1a, 1b, 1c,
After alignment with 1d and 1e, it is mounted, and the cream solder 4 is melted by a method such as an infrared reflow method and cooled.
After solidification, the lead terminals 5 of the surface mounting IC package and the lands 1a, 1b, 1c, 1d, 1e of the printed wiring board are soldered to complete the mounting of the IC package. As shown in FIG. 1 (c), the difference in thickness between the land with the smallest solder thickness and the land with the largest solder thickness from the land surface in the conventional method was about 80 μm, but in the method of the present invention, Bonding with the solder 10 having a more uniform thickness of 30 to 40 μm was realized.

【0014】[0014]

【発明の効果】以上のように本発明は、表面実装用IC
パッケージのリード端子とプリント配線板との接合部分
のはんだ厚みに均一性をもたせることが可能となり、接
合強度のバラツキが抑制でき、はんだ接合の信頼性を向
上させることのできる優れた実装方法を実現できるもの
である。
As described above, the present invention relates to a surface mount IC.
It is possible to provide uniform solder thickness at the joints between the package lead terminals and the printed wiring board, suppress variations in joint strength, and realize an excellent mounting method that can improve solder joint reliability. You can do it.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は本発明の実施例におけるプリント配線
板の表面実装用ICパッケージ用ランド部とクリームは
んだ印刷用マスクとを重ね合わせたクリームはんだ印刷
直前の状態の平面図 (b)は同実施例におけるクリームはんだを塗布し、表
面実装用ICパッケージを装着したランド部の断面図 (c)は同実施例におけるリフロー後のランド部の断面
FIG. 1 (a) is a plan view showing a state immediately before cream solder printing in which a land portion for a surface mounting IC package of a printed wiring board and a cream solder printing mask are overlapped in an embodiment of the present invention. Sectional view of the land portion where the cream solder is applied in the embodiment and the IC package for surface mounting is mounted. (C) is a cross-sectional view of the land portion after reflow in the embodiment.

【図2】(a)は従来のプリント配線板の表面実装用I
Cパッケージ用ランド部とクリームはんだ印刷用マスク
とを重ね合わせたクリームはんだ印刷直前の状態の平面
図 (b)は従来のクリームはんだを塗布し、表面実装用I
Cパッケージを装着したランド部の断面図 (c)は従来のリフロー後のランド部の断面図
FIG. 2 (a) shows a conventional printed wiring board surface mount I.
The plan view of the state immediately before the cream solder printing in which the land portion for the C package and the mask for the cream solder printing are superimposed on each other is shown in FIG.
Sectional view of land part with C package mounted (c) Sectional view of land part after conventional reflow

【図3】プリント配線板の表面実装用ICパッケージ用
ランド部の平面図
FIG. 3 is a plan view of a land portion for an IC package for surface mounting of a printed wiring board.

【符号の説明】[Explanation of symbols]

1a プリント配線板の表面実装用ICパッケージ用ラ
ンド 1b プリント配線板の表面実装用ICパッケージ用ラ
ンド 1c プリント配線板の表面実装用ICパッケージ用ラ
ンド 1d プリント配線板の表面実装用ICパッケージ用ラ
ンド 1e プリント配線板の表面実装用ICパッケージ用ラ
ンド 2 導体パターン 3 ソルダレジスト 4 クリームはんだ 5 表面実装用ICパッケージのリード端子 6 冷却・固化後のはんだ 8 クリームはんだ印刷用マスク 8a 切り欠き部
1a Land for IC package for surface mounting of printed wiring board 1b Land for IC package for surface mounting of printed wiring board 1c Land for IC package for surface mounting of printed wiring board 1d Land for IC package for surface mounting of printed wiring board 1e Printing Land for IC package for surface mounting of wiring board 2 Conductor pattern 3 Solder resist 4 Cream solder 5 Lead terminal of IC package for surface mounting 6 Solder after cooling and solidification 8 Mask for cream solder printing 8a Notch

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 他の導体パターンとの接続のない独立し
たランドと、長さ、幅、形状が異なる導体パターンと接
続した個々のランドを有するプリント配線板であって、 前記プリント配線板の個々のランド及びランド間隙を含
む特定の領域のすべての部分に印刷用マスクを介してク
リームはんだを塗布し、ICパッケージの装着後、クリ
ームはんだを溶融させて、表面実装用ICパッケージの
リード端子とプリント配線板のランドとを接続する表面
実装用ICパッケージの実装方法において、 独立したランドおよび接続した導体パターンの長さ、
幅、形状の違いによる個々のランドの熱伝導性の違いに
対応した切り欠き部を有する印刷用マスクを介してクリ
ームはんだを塗布することを特徴とする表面実装用IC
パッケージの実装方法。
An independent, non-connected conductor pattern
Lands and conductor patterns with different lengths, widths and shapes.
A printed wiring board having individual lands connected thereto, including individual lands and land gaps of the printed wiring board.
All parts of a specific area through a printing mask.
After applying the solder paste and mounting the IC package,
Melts the solder for the
Surface to connect lead terminals and printed circuit board lands
In the mounting method of the mounting IC package, the length of the independent land and the length of the connected conductor pattern,
Difference in thermal conductivity between individual lands due to differences in width and shape
Clear through a printing mask with a corresponding notch
IC for surface mounting, characterized by applying a solder paste
Package implementation method.
JP3015175A 1991-02-06 1991-02-06 Mounting method of IC package for surface mounting Expired - Fee Related JP2917537B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3015175A JP2917537B2 (en) 1991-02-06 1991-02-06 Mounting method of IC package for surface mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3015175A JP2917537B2 (en) 1991-02-06 1991-02-06 Mounting method of IC package for surface mounting

Publications (2)

Publication Number Publication Date
JPH04254397A JPH04254397A (en) 1992-09-09
JP2917537B2 true JP2917537B2 (en) 1999-07-12

Family

ID=11881477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3015175A Expired - Fee Related JP2917537B2 (en) 1991-02-06 1991-02-06 Mounting method of IC package for surface mounting

Country Status (1)

Country Link
JP (1) JP2917537B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4773497B2 (en) * 2008-11-07 2011-09-14 株式会社タムラ製作所 Masking material, solder paste printing method using the masking material, and solder bump forming method

Also Published As

Publication number Publication date
JPH04254397A (en) 1992-09-09

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