JP3895020B2 - Method for forming conductive bump - Google Patents

Method for forming conductive bump Download PDF

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Publication number
JP3895020B2
JP3895020B2 JP29698697A JP29698697A JP3895020B2 JP 3895020 B2 JP3895020 B2 JP 3895020B2 JP 29698697 A JP29698697 A JP 29698697A JP 29698697 A JP29698697 A JP 29698697A JP 3895020 B2 JP3895020 B2 JP 3895020B2
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Japan
Prior art keywords
support substrate
conductive
semiconductor device
mounting
forming
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JP29698697A
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JPH11135671A (en
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賢司 笹岡
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

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  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は導電性バンプの形成方法、半導体装置および実装回路装置に関する。
【０００２】
【従来の技術】
実装回路装置は、回路機構もしくは機器類のコンパクト化や高容量化など図ることができるため、各種の電子機器類に広く使用されている。そして、この種の実装回路装置においては、組み立て，製造工程の簡略化、さらにはコンパクト化など図り易いことから、半導体装置などの電子部品を搭載・実装した構成と成っている。
【０００３】
図３は、実装回路装置の構成に使用されている半導体装置の要部構成を断面的に示したもので、１は所要の導体パッドを一主面に有する支持基板（キャリア基板）、２は前記支持基板１の一主面の導体パッドに入出力端子を対応・位置合せして搭載された半導体素子、３は前記支持基板１の他主面に導出・配置された端子、４は前記端子３面に形成された接続用の半田バンプ、５は前記半導体素子２を封止する樹脂層である。
【０００４】
上記構成の半導体装置は、実装回路用配線基板（実装用配線板本体）に対する搭載・実装において、たとえばリード端子を側面から延設した構成の場合に比べて、接続端子が垂直方向に設定されているため、搭載・実装領域を低減できるという利点がある。
【０００５】
【発明が解決しようとする課題】
しかしながら、上記構成の半導体装置においては、次のような不都合な問題がある。すなわち、最終的には、構成した実装回路装置として、十分な実装・接続の信頼性が確保される必要がある。そのためには、半田バンプ４の高さや大きさなどにバラツキがあってはならない。しかし、実際的に、これらを一様に形成することは困難で、接続実装部が微細化するほど、接続不良の発生が起こっている。たとえば、図３に図示した半導体装置の場合、大きい半田バンプ４1 に隣接する比較的小さい半田バンプ４2 は、半田バンプ４1 の表面張力に押されて、対応する導電パッドと接触しないことがしばしば起こり、接続不良を招来する恐れが多分にある。
【０００６】
こうした問題を解決するため、図４に断面的に示すごとく、端子３面に半田層６を介して、予め、球状に形成された半田ボールやCuボールなどの金属ボール７を配置し、この金属ボール７によって高さや大きさをコントロールする方式が提案されている。この方式は、前記金属ボールが一定の寸法・形状であることが前提になり、金属ボール７の大きさにバラツキがあると、接続不良などが発生して、実装回路装置の信頼性が損なわれ易い。つまり、一定の寸法・形状の金属ボール７を安定的に形成することは、プロセスが煩雑で、量産性が劣るだけでなく、コスト面からも多くの問題があって、実用的な手段とはいい難い。
【０００７】
本発明は上記事情に対処してなされたもので、突起電極の高さのバラツキに起因する接続の信頼性を改善できる導電性バンプの形成方法の提供を目的とする。
【０００８】
【課題を解決するための手段】
本発明は、表面に多数の電極が導出配置され、かつ半導体素子の搭載領域を有する支持基板に、所定の寸法および形状の開口部を前記電極に対応させて形設してなるマスクを、前記支持基板の電極に前記マスクの前記開口部を対応させて載置し、スクリーン印刷により前記電極面に導電性組成物の突起を形成する工程と、前記形成した突起の先端側に、平坦面を有する板を前記支持基板と平行に載置し、前記形成したすべての突起の先端が前記平坦面に接触する程度に加圧する工程と、前記加圧する工程を経た突起の外周面に無電解メッキ処理を施して金属バリア層を形成する工程と、前記金属バリア層の外周面に半田層を形成する工程とを有する導電性バンプの形成方法である。
【００１２】
本発明は、半導体装置の入出力用端子面の接続用バンプが、所定寸法・形状に形成し易い導電性組成物を芯体とし、この芯体外周面をメッキ層で被覆した複層構造に形成した点で特徴付けられる。すなわち、支持基板の入出力用端子（電極）面に、たとえばスクリーン印刷で導電性組成物（導電ペースト）を印刷し、ほぼ一定高さ・形状の導電性組成物の突起（導電性バンプ）を形成してから、乾燥・硬化させて成る芯体と、この芯体を被覆する半田層とで形成されている。ここで、導電性バンプの高さをほぼ一定にする手段は、導電性バンプ群の形成面に、平坦面を有する板を支持基板面と平行に載置し加圧するなどの加工・調整が挙げられる。また、導電性組成物は、たとえばAg粉末などの導電性粉末およびエポキシ樹脂などのバインダー成分で調製されたものであり、さらに、半田層は無電解メッキ法や溶融塗布法などで形成される。
【００１３】
なお、実際的には、前記半田層の下地として、たとえば無電解Cuメッキ法などで、金属バリア層を形成しておくのが好ましい。すなわち、芯体を成す導電性組成物が半田付け性良好の場合は、金属バリア層の形成を省略でき、この金属バリア層の省略で、生産性などの向上を図ることができる。
【００１４】
本発明において、配線板本体は、たとえばアルミナなどのセラミックスを層間絶縁体として形成されたセラミックス系厚膜多層配線板、ポリイミド樹脂を層間絶縁体として形成されたポリイミド樹脂系薄膜多層配線板、もしくはこれらの複合型配線板やガラスクロスエポキシ樹脂を絶縁基材としたガラスエポキシ系多層配線板などが挙げられる。
【００１５】
本発明では、高さ・形状などのバラツキが大幅に低減・解消され、高品位な導電性バンプを安定的、かつ量産的に製造することが可能となる。すなわち、導電性バンプは、たとえば導電性組成物のスクリーン印刷などによって、所定寸法・形状に形成された芯体をベースとし、芯体を半田メッキ層で被覆した構成を採っているため、高さ・形状などのバラツキが大幅に低減・解消された導電性バンプが容易に、かつ再現性よく形成できる。
【００１６】
本発明を用いて半導体装置の接続用バンプを形成した場合には、配線板本体面に接続する入出力用端子面の導電性バンプが、その高さや大きさなどのバラツキが低減ないし解消されているため、隣接する端子同士間での短絡発生も回避され、かつ信頼性の高い電気的な接続・実装が容易に確保される。
【００１７】
本発明により形成した導電性バンプを用いて半導体装置を実装用配線板本体に接続した場合には、その実装用回路装置は、半導体装置における接続用導電性バンプのバラツキが低減ないし解消されているため、信頼性の高い接続・実装が容易に形成され、より安定した実装回路装置として機能する。
【００１８】
【発明の実施の形態】
以下図１ (a)， (b)および図２を参照して実施例を説明する。
【００１９】
図１ (a)は、この実施例に係る半導体装置の要部構成を示す断面図、図１ (b)は同じく半導体装置の要部構成を一部拡大して示す断面図である。
【００２０】
図１ (a)， (b)において、８は支持基板、９は前記支持基板８の一主面に搭載された半導体素子、10は前記支持基板８の他主面に導出配置された入出力用端子（電極）、11は前記入出力用端子（電極）10面に形成された接続用の導電性バンプである。ここで、接続用の導電性バンプ11は、図１ (b)に示すごとく、導電性組成物の突起 11aを芯体とし、外表面をメッキ形成したバリアメタル層 11b、溶融塗布した半田層 11cが順次被覆した構造と成っている。
【００２１】
次に、上記接続用導電性バンプ11の製造方法例を説明する。
【００２２】
先ず、一主面が半導体素子の搭載可能に形成され、他主面に入出力用の端子10が導出・配置された支持基板８を用意する一方、厚さ 300μm のステンレス鋼板に、径 400μm の開口を多数個形設して成るマスクを用意する。次に、前記支持基板８の端子10導出・配置面に、前記マスクを位置合せ・配置し、導電性ペースト（たとえばAgペースト、フジクラ化成社製）をスクリーン印刷する。すなわち、前記支持基板８の各端子10面に、導電性ペーストを３回スクリーン印刷して、高さ 250μm の円錐状の突起を形成し、その後、 150℃のオーブン中に約30分間放置して、導電性の突起を乾燥・硬化させる。
【００２３】
次いで、前記導電性バンプ 11aを形成した面に、所要のマスキングを行ってから、露出させてある各導電性バンプ 11aの外周面に、無電解Cuメッキによって、厚さ 3μm 程度の金属バリア層 11bを被覆・形成した。さらに、前記金属バリア層 11bの外周面に、ホットエアーレベラーを用いて厚さ15μm 程度の半田層 11cをコーティングした。なお、ホットエアーレベラーを用いる代りに、無電解めっき法やスーパージャフィト法など他の半田層を形成する手段であってもよい。
【００２４】
上記形成した各導電性バンプ11の高さ、形状などを光学的に測定評価したところ、それらの寸法・形状のバラツキは± 3％程度の範囲内にあり、全体的にほぼ一様な導電性バンプ11であった。
【００２５】
上記導電性バンプ11を端子10に形成した支持基板８に、半導体素子９を搭載し、さらに、要すれば封止用の樹脂12で封止することにより、図１ (a)に図示したような半導体装置13が構成される。
【００２６】
図２は、面実装用配線板14の所定領域面に、上記構成の半導体装置13を、搭載・実装して成る実装回路装置の要部構成例を断面的に示したもので、実装・製造工程は、通常実施されている手段である。
【００２７】
前記構成の実装回路装置について、常套的に行われている電気的な試験評価、たとえば熱（ 125℃，30分間）・冷（−65℃，30分間）を１サイクルとし、2000サイクルのテストなど行ったところ、接続抵抗の変化は±10％以内であり、不良の発生は認められず良好な結果が得られた。
【００２８】
なお、上記において、単一の支持基板８の端子10面に、導電性バンプ11を形成する例を示したが、支持基板８が多面取りに形成されている場合でも、同様に形成できる。また、導電性組成物からなる芯体 11aの形成は、スクリーン印刷法によることが好ましいけれど、制御によってはディスペンス方式でおこなうこともできる。
【００２９】
本発明は上記実施例に限定されるものでなく、発明の趣旨を逸脱しない範囲でいろいろの変形を採ることができる。たとえば配線板は、アルミナ系の他、窒化アルミ系，窒化ケイ素系、ガラスエポキシに代表される樹脂系などでもよい。
【００３０】
【発明の効果】
本発明によれば、高さ・形状などのバラツキが大幅に低減・解消され、高品位な導電性バンプを備えた支持基板を量産的に提供できる。すなわち、スクリーン印刷などによって、所定寸法・形状に形成された芯体をベースとし、芯体を半田層で被覆した構成を採るため、高さ・形状などのバラツキが大幅に低減・解消された導電性バンプが容易に、かつ再現性よく提供できる。
【００３１】
本発明により形成した導電性バンプを半導体装置の接続用バンプとして用いた場合には、隣接する端子同士間での短絡発生も回避され、配線板本体面に搭載・実装した場合、信頼性の高い電気的な接続・実装が容易に確保されるので、高品質な実装回路装置などの提供が可能となる。
【００３２】
本発明により形成した導電性バンプを用いて半導体装置を接続した場合の実装用回路装置は、半導体装置における接続用導電性バンプのバラツキが低減ないし解消されているため、信頼性の高い接続・実装が容易に形成され、より安定した実装回路装置として機能する。
【図面の簡単な説明】
【図１】 (a)は実施例に係る半導体装置の要部構成を示す断面図、 (b)は半導体装置の導電性バンプの構成を拡大して示す断面図。
【図２】実施例に係る実装回路装置の要部構成を示す断面図。
【図３】従来の半導体装置の要部構成例を示す断面図。
【図４】従来の他の半導体装置の要部構成例を示す断面図。
【符号の説明】
１，８……支持基板
２，９……半導体素子
３，10……半導体装置の入出力用端子（電極）
４……半田バンプ
５，12……封止樹脂層
６……半田層
７……金属ボール
11……導電性バンプ
11a……芯体
11b……金属バリア層
11c……半田層
13……半導体装置
14……実装用配線板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a conductive bump, a semiconductor device, and a mounting circuit device.
[0002]
[Prior art]
The mounted circuit device is widely used in various electronic devices because the circuit mechanism or devices can be made compact and have a high capacity. In this type of mounted circuit device, since it is easy to achieve assembly, manufacturing process simplification, and further compactness, it has a configuration in which an electronic component such as a semiconductor device is mounted and mounted.
[0003]
FIG. 3 is a cross-sectional view of a main part configuration of a semiconductor device used in the configuration of a mounted circuit device. Reference numeral 1 denotes a support substrate (carrier substrate) having a required conductor pad on one main surface. A semiconductor element in which input / output terminals are mounted in correspondence with and aligned with conductor pads on one main surface of the support substrate 1, 3 is a terminal led out and arranged on the other main surface of the support substrate 1, and 4 is the terminal. Solder bumps 5 for connection formed on the three surfaces are resin layers for sealing the semiconductor element 2.
[0004]
In the semiconductor device having the above configuration, the connection terminals are set in the vertical direction in mounting / mounting on the mounting circuit wiring board (mounting wiring board body), for example, as compared with the case where the lead terminals are extended from the side surface. Therefore, there is an advantage that the mounting / mounting area can be reduced.
[0005]
[Problems to be solved by the invention]
However, the semiconductor device having the above configuration has the following disadvantages. That is, finally, it is necessary to ensure sufficient mounting and connection reliability as a configured mounting circuit device. For this purpose, the height and size of the solder bumps 4 should not vary. However, in practice, it is difficult to form them uniformly. As the connection mounting portion becomes finer, connection failures occur. For example, in the case of the semiconductor device illustrated in FIG. 3, is a relatively small solder bumps 4 2 adjacent to large solder bumps 4 1, by being pressed by the solder bump 4 1 surface tension, it does not contact the corresponding conductive pads Often there is a risk of poor connectivity, often occurring.
[0006]
In order to solve such a problem, as shown in a cross-sectional view in FIG. 4, a metal ball 7 such as a solder ball or a Cu ball formed in a spherical shape in advance is disposed on the surface of the terminal 3 via a solder layer 6. A method of controlling the height and size with the ball 7 has been proposed. This method is based on the premise that the metal ball has a certain size and shape. If the size of the metal ball 7 varies, connection failure occurs and the reliability of the mounted circuit device is impaired. easy. In other words, the stable formation of the metal balls 7 having a certain size and shape is not only complicated in process and inferior in mass productivity, but also has many problems in terms of cost. It ’s not good.
[0007]
The present invention has been made to address the above circumstances, and an object thereof is to provide a formation how conductive bump that can improve the reliability of the connection due to variation in the height of the bump electrode.
[0008]
[Means for Solving the Problems]
According to the present invention, there is provided a mask formed by forming an opening having a predetermined size and shape corresponding to the electrode on a support substrate having a plurality of electrodes led out on the surface and having a semiconductor element mounting region. A step of placing the opening of the mask in correspondence with the electrode of the support substrate, forming a projection of the conductive composition on the electrode surface by screen printing , and a flat surface on the tip side of the formed projection A plate having a plate in parallel with the support substrate, and pressurizing to the extent that the tips of all the formed protrusions are in contact with the flat surface; and an electroless plating process on the outer peripheral surface of the protrusion that has undergone the pressing step And forming a metal barrier layer and forming a solder layer on the outer peripheral surface of the metal barrier layer.
[0012]
The present invention provides a multi-layer structure in which the connection bumps on the input / output terminal surfaces of the semiconductor device have a conductive composition that can be easily formed in a predetermined size and shape as a core, and the outer peripheral surface of the core is covered with a plating layer. Characterized by the points formed. That is, a conductive composition (conductive paste) is printed on the input / output terminal (electrode) surface of the support substrate by, for example, screen printing, and a projection (conductive bump) of the conductive composition having a substantially constant height and shape is formed. After forming, the core body is formed by drying and curing, and a solder layer covering the core body. Here, as a means for making the height of the conductive bumps substantially constant, processing / adjustment such as placing and pressing a plate having a flat surface parallel to the support substrate surface on the formation surface of the conductive bump group can be cited. It is done. The conductive composition is prepared with conductive powder such as Ag powder and a binder component such as epoxy resin, and the solder layer is formed by electroless plating or melt coating.
[0013]
In practice, it is preferable to form a metal barrier layer as the base of the solder layer, for example, by electroless Cu plating. That is, when the conductive composition forming the core body has good solderability, the formation of the metal barrier layer can be omitted, and the productivity can be improved by omitting the metal barrier layer.
[0014]
In the present invention, the wiring board main body is, for example, a ceramic thick film multilayer wiring board formed of ceramics such as alumina as an interlayer insulator, a polyimide resin thin film multilayer wiring board formed of polyimide resin as an interlayer insulator, or these And a glass epoxy multilayer wiring board using a glass cloth epoxy resin as an insulating base.
[0015]
In the present invention, variations in height, shape, and the like are greatly reduced and eliminated, and high-quality conductive bumps can be stably and mass-produced. That is, the conductive bump has a structure in which the core body is coated with a solder plating layer based on a core body formed in a predetermined size and shape by screen printing of a conductive composition, for example. -Conductive bumps with greatly reduced and eliminated variations in shape, etc. can be easily and reproducibly formed.
[0016]
When bumps for connection of a semiconductor device are formed using the present invention, variations in height and size of the conductive bumps on the input / output terminal surface connected to the wiring board body surface are reduced or eliminated. Therefore, occurrence of a short circuit between adjacent terminals can be avoided, and highly reliable electrical connection / mounting can be easily ensured.
[0017]
When the semiconductor device is connected to the mounting wiring board body using the conductive bump formed according to the present invention, the mounting circuit device has reduced or eliminated variations in the conductive bump for connection in the semiconductor device. Therefore, highly reliable connection and mounting are easily formed, and the device functions as a more stable mounting circuit device.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment will be described below with reference to FIGS. 1 (a), 1 (b) and FIG.
[0019]
FIG. 1A is a cross-sectional view showing a main part configuration of a semiconductor device according to this embodiment, and FIG. 1B is a cross-sectional view showing a part of the main part configuration of the semiconductor device in an enlarged manner.
[0020]
1A and 1B, 8 is a support substrate, 9 is a semiconductor element mounted on one main surface of the support substrate 8, and 10 is an input / output led out on the other main surface of the support substrate 8. The connection terminals (electrodes) 11 are conductive bumps for connection formed on the surface of the input / output terminal (electrode) 10. Here, as shown in FIG. 1B, the conductive bump 11 for connection has a barrier metal layer 11b formed by plating the outer surface with a projection 11a of the conductive composition as a core, and a solder layer 11c melt-coated. Has a structure of sequentially covering.
[0021]
Next, an example of a method for manufacturing the connection conductive bump 11 will be described.
[0022]
First, a support substrate 8 having one main surface formed so that a semiconductor element can be mounted and an input / output terminal 10 led out and arranged on the other main surface is prepared, while a 300 μm-thick stainless steel plate is provided with a diameter of 400 μm. A mask having a large number of openings is prepared. Next, the mask is aligned and arranged on the terminal 10 lead-out / placement surface of the support substrate 8, and a conductive paste (for example, Ag paste, manufactured by Fujikura Kasei Co., Ltd.) is screen printed. That is, a conductive paste is screen-printed three times on the surface of each terminal 10 of the support substrate 8 to form a conical protrusion having a height of 250 μm, and then left in an oven at 150 ° C. for about 30 minutes. Dry and harden the conductive protrusions.
[0023]
Next, after performing necessary masking on the surface on which the conductive bumps 11a are formed, a metal barrier layer 11b having a thickness of about 3 μm is formed on the outer peripheral surface of each exposed conductive bump 11a by electroless Cu plating. Was coated and formed. Further, the outer peripheral surface of the metal barrier layer 11b was coated with a solder layer 11c having a thickness of about 15 μm using a hot air leveler. Instead of using a hot air leveler, other means for forming a solder layer such as an electroless plating method or a superjaphit method may be used.
[0024]
When the height, shape, etc. of each of the conductive bumps 11 formed were measured and evaluated optically, their dimensional and shape variation was in the range of about ± 3%, and the overall conductivity was almost uniform. It was bump 11.
[0025]
As shown in FIG. 1A, the semiconductor element 9 is mounted on the support substrate 8 on which the conductive bumps 11 are formed on the terminals 10 and further sealed with a sealing resin 12 if necessary. The semiconductor device 13 is configured.
[0026]
FIG. 2 is a sectional view showing an example of a configuration of a main part of a mounting circuit device in which the semiconductor device 13 having the above-described configuration is mounted and mounted on a predetermined area surface of the surface mounting wiring board 14. A process is a means normally implemented.
[0027]
For the mounted circuit device having the above-described configuration, a conventional electrical test evaluation, for example, a cycle of heat (125 ° C., 30 minutes) and cold (−65 ° C., 30 minutes), 2000 cycles, etc. As a result, the change in the connection resistance was within ± 10%, and no good defect was observed, and good results were obtained.
[0028]
In the above description, an example in which the conductive bumps 11 are formed on the surface of the terminal 10 of the single support substrate 8 has been described. However, even when the support substrate 8 is formed in multiple planes, it can be formed in the same manner. In addition, the core 11a made of the conductive composition is preferably formed by a screen printing method, but may be performed by a dispensing method depending on the control.
[0029]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. For example, the wiring board may be an alumina-based, aluminum nitride-based, silicon nitride-based, resin-based resin typified by glass epoxy, or the like.
[0030]
【The invention's effect】
According to the present invention, variations in height, shape, and the like are greatly reduced or eliminated, and a support substrate having high-quality conductive bumps can be provided in a mass production. In other words, the core body formed in a predetermined size and shape by screen printing etc. is used as the base, and the core body is covered with the solder layer, so that the variation in height and shape is greatly reduced and eliminated. Can be provided easily and with good reproducibility.
[0031]
When the conductive bump formed according to the present invention is used as a bump for connection of a semiconductor device, occurrence of a short circuit between adjacent terminals is avoided, and when mounted / mounted on the surface of the wiring board body, the reliability is high. Since electrical connection and mounting can be easily ensured, it is possible to provide a high-quality mounting circuit device and the like.
[0032]
In the mounting circuit device when the semiconductor device is connected using the conductive bump formed according to the present invention, the variation in the conductive bump for connection in the semiconductor device is reduced or eliminated. Is easily formed and functions as a more stable mounting circuit device.
[Brief description of the drawings]
FIG. 1A is a cross-sectional view showing a main part configuration of a semiconductor device according to an embodiment, and FIG. 1B is an enlarged cross-sectional view showing a configuration of conductive bumps of the semiconductor device.
FIG. 2 is a cross-sectional view showing the main configuration of a mounting circuit device according to an embodiment.
FIG. 3 is a cross-sectional view illustrating a configuration example of a main part of a conventional semiconductor device.
FIG. 4 is a cross-sectional view showing a configuration example of a main part of another conventional semiconductor device.
[Explanation of symbols]
1, 8... Support substrate 2, 9... Semiconductor element 3, 10... Input / output terminal (electrode) of semiconductor device
4 ... Solder bump 5, 12 ... Sealing resin layer 6 ... Solder layer 7 ... Metal ball
11 …… Conductive bump
11a …… Core
11b …… Metal barrier layer
11c …… Solder layer
13 …… Semiconductor device
14 …… Wiring board for mounting

Claims (1)

表面に多数の電極が導出配置され、かつ半導体素子の搭載領域を有する支持基板に、所定の寸法および形状の開口部を前記電極に対応させて形設してなるマスクを、前記支持基板の電極に前記マスクの前記開口部を対応させて載置し、スクリーン印刷により前記電極面に導電性組成物の突起を形成する工程と、
前記形成した突起の先端側に、平坦面を有する板を前記支持基板と平行に載置し、前記形成したすべての突起の先端が前記平坦面に接触する程度に加圧する工程と、
前記加圧する工程を経た突起の外周面に無電解メッキ処理を施して金属バリア層を形成する工程と、
前記金属バリア層の外周面に半田層を形成する工程と
を有する導電性バンプの形成方法。A mask in which an opening having a predetermined size and shape is formed corresponding to the electrode on a support substrate having a large number of electrodes led out on the surface and having a semiconductor element mounting region. And placing the openings of the mask in correspondence with each other, and forming projections of the conductive composition on the electrode surface by screen printing;
A step of placing a plate having a flat surface on the tip side of the formed protrusions in parallel with the support substrate, and pressurizing the tips of all the formed protrusions to contact the flat surface;
Forming a metal barrier layer by subjecting the outer peripheral surface of the protrusion subjected to the pressurizing step to electroless plating treatment;
Forming a solder layer on the outer peripheral surface of the metal barrier layer.
JP29698697A 1997-10-29 1997-10-29 Method for forming conductive bump Expired - Fee Related JP3895020B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29698697A JP3895020B2 (en) 1997-10-29 1997-10-29 Method for forming conductive bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29698697A JP3895020B2 (en) 1997-10-29 1997-10-29 Method for forming conductive bump

Publications (2)

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JPH11135671A JPH11135671A (en) 1999-05-21
JP3895020B2 true JP3895020B2 (en) 2007-03-22

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Publication number Priority date Publication date Assignee Title
KR100873041B1 (en) * 2002-06-12 2008-12-09 삼성테크윈 주식회사 Connecting method between bump of semiconductor package and copper circuit pattern and bump structure of semiconductor package therefor
JP5707316B2 (en) * 2009-03-12 2015-04-30 ナミックス株式会社 Electronic component mounting method

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