JPH11135671A - Method for forming conductive bump, semiconductor device and mounting circuit device - Google Patents
Method for forming conductive bump, semiconductor device and mounting circuit deviceInfo
- Publication number
- JPH11135671A JPH11135671A JP9296986A JP29698697A JPH11135671A JP H11135671 A JPH11135671 A JP H11135671A JP 9296986 A JP9296986 A JP 9296986A JP 29698697 A JP29698697 A JP 29698697A JP H11135671 A JPH11135671 A JP H11135671A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- support substrate
- semiconductor device
- electrode
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は導電性バンプの形成
方法、半導体装置および実装回路装置に関する。The present invention relates to a method for forming a conductive bump, a semiconductor device, and a mounted circuit device.
【０００２】[0002]
【従来の技術】実装回路装置は、回路機構もしくは機器
類のコンパクト化や高容量化など図ることができるた
め、各種の電子機器類に広く使用されている。そして、
この種の実装回路装置においては、組み立て，製造工程
の簡略化、さらにはコンパクト化など図り易いことか
ら、半導体装置などの電子部品を搭載・実装した構成と
成っている。2. Description of the Related Art Mounted circuit devices are widely used in various electronic devices because they can reduce the size and capacity of circuit mechanisms or devices. And
This type of mounted circuit device has a configuration in which electronic components such as a semiconductor device are mounted and mounted because simplification of the assembly and manufacturing processes and further reduction in size are easy.
【０００３】図３は、実装回路装置の構成に使用されて
いる半導体装置の要部構成を断面的に示したもので、１
は所要の導体パッドを一主面に有する支持基板（キャリ
ア基板）、２は前記支持基板１の一主面の導体パッドに
入出力端子を対応・位置合せして搭載された半導体素
子、３は前記支持基板１の他主面に導出・配置された端
子、４は前記端子３面に形成された接続用の半田バン
プ、５は前記半導体素子２を封止する樹脂層である。FIG. 3 is a cross-sectional view showing a main configuration of a semiconductor device used for the configuration of a mounted circuit device.
Is a support substrate (carrier substrate) having required conductor pads on one main surface; 2 is a semiconductor element mounted with input / output terminals corresponding to and aligned with the conductor pads on one main surface of the support substrate 1; Terminals 4 drawn out and arranged on the other main surface of the support substrate 1 are solder bumps for connection formed on the surface of the terminals 3, and 5 is a resin layer for sealing the semiconductor element 2.
【０００４】上記構成の半導体装置は、実装回路用配線
基板（実装用配線板本体）に対する搭載・実装におい
て、たとえばリード端子を側面から延設した構成の場合
に比べて、接続端子が垂直方向に設定されているため、
搭載・実装領域を低減できるという利点がある。In the semiconductor device having the above-described structure, the connection terminals are more vertically mounted and mounted on the wiring board for the mounting circuit (main body of the mounting wiring board) than in the case where the lead terminals are extended from the side, for example. Is set,
There is an advantage that the mounting / mounting area can be reduced.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記構
成の半導体装置においては、次のような不都合な問題が
ある。すなわち、最終的には、構成した実装回路装置と
して、十分な実装・接続の信頼性が確保される必要があ
る。そのためには、半田バンプ４の高さや大きさなどに
バラツキがあってはならない。しかし、実際的に、これ
らを一様に形成することは困難で、接続実装部が微細化
するほど、接続不良の発生が起こっている。たとえば、
図３に図示した半導体装置の場合、大きい半田バンプ４
1 に隣接する比較的小さい半田バンプ４2 は、半田バン
プ４1 の表面張力に押されて、対応する導電パッドと接
触しないことがしばしば起こり、接続不良を招来する恐
れが多分にある。However, the semiconductor device having the above configuration has the following disadvantages. That is, finally, it is necessary to ensure sufficient mounting and connection reliability as the configured mounting circuit device. For this purpose, the height and size of the solder bumps 4 must not vary. However, in practice, it is difficult to form these uniformly, and as the connection mounting portion becomes finer, the occurrence of connection failure occurs. For example,
In the case of the semiconductor device shown in FIG.
Relatively small solder bump 4 2 adjacent to 1 is pushed into the solder bump 4 1 of surface tension, occur often not in contact with the corresponding conductive pad, a possibility that lead to connection failure is perhaps.
【０００６】こうした問題を解決するため、図４に断面
的に示すごとく、端子３面に半田層６を介して、予め、
球状に形成された半田ボールやCuボールなどの金属ボー
ル７を配置し、この金属ボール７によって高さや大きさ
をコントロールする方式が提案されている。この方式
は、前記金属ボールが一定の寸法・形状であることが前
提になり、金属ボール７の大きさにバラツキがあると、
接続不良などが発生して、実装回路装置の信頼性が損な
われ易い。つまり、一定の寸法・形状の金属ボール７を
安定的に形成することは、プロセスが煩雑で、量産性が
劣るだけでなく、コスト面からも多くの問題があって、
実用的な手段とはいい難い。In order to solve such a problem, as shown in a cross-sectional view in FIG.
A method has been proposed in which metal balls 7 such as solder balls and Cu balls formed in a spherical shape are arranged, and the height and size are controlled by the metal balls 7. This method is based on the premise that the metal ball has a certain size and shape. If the size of the metal ball 7 varies,
Due to a connection failure or the like, the reliability of the mounted circuit device is likely to be impaired. In other words, stably forming the metal balls 7 having a certain size and shape is not only complicated in the process and inferior in mass productivity, but also has many problems in terms of cost.
It is not a practical means.
【０００７】本発明は上記事情に対処してなされたもの
で、突起電極の高さのバラツキに起因する接続の信頼性
を改善できる導電性バンプの形成方法、半導体装置、お
よび実装回路装置の提供を目的とする。The present invention has been made in view of the above circumstances, and provides a method of forming a conductive bump, a semiconductor device, and a mounting circuit device capable of improving the reliability of connection caused by a variation in the height of a bump electrode. With the goal.
【０００８】[0008]
【課題を解決するための手段】請求項１の発明は、表面
に電極が導出配置され、かつ半導体素子の搭載領域を有
する支持基板の電極面に導電性組成物の突起を形成する
工程と、前記突起の外周面に無電解メッキ処理を施して
金属バリア層を形成する工程と、 前記金属バリア層の
外周面に半田層を形成する工程と有する導電性バンプの
形成方法である。According to the first aspect of the present invention, there is provided a step of forming a projection of a conductive composition on an electrode surface of a support substrate having electrodes mounted on a surface thereof and having a semiconductor element mounting area, A method of forming a metal barrier layer by performing an electroless plating process on an outer peripheral surface of the projection; and a step of forming a solder layer on an outer peripheral surface of the metal barrier layer.
【０００９】請求項２の発明は、表面に電極が導出配置
され、かつ半導体素子の搭載領域を有する支持基板の電
極面に導電性組成物の突起を形成する工程と、前記形成
した突起の高さをほぼ一定に加工・調整する工程と、前
記高さを調整した突起の外周面に無電解メッキ処理を施
して金属バリア層を形成する工程と、前記金属バリア層
の外周面に半田層を形成する工程とを有する導電性バン
プの形成方法。According to a second aspect of the present invention, there is provided a step of forming a projection of a conductive composition on an electrode surface of a supporting substrate having a mounting area for a semiconductor element, wherein the electrode is led out on the surface, and the height of the formed projection is increased. A step of processing and adjusting the height to be substantially constant, a step of forming a metal barrier layer by performing an electroless plating process on the outer peripheral surface of the protrusion whose height has been adjusted, and a step of forming a solder layer on the outer peripheral surface of the metal barrier layer. Forming a conductive bump.
【００１０】請求項３の発明は、支持基板と、前記支持
基板の一主面に搭載された半導体素子と、前記支持基板
の他主面に導出配置された電極と、前記電極面に形成さ
れた接続用バンプとを有する半導体装置において、前記
バンプは導電性組成物の突起を芯体とし、外表面を半田
層が被覆していることを特徴とする半導体装置である。According to a third aspect of the present invention, there is provided a support substrate, a semiconductor element mounted on one main surface of the support substrate, an electrode led out on the other main surface of the support substrate, and an electrode formed on the electrode surface. And a connection bump, wherein the bump has a projection made of a conductive composition as a core, and the outer surface is covered with a solder layer.
【００１１】請求項４の発明は、実装用配線板本体と、
前記配線板本体の所定領域面に実装された半導体装置と
を有する実装回路装置であって、前記半導体装置は、支
持基板の一主面に搭載された半導体素子、前記支持基板
の他主面に導出配置された電極、および前記電極面に形
成された導電性組成物の突起を芯体とし、外表面を半田
層が被覆された接続用バンプを備えた構成と成っている
ことを特徴とする実装回路装置である。According to a fourth aspect of the present invention, there is provided a wiring board body for mounting,
A semiconductor device mounted on a predetermined area surface of the wiring board main body, wherein the semiconductor device includes a semiconductor element mounted on one main surface of a support substrate, and a semiconductor element mounted on another main surface of the support substrate. An electrode arranged and led out, and a projection of the conductive composition formed on the electrode surface as a core body, and a configuration having a connection bump covered with a solder layer on the outer surface, It is a mounted circuit device.
【００１２】これらの発明は、半導体装置の入出力用端
子面の接続用バンプが、所定寸法・形状に形成し易い導
電性組成物を芯体とし、この芯体外周面をメッキ層で被
覆した複層構造に形成した点で特徴付けられる。すなわ
ち、支持基板の入出力用端子（電極）面に、たとえばス
クリーン印刷で導電性組成物（導電ペースト）を印刷
し、ほぼ一定高さ・形状の導電性組成物の突起（導電性
バンプ）を形成してから、乾燥・硬化させて成る芯体
と、この芯体を被覆する半田層とで形成されている。
ここで、導電性バンプの高さをほぼ一定にする手段は、
導電性バンプ群の形成面に、平坦面を有する板を支持基
板面と平行に載置し加圧するなどの加工・調整が挙げら
れる。また、導電性組成物は、たとえばAg粉末などの導
電性粉末およびエポキシ樹脂などのバインダー成分で調
製されたものであり、さらに、半田層は無電解メッキ法
や溶融塗布法などで形成される。In these inventions, the connecting bumps on the input / output terminal surfaces of the semiconductor device have a core made of a conductive composition that can be easily formed into a predetermined size and shape, and the outer peripheral surface of the core is covered with a plating layer. It is characterized by forming a multilayer structure. That is, a conductive composition (conductive paste) is printed on the input / output terminal (electrode) surface of the support substrate by, for example, screen printing, and projections (conductive bumps) of the conductive composition having a substantially constant height and shape are formed. The core is formed by drying and curing after being formed, and a solder layer covering the core.
Here, the means for making the height of the conductive bumps substantially constant is:
Processing / adjustment such as placing a plate having a flat surface on the surface on which the conductive bump group is formed in parallel with the surface of the support substrate and pressing the plate is applied. The conductive composition is prepared by using a conductive powder such as an Ag powder and a binder component such as an epoxy resin, and the solder layer is formed by an electroless plating method or a melt coating method.
【００１３】なお、実際的には、前記半田層の下地とし
て、たとえば無電解Cuメッキ法などで、金属バリア層を
形成しておくのが好ましい。すなわち、芯体を成す導電
性組成物が半田付け性良好の場合は、金属バリア層の形
成を省略でき、この金属バリア層の省略で、生産性など
の向上を図ることができる。In practice, it is preferable to form a metal barrier layer as an underlayer of the solder layer by, for example, an electroless Cu plating method. That is, when the conductive composition forming the core has good solderability, the formation of the metal barrier layer can be omitted, and the productivity can be improved by omitting the metal barrier layer.
【００１４】本発明において、配線板本体は、たとえば
アルミナなどのセラミックスを層間絶縁体として形成さ
れたセラミックス系厚膜多層配線板、ポリイミド樹脂を
層間絶縁体として形成されたポリイミド樹脂系薄膜多層
配線板、もしくはこれらの複合型配線板やガラスクロス
エポキシ樹脂を絶縁基材としたガラスエポキシ系多層配
線板などが挙げられる。In the present invention, the main body of the wiring board is, for example, a ceramic-based thick-film multilayer wiring board formed of ceramics such as alumina as an interlayer insulator, and a polyimide resin-based thin-film multilayer wiring board formed of polyimide resin as an interlayer insulator. Alternatively, a composite type wiring board or a glass epoxy type multilayer wiring board using glass cloth epoxy resin as an insulating base material may be used.
【００１５】請求項１および２の発明では、高さ・形状
などのバラツキが大幅に低減・解消され、高品位な導電
性バンプを安定的、かつ量産的に製造することが可能と
なる。すなわち、導電性バンプは、たとえば導電性組成
物のスクリーン印刷などによって、所定寸法・形状に形
成された芯体をベースとし、芯体を半田メッキ層で被覆
した構成を採っているため、高さ・形状などのバラツキ
が大幅に低減・解消された導電性バンプが容易に、かつ
再現性よく形成できる。According to the first and second aspects of the present invention, variations in height, shape and the like are greatly reduced and eliminated, and high-quality conductive bumps can be stably and mass-produced. That is, since the conductive bumps have a configuration in which the core is formed with a solder plating layer based on a core formed in a predetermined size and shape by screen printing of a conductive composition, for example, the height is high. -Conductive bumps with reduced or eliminated variations in shape and the like can be formed easily and with good reproducibility.
【００１６】請求項３の発明では、配線板本体面に接続
する入出力用端子面の導電性バンプが、その高さや大き
さなどのバラツキが低減ないし解消されているため、隣
接する端子同士間での短絡発生も回避され、かつ信頼性
の高い電気的な接続・実装が容易に確保される。According to the third aspect of the present invention, the variation in height and size of the conductive bumps on the input / output terminal surface connected to the wiring board body surface is reduced or eliminated, so that the distance between adjacent terminals can be reduced. The occurrence of a short circuit in the semiconductor device is also avoided, and highly reliable electrical connection and mounting are easily ensured.
【００１７】請求項４の発明では、半導体装置における
接続用導電性バンプのバラツキが低減ないし解消されて
いるため、信頼性の高い接続・実装が容易に形成され、
より安定した実装回路装置として機能する。According to the fourth aspect of the present invention, since the variation in the conductive bumps for connection in the semiconductor device is reduced or eliminated, highly reliable connection and mounting can be easily formed.
It functions as a more stable mounting circuit device.
【００１８】[0018]
【発明の実施の形態】以下図１ (a)， (b)および図２を
参照して実施例を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below with reference to FIGS. 1 (a) and 1 (b) and FIG.
【００１９】図１ (a)は、この実施例に係る半導体装置
の要部構成を示す断面図、図１ (b)は同じく半導体装置
の要部構成を一部拡大して示す断面図である。FIG. 1A is a cross-sectional view showing a configuration of a main part of a semiconductor device according to this embodiment, and FIG. 1B is a cross-sectional view showing an enlarged configuration of a main part of the semiconductor device. .
【００２０】図１ (a)， (b)において、８は支持基板、
９は前記支持基板８の一主面に搭載された半導体素子、
10は前記支持基板８の他主面に導出配置された入出力用
端子（電極）、11は前記入出力用端子（電極）10面に形
成された接続用の導電性バンプである。ここで、接続用
の導電性バンプ11は、図１ (b)に示すごとく、導電性組
成物の突起 11aを芯体とし、外表面をメッキ形成したバ
リアメタル層 11b、溶融塗布した半田層 11cが順次被覆
した構造と成っている。In FIGS. 1A and 1B, reference numeral 8 denotes a support substrate,
9 is a semiconductor element mounted on one main surface of the support substrate 8,
Reference numeral 10 denotes an input / output terminal (electrode) led out on the other main surface of the support substrate 8, and reference numeral 11 denotes a conductive bump for connection formed on the surface of the input / output terminal (electrode) 10. Here, as shown in FIG. 1 (b), the conductive bumps 11 for connection have a projection 11a of a conductive composition as a core, a barrier metal layer 11b formed by plating the outer surface, and a solder layer 11c formed by melting and coating. Are sequentially covered.
【００２１】次に、上記接続用導電性バンプ11の製造方
法例を説明する。Next, an example of a method of manufacturing the connection conductive bump 11 will be described.
【００２２】先ず、一主面が半導体素子の搭載可能に形
成され、他主面に入出力用の端子10が導出・配置された
支持基板８を用意する一方、厚さ 300μm のステンレス
鋼板に、径 400μm の開口を多数個形設して成るマスク
を用意する。次に、前記支持基板８の端子10導出・配置
面に、前記マスクを位置合せ・配置し、導電性ペースト
（たとえばAgペースト、フジクラ化成社製）をスクリー
ン印刷する。すなわち、前記支持基板８の各端子10面
に、導電性ペーストを３回スクリーン印刷して、高さ 2
50μm の円錐状の突起を形成し、その後、 150℃のオー
ブン中に約30分間放置して、導電性の突起を乾燥・硬化
させる。First, a support substrate 8 having one main surface formed so that a semiconductor element can be mounted thereon and the input / output terminals 10 led out and arranged on the other main surface is prepared. On the other hand, a stainless steel plate having a thickness of 300 μm is prepared. Prepare a mask with a large number of openings with a diameter of 400 μm. Next, the mask is positioned and arranged on the terminal 10 leading-out and arrangement surface of the support substrate 8, and a conductive paste (for example, Ag paste, manufactured by Fujikura Kasei Co., Ltd.) is screen-printed. That is, a conductive paste is screen-printed three times on the surface of each terminal 10 of the support substrate 8 so as to have a height 2.
A 50 μm conical projection is formed, and then left in an oven at 150 ° C. for about 30 minutes to dry and cure the conductive projection.
【００２３】次いで、前記導電性バンプ 11aを形成した
面に、所要のマスキングを行ってから、露出させてある
各導電性バンプ 11aの外周面に、無電解Cuメッキによっ
て、厚さ 3μm 程度の金属バリア層 11bを被覆・形成し
た。さらに、前記金属バリア層 11bの外周面に、ホット
エアーレベラーを用いて厚さ15μm 程度の半田層 11cを
コーティングした。なお、ホットエアーレベラーを用い
る代りに、無電解めっき法やスーパージャフィト法など
他の半田層を形成する手段であってもよい。Next, after masking is performed on the surface on which the conductive bumps 11a are formed, the outer peripheral surfaces of the exposed conductive bumps 11a are plated with a metal having a thickness of about 3 μm by electroless Cu plating. The barrier layer 11b was covered and formed. Further, the outer peripheral surface of the metal barrier layer 11b was coated with a solder layer 11c having a thickness of about 15 μm using a hot air leveler. Instead of using a hot air leveler, another means for forming a solder layer such as an electroless plating method or a super japhite method may be used.
【００２４】上記形成した各導電性バンプ11の高さ、形
状などを光学的に測定評価したところ、それらの寸法・
形状のバラツキは± 3％程度の範囲内にあり、全体的に
ほぼ一様な導電性バンプ11であった。The height, shape, and the like of each of the conductive bumps 11 formed above were optically measured and evaluated.
The variation in shape was in the range of about ± 3%, and the conductive bumps 11 were substantially uniform overall.
【００２５】上記導電性バンプ11を端子10に形成した支
持基板８に、半導体素子９を搭載し、さらに、要すれば
封止用の樹脂12で封止することにより、図１ (a)に図示
したような半導体装置13が構成される。The semiconductor element 9 is mounted on the support substrate 8 having the conductive bumps 11 formed on the terminals 10 and, if necessary, is sealed with a sealing resin 12 to obtain the structure shown in FIG. A semiconductor device 13 as shown is configured.
【００２６】図２は、面実装用配線板14の所定領域面
に、上記構成の半導体装置13を、搭載・実装して成る実
装回路装置の要部構成例を断面的に示したもので、実装
・製造工程は、通常実施されている手段である。FIG. 2 is a cross-sectional view showing a configuration example of a main part of a mounted circuit device in which the semiconductor device 13 having the above configuration is mounted and mounted on a predetermined area surface of a wiring board 14 for surface mounting. The mounting / manufacturing process is a commonly practiced means.
【００２７】前記構成の実装回路装置について、常套的
に行われている電気的な試験評価、たとえば熱（ 125
℃，30分間）・冷（−65℃，30分間）を１サイクルと
し、2000サイクルのテストなど行ったところ、接続抵抗
の変化は±10％以内であり、不良の発生は認められず良
好な結果が得られた。With respect to the mounted circuit device having the above-described configuration, a conventional electrical test evaluation, for example, a heat (125)
The test was performed for 2000 cycles with one cycle of cooling (-65 ° C, 30 minutes) and cooling (-65 ° C, 30 minutes). The change in connection resistance was within ± 10%, and no failure was observed. The result was obtained.
【００２８】なお、上記において、単一の支持基板８の
端子10面に、導電性バンプ11を形成する例を示したが、
支持基板８が多面取りに形成されている場合でも、同様
に形成できる。また、導電性組成物からなる芯体 11aの
形成は、スクリーン印刷法によることが好ましいけれ
ど、制御によってはディスペンス方式でおこなうことも
できる。In the above description, an example in which the conductive bumps 11 are formed on the terminals 10 of the single support substrate 8 has been described.
Even when the support substrate 8 is formed in a multiple pattern, it can be similarly formed. The core 11a made of the conductive composition is preferably formed by a screen printing method, but may be formed by a dispense method depending on control.
【００２９】本発明は上記実施例に限定されるものでな
く、発明の趣旨を逸脱しない範囲でいろいろの変形を採
ることができる。たとえば配線板は、アルミナ系の他、
窒化アルミ系，窒化ケイ素系、ガラスエポキシに代表さ
れる樹脂系などでもよい。The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. For example, wiring boards are alumina-based,
Aluminum nitride, silicon nitride, and resin such as glass epoxy may be used.
【００３０】[0030]
【発明の効果】請求項１および２の発明によれば、高さ
・形状などのバラツキが大幅に低減・解消され、高品位
な導電性バンプを備えた支持基板を量産的に提供でき
る。すなわち、スクリーン印刷などによって、所定寸法
・形状に形成された芯体をベースとし、芯体を半田層で
被覆した構成を採るため、高さ・形状などのバラツキが
大幅に低減・解消された導電性バンプが容易に、かつ再
現性よく提供できる。According to the first and second aspects of the present invention, variations in height, shape and the like are greatly reduced and eliminated, and a support substrate having high-quality conductive bumps can be mass-produced. In other words, the core is formed into a predetermined size and shape by screen printing, etc., and the core is covered with a solder layer. Bumps can be provided easily and with good reproducibility.
【００３１】請求項３の発明によれば、隣接する端子同
士間での短絡発生も回避され、配線板本体面に搭載・実
装した場合、信頼性の高い電気的な接続・実装が容易に
確保されるので、高品質な実装回路装置などの提供が可
能となる。According to the third aspect of the present invention, the occurrence of a short circuit between adjacent terminals is also avoided, and when mounted and mounted on the wiring board body surface, highly reliable electrical connection and mounting can be easily secured. Therefore, it is possible to provide a high-quality mounted circuit device and the like.
【００３２】請求項４の発明によれば、半導体装置にお
ける接続用導電性バンプのバラツキが低減ないし解消さ
れているため、信頼性の高い接続・実装が容易に形成さ
れ、より安定した実装回路装置として機能する。According to the fourth aspect of the present invention, since the variation of the conductive bumps for connection in the semiconductor device is reduced or eliminated, highly reliable connection and mounting can be easily formed, and a more stable mounting circuit device. Function as
【図１】(a)は実施例に係る半導体装置の要部構成を示
す断面図、 (b)は半導体装置の導電性バンプの構成を拡
大して示す断面図。FIG. 1A is a cross-sectional view illustrating a main part configuration of a semiconductor device according to an embodiment, and FIG. 1B is an enlarged cross-sectional view illustrating a configuration of a conductive bump of the semiconductor device.
【図２】実施例に係る実装回路装置の要部構成を示す断
面図。FIG. 2 is a sectional view showing a configuration of a main part of the mounted circuit device according to the embodiment.
【図３】従来の半導体装置の要部構成例を示す断面図。FIG. 3 is a cross-sectional view illustrating a configuration example of a main part of a conventional semiconductor device.
【図４】従来の他の半導体装置の要部構成例を示す断面
図。FIG. 4 is a cross-sectional view illustrating a configuration example of a main part of another conventional semiconductor device.
１，８……支持基板 ２，９……半導体素子 ３，10……半導体装置の入出力用端子（電極） ４……半田バンプ ５，12……封止樹脂層 ６……半田層 ７……金属ボール 11……導電性バンプ 11a……芯体 11b……金属バリア層 11c……半田層 13……半導体装置 14……実装用配線板 1, 8 support substrate 2, 9 semiconductor element 3, 10 input / output terminal (electrode) of semiconductor device 4 solder bump 5, 12 sealing resin layer 6 solder layer 7 … Metal balls 11… conductive bumps 11a… core 11b …… metal barrier layer 11c …… solder layer 13 …… semiconductor device 14 …… wiring board for mounting
Claims (4)
素子の搭載領域を有する支持基板の電極面に導電性組成
物の突起を形成する工程と、 前記突起の外周面に無電解メッキ処理を施して金属バリ
ア層を形成する工程と、 前記金属バリア層の外周面に
半田層を形成する工程とを有する導電性バンプの形成方
法。A step of forming projections of a conductive composition on an electrode surface of a support substrate having a semiconductor element mounting area on which electrodes are led out and arranged; and performing electroless plating on an outer peripheral surface of the projections. A method of forming a metal barrier layer by performing the method and a step of forming a solder layer on an outer peripheral surface of the metal barrier layer.
素子の搭載領域を有する支持基板の電極面に導電性組成
物の突起を形成する工程と、 前記形成した突起の高さをほぼ一定に加工・調整する工
程と、 前記高さを調整した突起の外周面に無電解メッキ処理を
施して金属バリア層を形成する工程と、 前記金属バリア層の外周面に半田層を形成する工程とを
有する導電性バンプの形成方法。A step of forming protrusions of a conductive composition on an electrode surface of a support substrate having a semiconductor element mounting area on which electrodes are led out on the surface, and making the height of the formed protrusions substantially constant. Processing and adjusting, forming a metal barrier layer by performing electroless plating on the outer peripheral surface of the protrusion whose height has been adjusted, and forming a solder layer on the outer peripheral surface of the metal barrier layer. A method for forming a conductive bump having the same.
載された半導体素子と、前記支持基板の他主面に導出配
置された電極と、前記電極面に形成された接続用バンプ
とを有する半導体装置において、 前記バンプは導電性組成物の突起を芯体とし、外表面を
半田層が被覆していることを特徴とする半導体装置。3. A support substrate, a semiconductor element mounted on one main surface of the support substrate, electrodes led out on another main surface of the support substrate, and connection bumps formed on the electrode surface. A semiconductor device according to claim 1, wherein the bump has a projection made of a conductive composition as a core, and the outer surface is covered with a solder layer.
所定領域面に実装された半導体装置とを有する実装回路
装置であって、 前記半導体装置は、支持基板の一主面に搭載された半導
体素子、前記支持基板の他主面に導出配置された電極、
および前記電極面に形成された導電性組成物の突起を芯
体とし、外表面を半田層が被覆された接続用バンプを備
えた構成と成っていることを特徴とする実装回路装置。4. A mounting circuit device comprising: a mounting wiring board main body; and a semiconductor device mounted on a predetermined area surface of the wiring board main body, wherein the semiconductor device is mounted on one main surface of a support substrate. Semiconductor element, an electrode led out on the other main surface of the support substrate,
A mounting circuit device having a configuration in which a projection of the conductive composition formed on the electrode surface is used as a core, and a connection bump whose outer surface is covered with a solder layer is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29698697A JP3895020B2 (en) | 1997-10-29 | 1997-10-29 | Method for forming conductive bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29698697A JP3895020B2 (en) | 1997-10-29 | 1997-10-29 | Method for forming conductive bump |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11135671A true JPH11135671A (en) | 1999-05-21 |
| JP3895020B2 JP3895020B2 (en) | 2007-03-22 |
Family
ID=17840780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29698697A Expired - Fee Related JP3895020B2 (en) | 1997-10-29 | 1997-10-29 | Method for forming conductive bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3895020B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100873041B1 (en) * | 2002-06-12 | 2008-12-09 | 삼성테크윈 주식회사 | Connecting method between bump of semiconductor package and copper circuit pattern and bump structure of semiconductor package therefor |
| WO2010103934A1 (en) * | 2009-03-12 | 2010-09-16 | ナミックス株式会社 | Underfill material and method for mounting electronic component |
-
1997
- 1997-10-29 JP JP29698697A patent/JP3895020B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100873041B1 (en) * | 2002-06-12 | 2008-12-09 | 삼성테크윈 주식회사 | Connecting method between bump of semiconductor package and copper circuit pattern and bump structure of semiconductor package therefor |
| WO2010103934A1 (en) * | 2009-03-12 | 2010-09-16 | ナミックス株式会社 | Underfill material and method for mounting electronic component |
| CN102349141A (en) * | 2009-03-12 | 2012-02-08 | 纳美仕股份有限公司 | Underfill material and method for mounting electronic component |
| US8586467B2 (en) | 2009-03-12 | 2013-11-19 | Namics Corporation | Method of mounting electronic component and mounting substrate |
| JP5707316B2 (en) * | 2009-03-12 | 2015-04-30 | ナミックス株式会社 | Electronic component mounting method |
| TWI509751B (en) * | 2009-03-12 | 2015-11-21 | Namics Corp | Bottoming of the filling material and electronic components of the assembly method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3895020B2 (en) | 2007-03-22 |
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