JPH0558678B2 - - Google Patents
Info
- Publication number
- JPH0558678B2 JPH0558678B2 JP7042589A JP7042589A JPH0558678B2 JP H0558678 B2 JPH0558678 B2 JP H0558678B2 JP 7042589 A JP7042589 A JP 7042589A JP 7042589 A JP7042589 A JP 7042589A JP H0558678 B2 JPH0558678 B2 JP H0558678B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode part
- thick film
- electrode
- wiring board
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000012298 atmosphere Substances 0.000 claims description 10
- 238000007650 screen-printing Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 239000010408 film Substances 0.000 description 24
- 239000004020 conductor Substances 0.000 description 11
- 238000010304 firing Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体デバイス搭載部と、半導体デ
バイスからの回路を導く配線電極部とからなる配
線基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a wiring board comprising a semiconductor device mounting section and a wiring electrode section for guiding circuits from the semiconductor device.
（従来の技術）
従来、第３図ａに示すように、基板１１上に半
導体デバイス搭載部１２と、半導体デバイス搭載
部１２に搭載した半導体デバイスからの回路を導
く配線電極部１３とからなる配線基板１４では、
配線電極部１３のうち半導体デバイス搭載部１２
に近い電極部１３ａは微細配線が必要であるとと
もにワイヤボンデイング等に使用できる必要があ
るため、配線電極部１３全体をAuで形成してい
た。Au配線電極部１３を作成する方法としては、
従来からの公知のスクリーン印刷法、スクリーン
印刷法とエツチング方法の組合わせ、Auレジネ
ート方法等の方法が使用できる。(Prior Art) Conventionally, as shown in FIG. 3a, wiring is made up of a semiconductor device mounting portion 12 on a substrate 11 and a wiring electrode portion 13 that leads a circuit from the semiconductor device mounted on the semiconductor device mounting portion 12. On the board 14,
Semiconductor device mounting portion 12 of wiring electrode portion 13
The electrode portion 13a near the wire requires fine wiring and also needs to be usable for wire bonding, etc., so the entire wiring electrode portion 13 is made of Au. The method for creating the Au wiring electrode section 13 is as follows:
Conventional methods such as a screen printing method, a combination of a screen printing method and an etching method, and an Au resinate method can be used.
（発明が解決しようとする課題）
しかしながら、Auは高価であり、配線電極部
１３全体をAuで形成すると、配線基板が高価に
なるとともに、半田付も不可能で導体抵抗も高く
なる問題があつた。(Problems to be Solved by the Invention) However, Au is expensive, and if the entire wiring electrode part 13 is made of Au, there are problems in that the wiring board becomes expensive, it is impossible to solder, and the conductor resistance becomes high. Ta.
この問題を解決するため、Au配線電極部１３
をCu等の他の安価な配線パターンに置き換える
ことも考えられるが、これらの安価な金属では、
特に電極部１３ａに必要な微細パターンが形成で
きないとともに、ワイヤボンデイング等を実施で
きない問題があつた。 In order to solve this problem, the Au wiring electrode section 13
It is also possible to replace it with other inexpensive wiring patterns such as Cu, but with these cheap metals,
In particular, there were problems in that it was not possible to form a necessary fine pattern on the electrode portion 13a, and it was not possible to carry out wire bonding or the like.
このため、電極部１３ａの部分はAuにより配
線パターンを形成し、他の部分をCu等の他の金
属で形成することも考えられるが、この場合に第
３図ｂに示すように、Au電極部１３ａを形成し
た後例えばスクリーン印刷法によりCu厚膜電極
部１３を形成すると、Cu厚膜電極部１３の焼成
にあたつてAuがCu中にカーケンドル効果により
拡散して断線１５が生じることが多かつた。ま
た、Cu厚膜電極部１３を全体に形成した後、所
定の部分に無電解Niメツキを介して無電解Auメ
ツキにより電極部１３ａを形成することも可能だ
が、メツキのはみ出しによつて微細パターンが達
成できないとともに、Cu厚膜電極部１３がメツ
キ液に侵されて接着強度が約1/2に劣化する問題
もあつた。 Therefore, it is conceivable to form the wiring pattern in the electrode part 13a part using Au, and to form the other parts with other metals such as Cu, but in this case, as shown in FIG. 3b, the Au electrode If the Cu thick film electrode part 13 is formed by, for example, a screen printing method after forming the part 13a, Au may be diffused into the Cu due to the Kirkendall effect during firing of the Cu thick film electrode part 13, causing a disconnection 15. It was a lot. Furthermore, after forming the Cu thick film electrode part 13 on the whole, it is also possible to form the electrode part 13a on a predetermined part by electroless Au plating via electroless Ni plating, but the protrusion of the plating may cause a fine pattern. In addition, there was a problem that the Cu thick film electrode portion 13 was eroded by the plating solution and the adhesive strength was reduced to about 1/2.
本発明の目的は上述した課題を解消して、低コ
ストで、半田付が可能であり、低導体抵抗であ
り、かつワイヤボンデイングやダイボンデイング
が容易に可能な配線基板の製造方法を提供しよう
とするものである。 An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a wiring board that is low cost, can be soldered, has low conductor resistance, and can be easily wire bonded and die bonded. It is something to do.
（課題を解決するための手段）
本発明の配線基板の製造方法は、半導体デバイ
ス搭載部と、半導体デバイスからの回路を導く
Au電極部と、このAu電極部から接続部を介して
回路を導くCu厚膜電極部とを基板上に設けてな
る配線基板の製造方法において、Au電極部を形
成する工程と、スクリーン印刷法によりパターン
を形成後不活性雰囲気中で焼成してCu厚膜電極
部を形成する工程と、導体ペーストを700℃以下
の不活性雰囲気中で焼成して接続部を形成する工
程とからなることを特徴とするものである。(Means for Solving the Problems) The method for manufacturing a wiring board of the present invention includes a semiconductor device mounting portion and a circuit leading from the semiconductor device.
A method for manufacturing a wiring board in which an Au electrode part and a Cu thick film electrode part that leads a circuit from the Au electrode part through a connection part are provided on a substrate, including a step of forming the Au electrode part, and a screen printing method. The process consists of a step of forming a pattern and then firing it in an inert atmosphere to form a Cu thick film electrode part, and a process of firing the conductive paste in an inert atmosphere of 700°C or less to form a connection part. This is a characteristic feature.
（作用）
上述した構成において、予じめAu電極部を形
成した後、Cu厚膜電極部を形成し、さらにこれ
らAu電極部とCu厚膜電極部との間に、不活性導
体ペーストを使用して接続部を形成する。導体ペ
ーストとしては低温焼結性のCu厚膜導体ペース
トや、不活性雰囲気中にて焼成できるNi導体ペ
ーストを使用することが好ましく、以下のような
作用効果を得ることができる。(Function) In the above structure, after forming the Au electrode section in advance, the Cu thick film electrode section is formed, and then an inert conductive paste is used between these Au electrode sections and the Cu thick film electrode section. to form a connection. As the conductor paste, it is preferable to use a Cu thick film conductor paste that can be sintered at low temperatures or a Ni conductor paste that can be fired in an inert atmosphere, and the following effects can be obtained.
(1) Auの使用量を減らしているため、低コスト
で配線基板を得ることができる。(1) Since the amount of Au used is reduced, wiring boards can be obtained at low cost.
(2) Au電極部とCu厚膜電極部との間を接続部に
より接続し、焼成を比較的低温度で実施する
為、AuのCu中へのカーケンドル効果による拡
散に起因する断線を効果的になくすことができ
る。(2) Since the Au electrode part and the Cu thick film electrode part are connected by a connecting part and firing is performed at a relatively low temperature, disconnections caused by diffusion of Au into Cu due to the Kirkendall effect can be effectively prevented. can be lost.
(3) Au電極部を形成しているため、ワイヤボン
デイングやダイボンデイングを容易に実施する
ことができる。(3) Since the Au electrode part is formed, wire bonding and die bonding can be easily performed.
(4) 接続部の焼成を不活性雰囲気中でしかも低温
で実施することができるため、Cu厚膜電極部
が酸化されることもない。(4) Since the connecting portion can be fired in an inert atmosphere and at a low temperature, the Cu thick film electrode portion will not be oxidized.
(5) Cu厚膜電極部が設けられているため、半田
付が可能となる。(5) Soldering is possible because a Cu thick film electrode part is provided.
(6) Cu厚膜にて配線パターンを形成している為、
低導体抵抗である。(6) Since the wiring pattern is formed with a thick Cu film,
Low conductor resistance.
（実施例）
第１図ａ，ｂはそれぞれ本発明の製造方法によ
り得た配線基板の一例の構造を示す図およびその
接続部を拡大して示す図である。第１図ａにおい
て、本発明の配線基板１はアルミナ等よりなる基
板２上にLSI等の半導体デバイスを搭載する半導
体デバイス搭載部３を有するとともに、この半導
体デバイス搭載部３近傍に半導体デバイスからの
回路を導く複数のAu電極部４、およびこれらAu
電極部４から接続部５を介して回路を導くCu厚
膜電極部６を設けて構成されている。(Example) FIGS. 1a and 1b are a diagram showing the structure of an example of a wiring board obtained by the manufacturing method of the present invention, and an enlarged diagram showing the connection part thereof, respectively. In FIG. 1a, a wiring board 1 of the present invention has a semiconductor device mounting portion 3 on which a semiconductor device such as an LSI is mounted on a substrate 2 made of alumina or the like, and a semiconductor device mounting portion 3 in the vicinity of the semiconductor device mounting portion 3 has a semiconductor device mounting portion 3 on which a semiconductor device such as an LSI is mounted. A plurality of Au electrode parts 4 that guide the circuit, and these Au electrode parts 4
It is configured by providing a Cu thick film electrode section 6 that leads the circuit from the electrode section 4 through the connection section 5.
接続部５は、第１図ｂの拡大図に示すように、
Au電極部４の先端とCu厚膜電極部６の先端とを
印刷の精度を配慮し例えば200μｍ程度離れた状
態で設けると、AuとCuとの間のカーケンドル効
果を皆無にできるため、断線を有効に防止でき好
ましい。しかしながら、本発明では、Au電極部
４の先端とCu厚膜電極部６の先端とが重なつて
も、接続部５を設けているため断線の防止が可能
となる。 As shown in the enlarged view of FIG. 1b, the connecting portion 5 is
If the tip of the Au electrode section 4 and the tip of the Cu thick film electrode section 6 are separated by, for example, about 200 μm in consideration of printing accuracy, the Kirkendall effect between Au and Cu can be completely eliminated, thereby preventing wire breakage. This is preferable because it can be effectively prevented. However, in the present invention, even if the tip of the Au electrode section 4 and the tip of the Cu thick film electrode section 6 overlap, disconnection can be prevented because the connection section 5 is provided.
第２図は本発明の配線基板の製造方法の一例を
示すフローチヤートである。まず、従来から公知
のスクリーン印刷法、スクリーン印刷法とエツチ
ング法を組み合わせた方法、薄膜エツチング方法
等によりパターン形成後必要に応じて焼成して、
基板上にAu電極部を形成する。次に、Cu厚膜導
体ペーストをスクリーン印刷法によりパターン印
刷後、例えば窒素雰囲気等の不活性雰囲気下850
〜950℃の温度で焼成してCu厚膜電極部を形成す
る。 FIG. 2 is a flowchart showing an example of the method for manufacturing a wiring board according to the present invention. First, a pattern is formed by a conventionally known screen printing method, a method combining screen printing and etching, a thin film etching method, etc., and then baked as necessary.
Form an Au electrode part on the substrate. Next, after pattern-printing the Cu thick film conductor paste by screen printing method, the paste is printed at 850° C. in an inert atmosphere such as a nitrogen atmosphere.
A Cu thick film electrode part is formed by firing at a temperature of ~950°C.
次に、Au電極部とCu厚膜電極部との間に、低
温焼結性のCu厚膜導体ペーストをスクリーン印
刷法によりパターン印刷後、例えば窒素雰囲気等
の不活性雰囲気下550〜700℃の温度で焼成して接
続部を形成する。 Next, a pattern of low-temperature sinterable Cu thick-film conductor paste is printed between the Au electrode part and the Cu thick-film electrode part by screen printing, and the paste is then heated at 550 to 700°C in an inert atmosphere such as a nitrogen atmosphere. The connection is formed by firing at a temperature.
また、別な方法によれば、Au電極部とCu厚膜
電極部との間に、不活性雰囲気中で焼成可能な
Ni導体ペーストをスクリーン印刷法によりパタ
ーン印刷後、不活性雰囲気下550〜700℃の温度で
焼成して接続部を形成する。 In addition, according to another method, there is a layer between the Au electrode part and the Cu thick film electrode part that can be fired in an inert atmosphere.
After pattern-printing the Ni conductor paste by screen printing, it is fired at a temperature of 550 to 700°C in an inert atmosphere to form a connection part.
最後に、必要に応じて保護層を基板表面に設け
て、本発明の配線基板を得ている。 Finally, a protective layer is provided on the surface of the substrate, if necessary, to obtain the wiring board of the present invention.
実際に、上述した方法により作製した本発明の
配線基板について評価試験を実施した結果を第４
図ａ，ｂに示す。第４図ａ，ｂの結果から判る様
に本発明で得た配線基板は、ワイヤボンデイング
性をそこなわずに導体抵抗値を従来品に比べ、約
半分にする事が出来た。 The results of an evaluation test on the wiring board of the present invention manufactured by the method described above are shown in the fourth section.
Shown in Figures a and b. As can be seen from the results shown in FIGS. 4a and 4b, the wiring board obtained by the present invention was able to reduce the conductor resistance value to about half that of the conventional product without impairing wire bonding properties.
本発明は、上述した実施例にのみ限定されるも
のでなく、幾多の変形、変更が可能である。例え
ば、上述した実施例では焼成温度の一例を具体的
に示したが、焼成温度がこの温度に限定されるも
のでないことは明らかである。 The present invention is not limited to the embodiments described above, and can be modified and changed in many ways. For example, although an example of the firing temperature was specifically shown in the above embodiment, it is clear that the firing temperature is not limited to this temperature.
（発明の効果）
以上の説明から明らかなように、本発明の配線
基板の製造方法によれば、Au電極部を形成した
後Cu厚膜電極部を形成し、さらにこれらAu電極
部とCu厚膜電極部との間に所定の接続部を所定
の焼成により形成しているため、低コストで、半
田付が可能であり、低導体抵抗であり、かつワイ
ヤボンデイングやダイボンデイングが容易な配線
基板を得ることができる。(Effects of the Invention) As is clear from the above description, according to the method for manufacturing a wiring board of the present invention, after forming an Au electrode portion, a Cu thick film electrode portion is formed, and further, these Au electrode portions and a Cu thick film electrode portion are formed. A wiring board that is low cost, can be soldered, has low conductor resistance, and is easy to wire bond and die bond because the specified connection part with the membrane electrode part is formed by a specified firing process. can be obtained.
第１図ａ，ｂはそれぞれ本発明の製造方法によ
り得た配線基板の一例の構造を示す図およびその
接続部を拡大して示す図、第２図は本発明の配線
基板の製造方法の一例を示すフローチヤート、第
３図ａ，ｂはそれぞれ従来の製造方法により得た
配線基板の一例の構造を示す図およびその接続部
を拡大して示す図、第４図ａ，ｂは本発明で得た
配線基板と従来品との比較データーを示す図であ
る。
１……配線基板、２……基板、３……半導体デ
バイス搭載部、４……Au電極部、５……接続部、
６……Cu厚膜電極部。
FIGS. 1a and 1b are diagrams showing the structure of an example of a wiring board obtained by the manufacturing method of the present invention and an enlarged view of the connection parts thereof, and FIG. 2 is an example of the manufacturing method of the wiring board of the present invention. FIGS. 3a and 3b are flowcharts showing the structure of an example of a wiring board obtained by the conventional manufacturing method and an enlarged view of its connection parts, and FIGS. FIG. 3 is a diagram showing comparison data between the obtained wiring board and a conventional product. DESCRIPTION OF SYMBOLS 1... Wiring board, 2... Substrate, 3... Semiconductor device mounting part, 4... Au electrode part, 5... Connection part,
6...Cu thick film electrode part.
Claims (1)
らの回路を導くAu電極部と、このAu電極部から
接続部を介して回路を導くCu厚膜電極部とを基
板上に設けてなる配線基板の製造方法において、
Au電極部を形成する工程と、スクリーン印刷法
によりパターンを形成後不活性雰囲気中で焼成し
てCu厚膜電極部を形成する工程と、導体ペース
トを700℃以下の不活性雰囲気中で焼成して接続
部を形成する工程とからなることを特徴とする配
線基板の製造方法。1. A method for manufacturing a wiring board in which a semiconductor device mounting part, an Au electrode part that leads a circuit from the semiconductor device, and a Cu thick film electrode part that leads a circuit from this Au electrode part via a connection part are provided on a substrate. In,
A process of forming an Au electrode part, a process of forming a pattern by screen printing method and baking it in an inert atmosphere to form a Cu thick film electrode part, and a process of baking the conductive paste in an inert atmosphere at 700℃ or less. 1. A method for manufacturing a wiring board, comprising the step of: forming a connection portion using a wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7042589A JPH02250392A (en) | 1989-03-24 | 1989-03-24 | Manufacture of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7042589A JPH02250392A (en) | 1989-03-24 | 1989-03-24 | Manufacture of wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02250392A JPH02250392A (en) | 1990-10-08 |
| JPH0558678B2 true JPH0558678B2 (en) | 1993-08-27 |
Family
ID=13431113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7042589A Granted JPH02250392A (en) | 1989-03-24 | 1989-03-24 | Manufacture of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02250392A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04316394A (en) * | 1991-04-15 | 1992-11-06 | Ngk Insulators Ltd | Manufacture of ceramic thick film wiring circuit board |
| US6384344B1 (en) | 1995-06-19 | 2002-05-07 | Ibiden Co., Ltd | Circuit board for mounting electronic parts |
| EP0883173B1 (en) | 1996-09-12 | 2007-09-12 | Ibiden Co., Ltd. | Circuit board for mounting electronic parts |
| JP3225854B2 (en) * | 1996-10-02 | 2001-11-05 | 株式会社デンソー | Thick film circuit board and wire bonding electrode forming method thereof |
-
1989
- 1989-03-24 JP JP7042589A patent/JPH02250392A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02250392A (en) | 1990-10-08 |
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| JPH04334083A (en) | Thick film circuit board and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |