JPH0353793B2 - - Google Patents
Info
- Publication number
- JPH0353793B2 JPH0353793B2 JP59009762A JP976284A JPH0353793B2 JP H0353793 B2 JPH0353793 B2 JP H0353793B2 JP 59009762 A JP59009762 A JP 59009762A JP 976284 A JP976284 A JP 976284A JP H0353793 B2 JPH0353793 B2 JP H0353793B2
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- substrate
- solder
- hole
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 26
- 239000004020 conductor Substances 0.000 claims description 24
- 229910000679 solder Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 12
- 239000010410 layer Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000004544 sputter deposition Methods 0.000 claims description 10
- 238000007740 vapor deposition Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000009736 wetting Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 12
- 239000010409 thin film Substances 0.000 claims 3
- 239000000919 ceramic Substances 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、絶縁性基板の表面および裏面に互い
に電気的に接続された導体パターンを形成してな
る厚膜回路基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a thick film circuit board in which conductive patterns electrically connected to each other are formed on the front and back surfaces of an insulating substrate.
近年、様々な分野において電子機器の小型軽量
化、高信頼性化の要求が益々高まつており、プリ
ント配線基板上にDIP型ICパツケージを搭載する
ような従来からの実装方法では、その要求を十分
に満足させることができなくなつてきている。こ
のような要求を満足するための一方法として、例
えばアルミナセラミツク等の絶縁性基板上に導体
ペーストと絶縁体ペーストを印刷し、乾燥、焼成
することにより積層する所謂、厚膜回路基板を形
成し、その上にICチツプ等のチツプ部品を直接
搭載し全体をシーリングする、所謂マルチチツプ
パツケージング技術が開発されつつある。 In recent years, there has been an increasing demand for electronic devices to be smaller, lighter, and more reliable in various fields, and traditional mounting methods such as mounting a DIP type IC package on a printed wiring board cannot meet these demands. It is becoming impossible to fully satisfy them. One way to meet these demands is to form a so-called thick film circuit board by printing conductive paste and insulating paste on an insulating substrate such as alumina ceramic, and then drying and baking them to laminate them. , so-called multi-chip packaging technology is being developed, in which chip components such as IC chips are directly mounted on top of the chip and the whole is sealed.
このような厚膜回路基板においては、入、出力
端子をいかに高密度に配設するかが大きな課題と
なる。すなわち、従来の厚膜回路基板では周辺に
厚膜からなる入、出力端子取付用パツドを形成
し、半田にてクリツプリードを支持固定すること
により入、出力端子を形成する方法をとつてい
た。この従来法では入、出力端子のピツチは実用
上2.54mm程度であり、これが1.27mmにも小さくな
ると、歩留りが著しく低下し、さらにパツドに
Agペースト等を用いた場合には、マイグレーシ
ヨンが起り、端子間の絶縁抵抗の劣化や短絡事故
が生じるという問題があつた。 In such thick film circuit boards, a major issue is how to arrange input and output terminals in a high density. In other words, in conventional thick film circuit boards, thick film input and output terminal mounting pads are formed on the periphery, and clip leads are supported and fixed with solder to form input and output terminals. . In this conventional method, the pitch between the input and output terminals is practically about 2.54 mm, but if this becomes as small as 1.27 mm, the yield will drop significantly and the pads will become more expensive.
When Ag paste or the like is used, migration occurs, causing problems such as deterioration of insulation resistance between terminals and short-circuit accidents.
本発明はこのような事情に鑑みてなされたもの
で、その目的とするところは、基板上に外部装置
との接続のため入、出力端子を高密度に配設する
ことができる厚膜回路基板の製造方法を提供する
ことにある。 The present invention was made in view of the above circumstances, and its purpose is to provide a thick film circuit board on which input and output terminals can be arranged in a high density for connection with external devices. The purpose of this invention is to provide a method for manufacturing the same.
本発明は、基板の通孔の内壁および表面に蒸着
またはスパツタにより形成される金属膜を含む導
体層を形成して、厚膜により基板の表面に形成さ
れる導体パターンと裏面に形成される導体パター
ンとを電気的に接続するとともに、この通孔の内
壁および基板の表面に形成された導体層を利用し
て、通孔内に入、出力端子となる金属ピンを挿入
し、半田により支持固定してこれらを入、出力端
子とするようにしたものである。従つて、基板の
周辺部等に入、出力端子を高密度に、かつ歩留り
よく、さらに十分な機械的強度で形成することが
できる。 The present invention forms a conductor layer including a metal film formed by vapor deposition or sputtering on the inner wall and surface of a through hole of a substrate, and forms a conductor pattern formed on the front surface of the substrate with a thick film and a conductor layer formed on the back surface. In addition to electrically connecting the pattern, the metal pin that will become the output terminal is inserted into the through hole using the conductor layer formed on the inner wall of the through hole and the surface of the board, and is supported and fixed with solder. These are used as input and output terminals. Therefore, output terminals can be formed in the periphery of the substrate with high density, high yield, and sufficient mechanical strength.
以下、図面を参照して本発明の実施例を説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.
第１図に本発明による厚膜回路基板の製造工程
を示す。まず第１図ａに示すように、アルミナセ
ラミツク等の絶縁性基板１１に通孔１２を形成す
る。次に、この基板１１の表面にフアインライン
性の優れた例えばAuペースト等をスクリーン印
刷法等によりパターニングし、これを乾燥、焼成
を行なう事により、第１図ｂに示すように表面導
体パターン１３を形成する。ここでAuペースト
の場合は、フアインライン性には優れているが半
田、特にSn／Pb半田に対する拡散速度が極めて
速いことを考慮しておかないといけない。基板１
１の表面には、さらに必要に応じて絶縁体ペース
トをスクリーン印刷法等によりパターニングし、
乾燥、焼成することにより絶縁体層１４を形成す
る。一方、基板１１の裏面にはフアインライン性
はさほど良くないが、半田に対する拡散速度の比
較的遅い、例えばNi、Ag、Ag／Pdペースト等
をスクリーン印刷法等には印刷し、乾燥、焼成す
ることにより裏面導体パターン１５を形成する。 FIG. 1 shows the manufacturing process of a thick film circuit board according to the present invention. First, as shown in FIG. 1a, a through hole 12 is formed in an insulating substrate 11 made of alumina ceramic or the like. Next, the surface of this substrate 11 is patterned with, for example, Au paste having excellent fine line properties, by screen printing, etc., and then dried and fired to form a surface conductor pattern 13 as shown in FIG. 1b. form. In the case of Au paste, although it has excellent fine line properties, it must be taken into account that the diffusion rate for solder, especially Sn/Pb solder, is extremely fast. Board 1
If necessary, insulating paste is further patterned on the surface of 1 by screen printing method, etc.
The insulator layer 14 is formed by drying and firing. On the other hand, on the back side of the substrate 11, a paste such as Ni, Ag, Ag/Pd paste, etc., which does not have very good fine line properties but has a relatively slow diffusion rate with respect to solder, is printed using a screen printing method, dried, and baked. By doing this, a back conductor pattern 15 is formed.
次に、第１図ｃに示すように基板１１の表面側
より半田に対する拡散係数がAuより小さい金属
材料、または半田に対する拡散速度よりも半田か
らの拡散速度の方が大きい金属材例、例えばNi、
Cu等からなる厚さ１〜5μの金属膜１７は蒸着あ
るいはスパツタにより形成する。この時、蒸着ま
たはスパツタによる金属粒子は、微小粒子である
ため、通孔１２の内壁にも回り込んで付着し、こ
れによつて表面導体パターン１３の裏面導体パタ
ーン１５との電気的接続を完全に行なうことがで
きる。なお、この場合接着強度を良くするためこ
れらの蒸着あるいはスパツタによる金属膜１７と
基板１１との間に必要に応じ、予め酸化し易く、
かつ酸素との結合力の大きい金属材料、例えば
Cr、Ti、Ｖ、Ni等からなる接着層１６を蒸着あ
るいはスパツタ等により形成してもよい。 Next, as shown in FIG. 1c, from the surface side of the substrate 11, a metal material whose diffusion coefficient to solder is smaller than that of Au, or a metal material whose diffusion rate from solder is higher than that from Au, such as Ni. ,
A metal film 17 made of Cu or the like and having a thickness of 1 to 5 μm is formed by vapor deposition or sputtering. At this time, since the metal particles deposited or sputtered are minute particles, they wrap around and adhere to the inner wall of the through hole 12, thereby completely establishing the electrical connection between the front conductor pattern 13 and the back conductor pattern 15. can be done. In this case, in order to improve the adhesive strength, if necessary, between the metal film 17 formed by vapor deposition or sputtering and the substrate 11, a layer that is easily oxidized,
and a metal material with a large bonding force with oxygen, e.g.
The adhesive layer 16 made of Cr, Ti, V, Ni, etc. may be formed by vapor deposition, sputtering, or the like.
ここで、後述するように通孔１２に入、出力端
子となる金属ピンを例えば半田にて支持固定する
場合を考えると、表面導体パターン１３である例
えばAu等の厚膜は多孔質であるため、この上に
蒸着あるいはスパツタで抵拡散物質を被覆させた
のでは、程度の差は多少あるがやはり多孔質の被
膜ができることと、冷却速度の不均一等により格
子欠陥ができる。そして半田はこのような孔や格
子欠陥に沿つて速やかに拡散するので、金属膜１
７のうち表面導体パターン１３であるAu厚膜上
に形成された部分は、半田、特にSn／Pb半田に
対して、半田の拡散防止効果を十分に奏し難い。
そこで、この実施例では第１図ｄに示すように半
田に対してAuよりも拡散係数の小さい金属材料、
例えばCuあるいはNiからなる厚さ５〜15μのメツ
キ膜１８を、電解あるいは無電解メツキにて形成
し、その後基板１１の表面および裏面にレジスト
あるいはドライフイルム等を塗布あるいはラミネ
ートし、該レジストあるいはドライフイルムを露
光、現像することにより、基板１１表面の必要な
回路パターンおよび通孔１２内壁を除いた不必要
な部分のメツキ膜および蒸着あるいはスパツタリ
ングによる金属膜を選択的にエツチング除去する
ことにより、第１図ｅに示す如く基板１１表面の
所定回路パターンおよび通孔１２の内壁に半田に
対しAuよりも拡散係数の小さい例えばCuあるい
はNi等のメツキ膜１８を表面導体とする導体層
１９を形成する。 Here, considering the case where a metal pin that enters the through hole 12 and becomes an output terminal is supported and fixed with solder, for example, as will be described later, since the thick film such as Au, which is the surface conductor pattern 13, is porous. If a resistive diffusion material is coated on this by vapor deposition or sputtering, a porous film will be formed to varying degrees, and lattice defects will occur due to non-uniform cooling rates, etc. Since the solder quickly diffuses along these holes and lattice defects, the metal film 1
Of the parts 7 formed on the thick Au film, which is the surface conductor pattern 13, it is difficult to sufficiently prevent the diffusion of solder, especially Sn/Pb solder.
Therefore, in this embodiment, as shown in FIG. 1d, a metal material with a smaller diffusion coefficient than Au for solder,
For example, a plating film 18 made of Cu or Ni with a thickness of 5 to 15 μm is formed by electrolytic or electroless plating, and then a resist or dry film is coated or laminated on the front and back surfaces of the substrate 11, and the resist or dry film is coated or laminated on the front and back surfaces of the substrate 11. By exposing and developing the film, the plating film and the metal film deposited by vapor deposition or sputtering are selectively etched away from the unnecessary portions of the surface of the substrate 11 except for the necessary circuit pattern and the inner wall of the through hole 12. As shown in FIG. 1e, a conductor layer 19 is formed on a predetermined circuit pattern on the surface of the substrate 11 and on the inner wall of the through hole 12, using a plating film 18 made of, for example, Cu or Ni, which has a smaller diffusion coefficient than Au for solder, as a surface conductor. .
そして次に、第１図ｆに示すように通孔１２内
に通孔１２の径よりも小さな径を有する入、出力
端子用の例えばアルミナセラミツク等の基板１１
と熱膨張係数の等しい金属、例えばコバールある
いはFe／Ni42合金等からなる0.35〜0.75mmφ程度
の径の金属ピン２０を半田２１にて支持固定す
る。この際、金属ピン２０には半田ヌレ性を良く
するために、予めNiメツキ、Auメツキあるいは
Snメツキ等を施しておいても良い。 Next, as shown in FIG.
A metal pin 20 having a diameter of about 0.35 to 0.75 mm and made of a metal having the same coefficient of thermal expansion as, for example, Kovar or Fe/Ni42 alloy, is supported and fixed with solder 21. At this time, the metal pin 20 is pre-plated with Ni plating, Au plating, or
It is also possible to apply Sn plating or the like.
上述した方法によれば、金属ピン２０からなる
入、出力端子を十分な強度で高密度にかつ歩留り
よく配設することが可能である。すなわち、従来
の厚膜回路基板では前述したように、周辺に厚膜
からなる入、出力端子取付用パツドを形成し、半
田にてクリツプリードを支持固定することにより
入、出力端子を形成する方法をとつていたため、
入、出力端子のピツチをあまり小さくできず、小
さくすると歩留りが著しく低下し、さらにパツド
にAgペースト等を用いた場合には、マイグレー
シヨンが起り、端子間の絶縁抵抗の劣化や短絡事
故などが生じる問題があつたが、本発明によれば
第２図に示すように基板３１の周辺に2.54mmピツ
チの入、出力端子３２を例えば２列に形成した
り、あるいは３列にも４列にも形成することが可
能で、高集積化に伴なう入、出力端子数の増加に
対しても十分対応することが可能となる。しか
も、この方法によれば入、出力端子３２の基板３
１への接着強度は、前記通孔１２の内壁に半田ヌ
レ性の良い導体層が存在することにより、十分な
強度を維持しているし、入、出力端子３２間のマ
イグレーシヨン間の問題、すなわち絶縁抵抗の劣
化や短絡事故等の問題もすべれ解決される。 According to the method described above, it is possible to arrange the input and output terminals made of metal pins 20 with sufficient strength, high density, and high yield. That is, as mentioned above, in conventional thick film circuit boards, input and output terminals are formed by forming input and output terminal mounting pads made of thick film around the board and supporting and fixing clip leads with solder. Because I was taking
The pitch of the input and output terminals cannot be made very small, and if they are made too small, the yield will drop significantly.Furthermore, if Ag paste is used for the pads, migration will occur, resulting in deterioration of the insulation resistance between the terminals and short circuit accidents. However, according to the present invention, as shown in FIG. 2, the input and output terminals 32 are formed at a pitch of 2.54 mm in two rows around the substrate 31, or in three or four rows. This makes it possible to sufficiently cope with the increase in the number of input and output terminals accompanying higher integration. Moreover, according to this method, the board 3 of the input and output terminals 32
1 maintains sufficient adhesive strength due to the presence of a conductive layer with good solder wetting properties on the inner wall of the through hole 12, and also solves the problem of migration between the input and output terminals 32. In other words, problems such as deterioration of insulation resistance and short circuit accidents are also solved.
このように、本発明によれば厚膜回路基板上に
外部装置との接続のための入、出力端子を高密度
に配設することができる。 As described above, according to the present invention, input and output terminals for connection with external devices can be arranged at high density on the thick film circuit board.
第１図ａ〜ｆは本発明の一実施例に係る厚膜回
路基板の製造工程を示す断面図、第２図は基板上
の入、出力端子の配設状態を示す平面図および側
面図である。
１１……絶縁性基板、１２……通孔、１３，１
５……導体パターン、１６……接着層、１７……
蒸着またはスパツタにより形成される金属膜、１
８……メツキ膜、１９……導体層、２０……金属
ピン、２１……半田、３１……基板、３２……
入、出力端子。
1A to 1F are cross-sectional views showing the manufacturing process of a thick film circuit board according to an embodiment of the present invention, and FIG. 2 is a plan view and a side view showing the arrangement of input and output terminals on the board. be. 11...Insulating substrate, 12...Through hole, 13,1
5... Conductor pattern, 16... Adhesive layer, 17...
Metal film formed by vapor deposition or sputtering, 1
8...Plating film, 19...Conductor layer, 20...Metal pin, 21...Solder, 31...Substrate, 32...
Input and output terminals.
Claims (1)
表面および裏面にそれぞれ導体ペーストを印刷
し、乾燥、焼成して厚膜導体パターンを形成した
後、前記通孔の内壁および前記基板の表面に蒸着
あるいはスパツタにより形成される金属薄膜を含
む導体層を形成して、前記基板の表面に形成され
た厚膜導体パターンと裏面に形成された厚膜導体
パターンとを電気的に接続するとともに、前記通
孔内に外部装置との接続のための入、出力端子と
なる金属ピンを挿入し、この金属ピンを半田によ
り支持固定することを特徴とする厚膜回路基板の
製造方法。 ２ 通孔の内壁および基板の表面に形成される導
体層は、蒸着あるいはスパツタにより形成される
金属薄膜が基板の表面および裏面に形成される厚
膜導体パターンよりも半田に対する拡散係数の小
さい金属材料、または半田に対する拡散速度より
も半田からの拡散速度の方が大きい金属材料から
なることを特徴とする特許請求の範囲第１項記載
の厚膜回路基板の製造方法。 ３ 通孔の内壁および基板の表面に形成される導
体層は、酸素との結合力が大きい易酸化性金属材
料からなる接着層を含むものであることを特徴と
する特許請求の範囲第１項または第２項記載の厚
膜回路基板の製造方法。 ４ 通孔の内壁および基板表面に形成される導体
層は、蒸着あるいはスパツタにより形成される金
属薄膜上に、基板の表面および裏面にそれぞれ形
成される厚膜導体パターンよりも半田に対する拡
散係数の小さい金属材料、または半田に対する拡
散速度よりも半田からの拡散速度の方が大きい金
属材料からなるメツキ膜を形成したものであるこ
とを特徴とする特許請求の範囲第１項〜第３項の
いずれかに記載の厚膜回路基板の製造方法。 ５ 入、出力端子となる金属ピンは半田のヌレ性
のよいメツキを施したものであることを特徴とす
る特許請求の範囲第１項記載の厚膜回路基板の製
造方法。[Claims] 1. A through hole is formed in a ceramic substrate, a conductor paste is printed on the front and back surfaces of the substrate, dried and fired to form a thick film conductor pattern, and then the inner wall of the through hole and A conductor layer including a metal thin film formed by vapor deposition or sputtering is formed on the surface of the substrate, and the thick film conductor pattern formed on the front surface of the substrate and the thick film conductor pattern formed on the back surface are electrically connected. A method for manufacturing a thick film circuit board, characterized in that, at the same time as connecting, a metal pin serving as an input/output terminal for connection with an external device is inserted into the through hole, and the metal pin is supported and fixed by soldering. . 2. The conductor layer formed on the inner wall of the through hole and the surface of the substrate is made of a metal material whose diffusion coefficient for solder is smaller than that of the thick film conductor pattern formed on the front and back surfaces of the substrate, such as a metal thin film formed by vapor deposition or sputtering. 2. The method of manufacturing a thick film circuit board according to claim 1, wherein the thick film circuit board is made of a metal material having a higher diffusion rate from the solder than from the solder. 3. The conductor layer formed on the inner wall of the through hole and the surface of the substrate includes an adhesive layer made of an oxidizable metal material with a high bonding force with oxygen. 2. The method for manufacturing a thick film circuit board according to item 2. 4. The conductor layer formed on the inner wall of the through hole and the surface of the substrate has a smaller diffusion coefficient for solder than the thick film conductor pattern formed on the front and back surfaces of the substrate, respectively, on a metal thin film formed by vapor deposition or sputtering. Any one of claims 1 to 3 is characterized in that the plating film is formed of a metal material or a metal material whose diffusion rate from the solder is higher than that from the solder. The method for manufacturing a thick film circuit board as described in . 5. The method of manufacturing a thick film circuit board according to claim 1, wherein the metal pins serving as input and output terminals are plated with good solder wetting properties.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP976284A JPS59150495A (en) | 1984-01-23 | 1984-01-23 | Method of producing thick film circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP976284A JPS59150495A (en) | 1984-01-23 | 1984-01-23 | Method of producing thick film circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59150495A JPS59150495A (en) | 1984-08-28 |
| JPH0353793B2 true JPH0353793B2 (en) | 1991-08-16 |
Family
ID=11729283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP976284A Granted JPS59150495A (en) | 1984-01-23 | 1984-01-23 | Method of producing thick film circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59150495A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6287476U (en) * | 1985-11-19 | 1987-06-04 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4841257A (en) * | 1971-09-23 | 1973-06-16 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5234949U (en) * | 1975-09-03 | 1977-03-11 |
-
1984
- 1984-01-23 JP JP976284A patent/JPS59150495A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4841257A (en) * | 1971-09-23 | 1973-06-16 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59150495A (en) | 1984-08-28 |
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