JPS60170294A - Method of producing multilayer circuit board with pin - Google Patents

Method of producing multilayer circuit board with pin

Info

Publication number
JPS60170294A
JPS60170294A JP2442584A JP2442584A JPS60170294A JP S60170294 A JPS60170294 A JP S60170294A JP 2442584 A JP2442584 A JP 2442584A JP 2442584 A JP2442584 A JP 2442584A JP S60170294 A JPS60170294 A JP S60170294A
Authority
JP
Japan
Prior art keywords
wiring
ceramic substrate
multilayer wiring
temperature
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2442584A
Other languages
Japanese (ja)
Other versions
JPH0254677B2 (en
Inventor
渡里 俊彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP2442584A priority Critical patent/JPS60170294A/en
Priority to US06/676,425 priority patent/US4612601A/en
Priority to FR8418321A priority patent/FR2555812B1/en
Publication of JPS60170294A publication Critical patent/JPS60170294A/en
Publication of JPH0254677B2 publication Critical patent/JPH0254677B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は高性能コ/ビュークに使用される多層配線基板
に関するもので、特に高密度化のためにLSIチップを
複数個搭載可能なように2表面に微細かつ多層配線を形
成しかつ裏面にマトリクス状に配列された多数の入出力
端子ビンを形成した多層配線セラミック基板の製造方法
に関するものである。
[Detailed Description of the Invention] [Technical Field] The present invention relates to a multilayer wiring board used in high-performance computers/bucks. The present invention relates to a method of manufacturing a multilayer wiring ceramic substrate on which fine multilayer wiring is formed and a large number of input/output terminal bins arranged in a matrix on the back surface.

〔従来技術〕[Prior art]

従来この種の多層配線基板は、たとえばPro−cee
dings 198030th glectronic
 Components Confe−renceのp
283〜p285に6多層セラミック、マルチチップモ
ジュール” (A Multi−Layer Cera
mic。
Conventionally, this type of multilayer wiring board is, for example, Pro-cee.
dings 198030th glectronic
Components Conference page
283~p285 6 Multi-Layer Ceramic, Multi-chip Module”
mic.

Multi −Chip Module )と題して掲
載された論文に示されておシ、基板として第6図に示す
ような内部に多層の信号配線層を有するアルミナセラミ
ック基板を使用し、さらに基板の裏面に配列された入出
力ビンは、第5図のフローチャートに示されているよう
に、内部に多層配線層を含むアルミナセラミック基板を
一括焼結した後にろう付は接着されている。しかも基板
の焼成は。
As shown in the paper titled "Multi-Chip Module", an alumina ceramic substrate with multi-layered signal wiring layers as shown in Fig. 6 is used as the substrate, and furthermore, an array of signal wiring layers is arranged on the back side of the substrate. As shown in the flowchart of FIG. 5, the input/output bin is soldered and bonded after collectively sintering an alumina ceramic substrate containing multilayer wiring layers therein. Moreover, the firing of the board.

285ペ一ジ右段1〜5行目に示されているように、’
 1550℃の高温還元雰囲気中で行なわれる。
As shown in lines 1 to 5 on the right side of page 285, '
The process is carried out in a high temperature reducing atmosphere of 1550°C.

さらに基板焼成後のピンのろう付けは1例えば銀ろうな
どのろう剤を用いて同様に水素中で前記の1550°C
より低い温度約800℃〜850℃で行なわれている。
Furthermore, the pins are brazed after the board is baked at the same temperature as described above at 1550°C in hydrogen using a brazing agent such as silver solder.
It has been carried out at lower temperatures of about 800°C to 850°C.

しかしながら上記のようなピン付は法は、内部に上述の
ようなモリブデンの多層配線層を含むセラミック多層配
線基板においては有効な方法であるが、セラミック基板
を焼結後、その表面に別の条件で微細な配線を形成する
タイプの多層配線基板においては1次のような点で問題
がある。すなわち、このようなタイプのセラミック基板
は内部にスルーホール導体のみを含み。
However, although the pin method described above is an effective method for ceramic multilayer wiring boards containing internal molybdenum multilayer wiring layers as described above, after sintering the ceramic board, other conditions may be applied to the surface of the ceramic board. In multilayer wiring boards of the type in which fine wiring is formed, there are problems in the first order. That is, this type of ceramic substrate contains only through-hole conductors inside.

還元雰囲気で焼結後その表面に微細配線層を形成するが
、この配線層の形成はセラミック基板内部に含まれるス
ルーホール導体に損傷を与えないような温度及び雰囲気
条件で行なう必要があり、逆にこのような条件で形成さ
れた配線層はそれ以上の温度及び厳しい雰囲気には耐え
られないから、上述の例のよりな還元雰囲気で800℃
〜850℃の温度を必要とするようなろう剤〔発明の目
的〕 したがって本発明の目的は、セラミック基板上への微細
配線の形成を容易ならしむると共に 一基板裏面全面に
多数の入出力ピンを容易に形成することを可能とした多
層配線基板の製造方法を提供するにある。
After sintering in a reducing atmosphere, a fine wiring layer is formed on the surface of the ceramic substrate, but this wiring layer must be formed under temperature and atmospheric conditions that do not damage the through-hole conductors contained within the ceramic substrate. Since the wiring layer formed under these conditions cannot withstand higher temperatures and harsher atmospheres, it is
[Object of the Invention] Therefore, an object of the present invention is to facilitate the formation of fine wiring on a ceramic substrate, and to provide a large number of input/output pins on the entire back surface of one substrate. An object of the present invention is to provide a method for manufacturing a multilayer wiring board that allows easy formation of a multilayer wiring board.

〔発明の構成〕[Structure of the invention]

本発明は上記の目的を達成するために、多層配線基板の
多層配線基板としてアルミナセラミ ・ツク基板の焼結
に必要な温度よシ十分に低い温度で焼成可能な絶縁材料
および薄膜配線材料を使用し、さらにビン接着材料とし
て前記多層配線の形成に必要な温度以下で接着可能な月
利を用いたものである。
In order to achieve the above object, the present invention uses an insulating material and a thin film wiring material that can be fired at a temperature sufficiently lower than that required for sintering an alumina ceramic board as a multilayer wiring board. Furthermore, as the adhesive material for the bottle, the adhesive material is used, which can be adhesively bonded at a temperature lower than that required for forming the multilayer wiring.

すなわち本発明によれば、内部において表裏度より低い
温度で焼成可能な絶縁膜と薄膜導体配線よシなる多層配
線層を形成、する第1の工程と、前記セラミック基板の
裏面に前記多層配線層を形成するに必要な温度以下で空
気中で接着可能な金属接着剤を用いて端子ピンを接着す
る第2の工程とからなるビン付き多層配線基板の製造方
法が得られる。
That is, according to the present invention, a first step of forming a multilayer wiring layer consisting of an insulating film and a thin film conductor wiring that can be fired at a temperature lower than that of the front and back surfaces, and forming the multilayer wiring layer on the back surface of the ceramic substrate. There is obtained a method for manufacturing a multilayer wiring board with a bottle, which comprises a second step of bonding terminal pins using a metal adhesive that can be bonded in air at a temperature below the temperature required to form a multilayer wiring board.

〔実施例〕〔Example〕

次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

してこれら6つの図に共通して、1はセラミック基板、
2はスルーホール配線、3はピンパッド、4は第1絶縁
層、5は第2絶縁層、6は第1ヴイアホール配線、7は
第2グイアホール配線、8は第1配線層、9は第2配線
層、】0は入出力ビンをあられしている。 ′ 第1図において、スルーホール配線2はセラミック基板
1の表裏を貫通するように設けられる。スルーホール配
線2の拐刺は前述の従来技術の例と同様にモリブデン又
はタングステンなどが用いられる。ビンパッド3はセラ
ミック基板1を製造するときに一体的にあらかじめ設け
られているものであシ9例えばモリブデン導体膜の上に
酸化保護のためニッケルメッキおよび金メッキを施した
ような構造である。
Common to these six figures, 1 is a ceramic substrate,
2 is a through hole wiring, 3 is a pin pad, 4 is a first insulating layer, 5 is a second insulating layer, 6 is a first via hole wiring, 7 is a second via hole wiring, 8 is a first wiring layer, 9 is a second wiring Layer, ]0 is emptying the input and output bins. ' In FIG. 1, the through-hole wiring 2 is provided so as to penetrate the front and back sides of the ceramic substrate 1. For the through-hole wiring 2, molybdenum, tungsten, or the like is used as in the prior art example described above. The bin pad 3 is integrally provided in advance when the ceramic substrate 1 is manufactured, and has a structure such that, for example, a molybdenum conductor film is plated with nickel and gold to protect it from oxidation.

第2図は、第1の工程においてセラミック基板1の表面
上に微細配線層を形成した状態を示す図である。第1絶
縁層4は基板上においてこの基板と第1配線層8とを絶
縁するために設けられるもので、第1配線層8とスルー
ホール配線2とを接続するための第1ヴイアホール配線
6を含んでいる。第2絶縁層5は第1絶縁層4の上に形
成され、第1配線層8と第2配線層9とを絶縁するため
に設けられるもので、第1配路層8と第2配線層9とを
接続するだめの第2絶縁層材料としてポリイミドが使用
される。ポリイミドの焼成温度は600℃〜400℃の
範囲にあり、しかも窒素中での焼成が好ましいので。
FIG. 2 is a diagram showing a state in which a fine wiring layer is formed on the surface of the ceramic substrate 1 in the first step. The first insulating layer 4 is provided on the substrate to insulate the substrate from the first wiring layer 8, and includes a first via-hole wiring 6 for connecting the first wiring layer 8 and the through-hole wiring 2. Contains. The second insulating layer 5 is formed on the first insulating layer 4 and is provided to insulate the first wiring layer 8 and the second wiring layer 9. Polyimide is used as the material for the second insulating layer that connects to the second insulating layer 9. The firing temperature of polyimide is in the range of 600°C to 400°C, and firing in nitrogen is preferred.

ポリイミドの焼成によって基板1内のスルーホール配線
2が酸化等によって劣化することなく好都合である。
By firing the polyimide, the through-hole wiring 2 in the substrate 1 is advantageously prevented from deteriorating due to oxidation or the like.

ポリイミド絶縁層4及び5の形成は、まず基板】上にポ
リイミドをスピン塗布し、乾燥した後にフォトレジスト
を塗り所望のグイアホール6のパターンをマスクを用い
て露光・現像した後、ポリイミドエツチング液(通常K
OHのような強アルカリ液が使用される)を用いてフォ
トレジスト内のスルーホールパターンに合わせて明けら
れた穴を通してフォトレジスト膜下のポリイミドをエン
チングする。これにより所望のグイアホール6がポリイ
ミド内に明けられる。
The polyimide insulating layers 4 and 5 are formed by first spin-coating polyimide on the substrate, drying it, coating it with photoresist, exposing and developing the desired pattern of guia holes 6 using a mask, and then applying a polyimide etching solution (usually K
The polyimide under the photoresist film is etched using a strong alkaline solution such as OH (a strong alkaline solution such as OH is used) through holes made in accordance with the through hole pattern in the photoresist. This opens the desired guia holes 6 in the polyimide.

配線層8及び9の形成はスルーホール6の明けられたポ
リイミド絶縁膜4上にCr及びPdをスパッタする。C
rはポリイミドとの密着層として形成され、 Pdは配
線導体となるCuとの密着層として形成式れる。Cr及
びPdを絶縁層4上に全面スパッタした後、その上にフ
ォトレジストを塗り、所望の配線8のパターンをマスク
を用いて露光現像すると、フォトレジストは配線8のパ
ターンに従って除去される。
The wiring layers 8 and 9 are formed by sputtering Cr and Pd onto the polyimide insulating film 4 in which the through holes 6 have been formed. C
r is formed as an adhesion layer with polyimide, and Pd is formed as an adhesion layer with Cu, which becomes a wiring conductor. After sputtering Cr and Pd on the entire surface of the insulating layer 4, a photoresist is applied thereon, and a desired pattern of the wiring 8 is exposed and developed using a mask, and the photoresist is removed according to the pattern of the wiring 8.

次にCr及びPdのスパッタ膜を電解メッキ導体として
銅メッキを行なうと、配線8のパターンに従って銅薄膜
が形成され、これが第1配線導体8となる。次にフォト
レジストを除去しPd及びCrエツチング液により銅パ
ターン部分以外の余分なCr、Pd膜を取り除いて第1
配線層8の形成が完了する。第2絶縁層5及び第2配線
層9の形成も同様である。
Next, when copper plating is performed using the sputtered Cr and Pd films as electroplated conductors, a copper thin film is formed according to the pattern of the wiring 8, and this becomes the first wiring conductor 8. Next, the photoresist is removed, and the excess Cr and Pd films other than the copper pattern area are removed using a Pd and Cr etching solution.
Formation of wiring layer 8 is completed. The same applies to the formation of the second insulating layer 5 and the second wiring layer 9.

第3図は、第2図に示すように第1の工程で微細配線を
形成した後、セラミック基板−1の裏面に入出力ピン1
0を接着した状態を示す。入出カビ/10のセラミック
基板1の裏面への接着は第2の工程として行なわれる。
Figure 3 shows the input/output pins 1 on the back side of the ceramic substrate-1 after forming fine wiring in the first step as shown in Figure 2.
0 is shown attached. Adhesion of the mold/10 to the back surface of the ceramic substrate 1 is performed as a second step.

第1の工程で表面に微細配線を形成した後、セラミンク
基板1の裏面においてピンパッド3上に金錫ろう拐を塗
付し、しかる後入出力ピン10を押しあてて200℃〜
600℃の温度を印加して金錫ろう材を溶解し、入出力
ピン】Oをピンバッド3に接着する。
After forming fine wiring on the surface in the first step, gold-tin brazing is applied onto the pin pads 3 on the back surface of the ceramic substrate 1, and then the input/output pins 10 are pressed against each other at 200°C.
A temperature of 600° C. is applied to melt the gold-tin brazing material, and the input/output pin O is bonded to the pin pad 3.

ここでろう材の1例として金錫ろう材を使用するのは、
金錫ろう拐の溶解温度が200℃〜300℃と比較的低
く、かつ錫鉛などのいわゆる半田拐料に比べて十分に接
着強度が強いことによる。さらにろう拐の溶解のために
印加する温度を600℃以下にできるため、基板10表
面に形成された配線層8及び9と絶縁層4及び5に対し
て酸化によるダメージを与えることもない。
Here, gold-tin brazing filler metal is used as an example of brazing filler metal.
This is because the melting temperature of gold-tin brazing is relatively low at 200° C. to 300° C., and the adhesive strength is sufficiently stronger than that of so-called soldering materials such as tin-lead. Furthermore, since the temperature applied to melt the wax can be lower than 600° C., the wiring layers 8 and 9 and the insulating layers 4 and 5 formed on the surface of the substrate 10 will not be damaged by oxidation.

以上のようにして表面に微細配線を形成し。Fine wiring is formed on the surface as described above.

かつ、裏面に多数の入出力ピンを有する高密度多層配線
基板を得ることができる。しかも、入出力ピン10は最
後の工程で接着されるので、第1の工程である基板10
表面への微細配線の形成過程では基板1の裏面において
はピン1oは接着されておらず、従って裏面のピンが障
害となることなく表面における微細配線の形成が容易に
行なえる。
Moreover, a high-density multilayer wiring board having a large number of input/output pins on the back surface can be obtained. Moreover, since the input/output pins 10 are bonded in the last process, the board 10 is bonded in the first process.
In the process of forming fine wiring on the front surface, the pins 1o are not bonded to the back surface of the substrate 1, so that fine wiring can be easily formed on the front surface without the pins on the back surface becoming an obstacle.

〔発明の効果〕〔Effect of the invention〕

以」二説明したように本発明による製造方法を採用する
ことによシ2表面上に微細配線を形成し裏面に多数の入
出力ピンを有する高密度多層配線基板を容易に実現する
ことができる。
As explained below, by employing the manufacturing method according to the present invention, it is possible to easily realize a high-density multilayer wiring board having fine wiring formed on the front surface and a large number of input/output pins on the back surface. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第6図は本発明に係る多層配線基板の製造方
法を工程順に示す図である。
FIGS. 1 to 6 are diagrams showing the method of manufacturing a multilayer wiring board according to the present invention in order of steps.

Claims (1)

【特許請求の範囲】[Claims] 1、内部において表裏を貫通するスルーホール導体配線
を含むセラミック基板の表面に前記セラミック基板の焼
結温度より低い温度で焼成可能な絶縁膜と薄膜導体配線
よりなる多層配線層を形成する第1の工程と、前記セラ
ミック基板の裏面に前記多層配線層を形成するに必要な
温度以下で空気中で接着可能な金属接着剤を用いて端子
ビンを接着する第2の工程とからなるピン付き多層配線
基板の製造方法。
1. A first method for forming a multilayer wiring layer consisting of an insulating film and thin film conductor wiring, which can be fired at a temperature lower than the sintering temperature of the ceramic substrate, on the surface of a ceramic substrate including through-hole conductor wiring that penetrates the front and back sides inside. and a second step of bonding a terminal bottle using a metal adhesive that can be bonded in air at a temperature below the temperature required to form the multilayer wiring layer on the back surface of the ceramic substrate. Substrate manufacturing method.
JP2442584A 1983-11-30 1984-02-14 Method of producing multilayer circuit board with pin Granted JPS60170294A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2442584A JPS60170294A (en) 1984-02-14 1984-02-14 Method of producing multilayer circuit board with pin
US06/676,425 US4612601A (en) 1983-11-30 1984-11-29 Heat dissipative integrated circuit chip package
FR8418321A FR2555812B1 (en) 1983-11-30 1984-11-30 BLOCK OF INTEGRATED CIRCUIT CHIPS

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2442584A JPS60170294A (en) 1984-02-14 1984-02-14 Method of producing multilayer circuit board with pin

Publications (2)

Publication Number Publication Date
JPS60170294A true JPS60170294A (en) 1985-09-03
JPH0254677B2 JPH0254677B2 (en) 1990-11-22

Family

ID=12137794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2442584A Granted JPS60170294A (en) 1983-11-30 1984-02-14 Method of producing multilayer circuit board with pin

Country Status (1)

Country Link
JP (1) JPS60170294A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442145A (en) * 1992-10-12 1995-08-15 Ngk Spark Plug Co., Ltd. Input/output terminal for electronic circuit device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57188896A (en) * 1981-05-15 1982-11-19 Nippon Electric Co Multilayer circuit board
JPS5873193A (en) * 1981-10-28 1983-05-02 株式会社日立製作所 Method of producing multilayer circuit board
JPS60117796A (en) * 1983-11-30 1985-06-25 日本電気株式会社 Multilayer circuit board and method of producing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57188896A (en) * 1981-05-15 1982-11-19 Nippon Electric Co Multilayer circuit board
JPS5873193A (en) * 1981-10-28 1983-05-02 株式会社日立製作所 Method of producing multilayer circuit board
JPS60117796A (en) * 1983-11-30 1985-06-25 日本電気株式会社 Multilayer circuit board and method of producing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442145A (en) * 1992-10-12 1995-08-15 Ngk Spark Plug Co., Ltd. Input/output terminal for electronic circuit device

Also Published As

Publication number Publication date
JPH0254677B2 (en) 1990-11-22

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