JPH05206598A - Ceramic circuit board - Google Patents
Ceramic circuit boardInfo
- Publication number
- JPH05206598A JPH05206598A JP4012755A JP1275592A JPH05206598A JP H05206598 A JPH05206598 A JP H05206598A JP 4012755 A JP4012755 A JP 4012755A JP 1275592 A JP1275592 A JP 1275592A JP H05206598 A JPH05206598 A JP H05206598A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- layer
- circuit board
- metal foil
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、電子機器などの回路構
成に用いる、高精度配線が可能なセラミック回路基板に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic circuit board which can be used for circuit construction of electronic equipment and the like and which enables highly accurate wiring.
【0002】[0002]
【従来の技術】近年、セラミック回路基板は、熱伝導性
や耐熱性、化学的耐久性が有機材料基板より優れている
ので、有機材料基板に代わるものとして利用が拡大して
いる。また電子機器の小型化、多様化に伴い、高密度配
線、高密度実装が可能な基板として広く使用されるよう
になってきた。さらに、今後は半導体ベアチップ実装基
板として需要は高まると予想され、さらに微細な配線が
必要になると考えられる。2. Description of the Related Art In recent years, a ceramic circuit board is superior in heat conductivity, heat resistance, and chemical durability to an organic material substrate, and thus its use is expanding as an alternative to the organic material substrate. In addition, with the miniaturization and diversification of electronic devices, they have come to be widely used as substrates capable of high-density wiring and high-density mounting. Furthermore, it is expected that demand for semiconductor bare chip mounting substrates will increase in the future, and it is considered that finer wiring is required.
【0003】以下に図面を参照しながら、従来のセラミ
ック回路基板の一例について説明する。An example of a conventional ceramic circuit board will be described below with reference to the drawings.
【0004】図3に、従来のセラミック回路基板の構成
を示す。図4は従来の製造方法により電子部品を実装し
たセラミック回路基板の構成を示す。FIG. 3 shows the structure of a conventional ceramic circuit board. FIG. 4 shows a structure of a ceramic circuit board on which electronic parts are mounted by a conventional manufacturing method.
【0005】図3に示すように、従来のセラミック基板
はアルミナなどからなるセラミック基板21上に、Ag
粉やCu粉を主成分とし、これにホウケイ酸ガラスまた
はホウケイ酸ガラスと熱可塑性樹脂などを添加してなる
導電ペーストを印刷して導体層22を形成する。導体層
22は、導電ペーストが充填されたスルホールやビアホ
ール23上にも形成される。このように構成されたセラ
ミック基板を焼成し、セラミック回路基板に図4に示す
ように回路部品を実装し、電子機器に使用する。As shown in FIG. 3, the conventional ceramic substrate is formed by depositing Ag on a ceramic substrate 21 made of alumina or the like.
The conductive layer 22 is formed by printing a conductive paste composed mainly of powder or Cu powder and adding borosilicate glass or borosilicate glass and a thermoplastic resin thereto. The conductor layer 22 is also formed on the through holes and the via holes 23 filled with the conductive paste. The ceramic substrate thus configured is fired, circuit components are mounted on the ceramic circuit substrate as shown in FIG. 4, and used in an electronic device.
【0006】図4に示すように、セラミック多層基板2
4には、ビアホール25が設けられ、必要に応じて表面
層26と接続している。さらに、半導体27やチップ部
品30がリード28などを介して半田29によって、表
面導体層26に接続されている。As shown in FIG. 4, the ceramic multilayer substrate 2
4 is provided with a via hole 25, which is connected to the surface layer 26 as required. Further, the semiconductor 27 and the chip component 30 are connected to the surface conductor layer 26 by the solder 29 via the leads 28 and the like.
【0007】[0007]
【発明が解決しようとする課題】しかし、このような従
来の構成では、導電ペーストをスクリーン印刷して形成
される導体層22のパターン形状は、インクのニジミ、
ヒゲあるいはインクが透過するスクリーン(紗)の影響
による輪郭部の直線性の低下などの問題が発生し、設計
精度を実現することが困難であった。特に微細なパター
ン、例えば線幅が60μm以下のライン印刷では、ライ
ンの途切れなどの問題が発生し、60μmのパターンは
実用できなかった。However, in such a conventional configuration, the pattern shape of the conductor layer 22 formed by screen-printing a conductive paste has a pattern of ink bleeding,
It has been difficult to realize the design accuracy because problems such as a decrease in the linearity of the contour portion occur due to the influence of a screen (shade) through which a beard or ink penetrates. In particular, fine patterns, for example, line printing with a line width of 60 μm or less caused problems such as line breaks, and the 60 μm pattern was not practical.
【0008】また、表面の平滑性も悪く、表面粗さのバ
ラツキは±10μmを必要とするので半導体のフリップ
実装には採用が困難であった。Further, the surface is poor in smoothness and requires a variation of surface roughness of ± 10 μm, so that it is difficult to adopt it for semiconductor flip mounting.
【0009】さらに、導電性パターンの作成時には、8
50℃〜900℃の温度で基板全体が焼成されるので、
ガラスによってセラミック基板24と、導体層26は密
着力を増すが、上記ガラスにより導体層26の表面は、
金属箔に比べて、半田29の濡れは悪くなるという問題
があった。また経時変化として、半田29中に含まれる
Sn成分が導体層26の内部に拡散し、合金を形成し、
セラミック基板との接着が熱衝撃によりはずれるという
極めて重大な課題を有していた。Further, at the time of forming the conductive pattern, 8
Since the entire substrate is baked at a temperature of 50 ° C to 900 ° C,
The glass increases the adhesion between the ceramic substrate 24 and the conductor layer 26, but the surface of the conductor layer 26 is changed by the glass.
There is a problem that the solder 29 gets worse than the metal foil. Further, as a change with time, the Sn component contained in the solder 29 diffuses inside the conductor layer 26 to form an alloy,
There was a very serious problem that the adhesion with the ceramic substrate was released by thermal shock.
【0010】しかも、850〜900℃での焼成によっ
て、ビアホール25を形成する導体の過焼結による収縮
で導体層26との間で接触不良が生じるなどの課題も有
していた。Further, there is a problem that the firing at 850 to 900 ° C. causes contraction due to oversintering of the conductor forming the via hole 25, resulting in poor contact with the conductor layer 26.
【0011】本発明は、上記課題を解決するもので、微
細なパターンを精度良く形成でき、さらに、半田濡れ性
がよく、熱衝撃により密着強度が低下しない、信頼性に
優れたセラミック回路基板を提供することを目的とする
ものである。The present invention solves the above problems and provides a highly reliable ceramic circuit board which can form a fine pattern with high accuracy, has good solder wettability, and does not deteriorate the adhesion strength due to thermal shock. It is intended to be provided.
【0012】[0012]
【課題を解決するための手段】この課題を解決するため
に本発明のセラミック回路基板は、セラミック基板また
はビアホールを有するセラミック多層基板上に金属フィ
ラーと樹脂からなる導電性樹脂層を設け、前記導電性樹
脂層上に、金属箔層を設ける構成としたものである。In order to solve this problem, a ceramic circuit board of the present invention provides a conductive resin layer composed of a metal filler and a resin on a ceramic substrate or a ceramic multilayer substrate having via holes, The metal foil layer is provided on the functional resin layer.
【0013】[0013]
【作用】本発明は上記構成によって、予め精度良くパタ
ーン形成された金属箔パターンを積層するので、微細な
パターンも設計通りに高精度に形成できる。また、金属
箔層は表面平滑に形成でき、半田濡れ性もよい。金属箔
は密度が高いので、半田中に含まれるSn成分も拡散し
にくく、導電性樹脂層が熱衝撃による歪を吸収するの
で、経時変化による導体層とセラミック基板との密着強
度の低下も少ない。According to the present invention, since the metal foil patterns, which have been preliminarily patterned with high precision, are laminated by the above-mentioned constitution, fine patterns can be formed with high precision as designed. Further, the metal foil layer can be formed to have a smooth surface and has good solder wettability. Since the metal foil has a high density, the Sn component contained in the solder does not easily diffuse, and the conductive resin layer absorbs the strain caused by thermal shock, so that the adhesive strength between the conductor layer and the ceramic substrate is not deteriorated over time. .
【0014】さらに、従来のように850℃〜900℃
の焼成工程を経ないので、ビアホール中の金属粉末導体
の過焼結による収縮に基因するビアホールと金属箔層間
の接触不良が発生せず、長期間にわたり高い信頼性を保
つことができることとなる。Further, as in the conventional case, 850 ° C. to 900 ° C.
Since the firing step is not performed, contact failure between the via hole and the metal foil layer due to shrinkage due to over-sintering of the metal powder conductor in the via hole does not occur, and high reliability can be maintained for a long period of time.
【0015】[0015]
【実施例】以下に本発明の一実施例のセラミック回路基
板について、図面を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A ceramic circuit board according to an embodiment of the present invention will be described below with reference to the drawings.
【0016】図1に本発明の一実施例のセラミック回路
基板の構成を示す。図1に示すように、アルミナやガラ
スからなるセラミック多層基板1にCu導体粉を主材と
するビアホール2を設け、その上にAg粉を導電材とす
る光硬化性または熱硬化性のエポキシ樹脂導体パターン
3を、さらに表面平滑なCu箔4を重ね、半導体ベアチ
ップ5がAuバンプ6を通じ半田7によって、Cu箔4
に電気的に接続されている。同じく、チップコンデンサ
8が半田7によってCu箔4に電気的に接続されてい
る。FIG. 1 shows the structure of a ceramic circuit board according to an embodiment of the present invention. As shown in FIG. 1, a ceramic multi-layer substrate 1 made of alumina or glass is provided with a via hole 2 containing Cu conductor powder as a main material, and a photo-curing or thermosetting epoxy resin containing Ag powder as a conductive material is provided thereon. The conductor pattern 3 and the Cu foil 4 having a smoother surface are stacked, and the semiconductor bare chip 5 is passed through the Au bumps 6 by the solder 7 to form the Cu foil 4
Electrically connected to. Similarly, the chip capacitor 8 is electrically connected to the Cu foil 4 by the solder 7.
【0017】以上のように構成されたセラミック回路基
板について、以下に図1,図2を用いてその動作を説明
する。図2に示すように、セラミック基板9内に形成さ
れたビアホール10の上に形成された導電性樹脂層11
が、Cu箔12とビアホール10とを電気的に接続する
電極として動作し、また、Cu箔12とセラミック基板
9とを強固に接着する接着層としても動作している。The operation of the ceramic circuit board configured as described above will be described below with reference to FIGS. 1 and 2. As shown in FIG. 2, the conductive resin layer 11 formed on the via hole 10 formed in the ceramic substrate 9
However, it also operates as an electrode that electrically connects the Cu foil 12 and the via hole 10, and also as an adhesive layer that firmly bonds the Cu foil 12 and the ceramic substrate 9.
【0018】さらに、図1に示すように、Cu箔4はそ
の上に実装されるベアチップ5、チップコンデンサ8を
接続する半田7の濡れ性をよくする部品パッドとなる。
導電性樹脂層3は、セラミック基板1と実装する部品と
の間で発生する熱膨張差による歪を吸収する緩衝層とし
て動作する。Further, as shown in FIG. 1, the Cu foil 4 becomes a component pad for improving the wettability of the solder 7 for connecting the bare chip 5 and the chip capacitor 8 mounted thereon.
The conductive resin layer 3 operates as a buffer layer that absorbs strain due to the difference in thermal expansion generated between the ceramic substrate 1 and the component to be mounted.
【0019】以上のように本実施例によれば、部品を実
装するCu箔4をエッチングなどの方法で精度よくパタ
ーン形成した後、導電性樹脂層3を介してセラミック基
板に密着させることができる。また、Cu箔4はガラス
を含まないので半田濡れ性が良好となる。As described above, according to this embodiment, the Cu foil 4 for mounting the component can be precisely patterned by a method such as etching, and then the Cu foil 4 can be adhered to the ceramic substrate through the conductive resin layer 3. . Further, since the Cu foil 4 does not contain glass, the solder wettability is good.
【0020】また、密度の高いCu箔4はSnの拡散が
遅く、しかも、導電性樹脂層3が、部品とセラミック基
板間で生じる熱膨張差による歪を吸収するので、Cu箔
4と導電性樹脂層3によって形成される表面層とセラミ
ック多層基板1との密着力を低下させることもない。Further, the Cu foil 4 having a high density is slow in the diffusion of Sn, and the conductive resin layer 3 absorbs the strain caused by the difference in thermal expansion between the component and the ceramic substrate. The adhesion between the surface layer formed by the resin layer 3 and the ceramic multilayer substrate 1 is not reduced.
【0021】さらに、従来例のように850〜900℃
という高温での熱処理を施さないため、ビアホール2の
金属導体の過焼結による収縮もないので、ビアホール2
と導電性樹脂層3との接触不良をなくすことができる。Further, as in the conventional example, 850 to 900 ° C.
Since the heat treatment at a high temperature is not performed, there is no shrinkage due to oversintering of the metal conductor of the via hole 2.
It is possible to eliminate poor contact between the conductive resin layer 3 and the conductive resin layer 3.
【0022】なお、本実施例では、セラミック多層基板
1の材料をアルミナとガラスを主成分としたが、他のセ
ラミック材を使用することもできる。また、Agをフィ
ラーとしたエポキシ樹脂導電性樹脂層も他の金属と他の
樹脂の組み合わせも可能である。また、金属箔4として
Cu箔を用いたが、半田付けができる金属箔であれば何
でもかまわない。In this embodiment, the material of the ceramic multilayer substrate 1 is mainly composed of alumina and glass, but other ceramic materials can be used. Further, the epoxy resin conductive resin layer containing Ag as a filler may be a combination of another metal and another resin. Although Cu foil is used as the metal foil 4, any metal foil that can be soldered may be used.
【0023】[0023]
【発明の効果】以上の実施例の説明から明らかなように
本発明によれば、セラミック回路基板がセラミック基板
上に形成された、金属フィラーと樹脂からなる導電性樹
脂層と、導電性樹脂層上に形成された金属箔層から構成
されるので、金属箔を予め精度良くパターン加工するこ
とができ、微細パターンを形成することができる。ま
た、金属箔であるため、半田濡れ性も良く半田中に含ま
れるSnの拡散による密着強度の低下もない。As is apparent from the above description of the embodiments, according to the present invention, a conductive resin layer made of a metal filler and a resin, in which a ceramic circuit board is formed on a ceramic substrate, and a conductive resin layer Since the metal foil layer is formed on the metal foil layer, the metal foil can be patterned in advance with high precision and a fine pattern can be formed. Further, since it is a metal foil, the solder wettability is good and there is no reduction in adhesion strength due to diffusion of Sn contained in the solder.
【0024】さらに、高温処理を必要としないので導電
性樹脂層は、ビアホールとの接続を確実にし、熱膨張差
による部品と基板の歪を吸収し、導体層と基板の密着強
度を低下させない。Further, since the high temperature treatment is not required, the conductive resin layer ensures the connection with the via hole, absorbs the strain between the component and the substrate due to the difference in thermal expansion, and does not reduce the adhesion strength between the conductor layer and the substrate.
【図1】本発明の一実施例のセラミック回路基板に電子
部品を実装した状態を示す断面図FIG. 1 is a sectional view showing a state in which electronic components are mounted on a ceramic circuit board according to an embodiment of the present invention.
【図2】同セラミック回路基板の構成を示す断面図FIG. 2 is a cross-sectional view showing the structure of the ceramic circuit board.
【図3】従来のセラミック回路基板の構成を示す断面図FIG. 3 is a sectional view showing the structure of a conventional ceramic circuit board.
【図4】同セラミック回路基板に電子部品を実装した状
態を示す断面図FIG. 4 is a sectional view showing a state where electronic components are mounted on the ceramic circuit board.
1 セラミック多層基板 2 ビアホール 3 導電性樹脂層 4 金属箔層 1 Ceramic Multilayer Substrate 2 Via Hole 3 Conductive Resin Layer 4 Metal Foil Layer
Claims (2)
に形成された金属フィラーと樹脂を主体としてなる導電
性樹脂層と、前記導電性樹脂層上に形成された金属箔層
から構成されるセラミック回路基板。1. A ceramic circuit comprising a ceramic substrate, a conductive resin layer mainly composed of a metal filler and a resin formed on the ceramic substrate, and a metal foil layer formed on the conductive resin layer. substrate.
ミック多層基板である請求項1記載のセラミック回路基
板。2. The ceramic circuit board according to claim 1, wherein the ceramic board is a ceramic multilayer board having via holes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4012755A JPH05206598A (en) | 1992-01-28 | 1992-01-28 | Ceramic circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4012755A JPH05206598A (en) | 1992-01-28 | 1992-01-28 | Ceramic circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05206598A true JPH05206598A (en) | 1993-08-13 |
Family
ID=11814226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4012755A Pending JPH05206598A (en) | 1992-01-28 | 1992-01-28 | Ceramic circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05206598A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007305741A (en) * | 2006-04-10 | 2007-11-22 | Murata Mfg Co Ltd | Ceramic multilayer board, and its manufacturing method |
JP2012222312A (en) * | 2011-04-14 | 2012-11-12 | Aica Kogyo Co Ltd | Substrate with built-in electronic components and manufacturing method of the same |
-
1992
- 1992-01-28 JP JP4012755A patent/JPH05206598A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007305741A (en) * | 2006-04-10 | 2007-11-22 | Murata Mfg Co Ltd | Ceramic multilayer board, and its manufacturing method |
JP2012222312A (en) * | 2011-04-14 | 2012-11-12 | Aica Kogyo Co Ltd | Substrate with built-in electronic components and manufacturing method of the same |
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