JPS5842259A - Ceramic package for semiconductor - Google Patents

Ceramic package for semiconductor

Info

Publication number
JPS5842259A
JPS5842259A JP56139479A JP13947981A JPS5842259A JP S5842259 A JPS5842259 A JP S5842259A JP 56139479 A JP56139479 A JP 56139479A JP 13947981 A JP13947981 A JP 13947981A JP S5842259 A JPS5842259 A JP S5842259A
Authority
JP
Japan
Prior art keywords
chip
metal frames
metal
wires
insulating material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56139479A
Other languages
Japanese (ja)
Other versions
JPH022289B2 (en
Inventor
Nobuhiko Mizuo
水尾　允彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56139479A priority Critical patent/JPS5842259A/en
Publication of JPS5842259A publication Critical patent/JPS5842259A/en
Publication of JPH022289B2 publication Critical patent/JPH022289B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable to perform automatic bonding of an IC chip by a method wherein thick films of thewiring part and the edges on one side of metal frames are connected electrically, the edges on another side of the metal frames and bonding pads of the semiconductor chip are connected with wires, and positioning is performed. CONSTITUTION:A heat resistively insulating material holding the metal frames 9 is fixed to the prescribed position on a ceramic substrate 1 with heat resistive adhesives, the edges of the metal frames 9 on one side are connected to the thick films 2 formed by printing and patterning on the ceramic substrate 1 or to pins 3 calked in holes of the ceramic substrate with low melting point solder or wires, and the edges on another side are connected to the bonding pads 6 of the IC chip 5 with the wires 7. Because the metal frames 9 are positioned on the heat resistively insulating material 8 of polyimide, etc., having favorable precision, by positioning the heat resistively insulating material 8 in relation to the IC chip 5, the bonding pads 6 of the IC chip 5 and the bonding parts of the metal frames 9 can be positioned having favorable precision. Accordingly automatic bonding can be performed having favorable reliability.

Description

【発明の詳細な説明】 本発明はワイヤボンディングの自動化が可能な多ビンｘ
ＣＡｇＩケージに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a multi-bin x
Regarding the CAgI cage.

Ｌ８１のケースは多くの矛盾す為要求を同時に満足させ
為必要がある。すなわち、（イ）多端子、（ロ）小形、
（ハ）曳好な放熱特性、（へ）プリント板装着時の取扱
い０１ＦＪ＆さ、あ為いは自動化への適合、（ホ）低価
格、（へ）テＶグ及びリー＃ＰＯポｙディングエ寝の自
動化などである。In the case of L81, there are many contradictory requirements, so it is necessary to satisfy them at the same time. In other words, (a) multi-terminal, (b) small size,
(c) Good heat dissipation characteristics, (f) Handling when printed board is installed, suitability for automation, (e) Low price, (f) TeVg and Li #PO Poyding automation, etc.

メモｖＬｓｘは一般に端子数が少なく、又、同一端子を
Ｘ％Ｙアドレスに共用することも可能で、従来ｔ）ＤＩ
Ｐで大きな問題はな−０一方、論理ＬＳＩは回路構成上
必然的に入出力端子数が増大す為。マイク冨プ■セｔ！
％現在４０ビン前後Ｏものが主であｐ％ＤＩＰＫ収容さ
れてい為が、今後、その高速化とビット数の増加の光め
に端子数の増大が必要となゐ。ＤＩＰ形式ではその長さ
方向の寸法が端子数に比例して増大し、占有面積の増大
、リードインダクタンスの増加が著し％Ａｏ仁の解決と
して４辺にビンを４つ正方形ケース０採用ヤ、ビン間隔
０１００ｍ１１Ｔｈら！ｉ　０ｉａｌｌへ０Ｊｌｌｚ、
ｈ。Memo vLsx generally has a small number of terminals, and it is also possible to share the same terminal for X%Y address.
There is no big problem with P-0On the other hand, logic LSI inevitably increases the number of input/output terminals due to its circuit configuration. Mike Tomi Set!
%Currently, DIPKs with around 40 bins are mainly accommodated, but in the future it will be necessary to increase the number of terminals in order to increase speed and increase the number of bits. In the DIP format, the lengthwise dimension increases in proportion to the number of terminals, resulting in an increase in occupied area and a significant increase in lead inductance.As a solution to this problem, a square case with four bins on each side is adopted. Bin spacing 0100m11Th et al! i 0iall to 0Jllz,
h.

あるいは３重ビン配列などが既に実用化された。Alternatively, a triple bin arrangement has already been put into practical use.

菖１図は従来の多ビｙＩＣパッケージＯ断面図−）と上
ｗｌＩ（ｂ）であ為。ＩＩＩにおいて１はセラセック基
板、２は−に’Ｊｔｙ／ｍｌ！ＫＭｏ／Ｍｍ＊Ａｗｚｅ
Ｐｔ＊ｊＬｇ、Ｒｄ等の貴金属の粉末とガラスフリット
を有機バインダに分散させたペーストをスクリーンを通
して印刷し、゛焼成して貴金属の合金化、ガラス成分と
七う建ツクの融着を行９た厚膜である。３はセラｔｙ夕
基Ｍ１の孔にビンを挿入し、基板表面又は裏面と接す為
部分をかしめたビンであ為。Diagram 1 is a cross-sectional view of a conventional multi-vib IC package O-) and the upper figure (b). In III, 1 is Cerasec substrate, 2 is -'Jty/ml! KMo/Mm*Awze
A paste in which noble metal powder such as Pt*jLg, Rd and glass frit were dispersed in an organic binder was printed through a screen, and fired to alloy the noble metal and fuse the glass component and the structure. It is a thick film. Step 3: Insert a bottle into the hole of the cell assembly M1, and use the bottle with the part caulked to make contact with the front or back side of the board.

４ａＩＣチツプ５をマクントするハンダである。4a This is solder for mounting IC chip 5.

６はＩＣ？ｙ７上のポンディングパッド、７はポンディ
ングパッド６と厚膜の配Ｍ１２との間のワイヤでＴｏ為
。6 is IC? The bonding pad on y7, 7 is the wire between the bonding pad 6 and the thick film wiring M12.

ワイヤボンディング方式はこれまで手動が主体でＴｏ９
九が、ＬＳＩのように電極数が増すにつれてオペレータ
の技能依存度の高ｉこの方法では、作業性中信頼性面で
問題があるため、オートポ／〆の一発がここ数年急速和
進められ、メ峰すやバＩ−ンｍ織機能をもった上々オー
ト、フルオートｌンダが急速に畳及してきて匹る。Until now, the wire bonding method was mainly manual, and it was top 9.
However, as the number of electrodes increases like in LSI, the dependence on the operator's skill increases.This method has problems in terms of workability and reliability, so the use of autopolymerization/finishing has been rapidly promoted in recent years. , semi-automatic and fully automatic vehicles with automatic weaving functions are rapidly gaining popularity.

チップ、ボンディングの自動化はリードフレームを用い
る＊ｍ封止（毫−ルド）ＩＣにつ一七。The automation of chip and bonding is based on sealed ICs that use lead frames.

既に以前から貴行されてＶ％為ところであ〕、ビン数の
比験的少な−モールドＬＳＩについて適用されている。By the way, this method has already been proposed for some time and has been applied to molded LSIs with a relatively small number of bins.

しかし多ビンのセランシクケース入１Ｌ８Ｉにつ−て適
用は中中遅れた。However, the application of 1L8I in a multi-bottle cellanic case was delayed for some time.

七うｆｙタメタライズ方式は収縮率の関係で精度が出す
Ｗ鐘・何工程の１動化が困−と云う問題がありた。つｔ
ＬＩｃ？ツブをセラ建、り基板に！ラントしてオートボ
ン〆でＩ　Ｃ？　ｙプ上のポンディングパッドの位置を
位置決めしても、セラセック基板上の厚模鵞のパターン
１’ｌｌ［が収縮率の関係で出な一為、所定のポンディ
ｙｌが行えないと云う問題があった。The problem with the seven-fy metallization method was that it was difficult to integrate all the processes into one motion to achieve accuracy due to the shrinkage rate. Tsut
LIc? Build the whelk into a ceramic board! Is it IC with runt and autobon? Even if the position of the bonding pad on the y-plate is determined, the pattern 1'll of the thick pattern on the Cerasec substrate cannot be produced due to the shrinkage rate, so there is a problem that the predetermined bonding pad cannot be performed. there were.

本発明は、上述の点に鎌みｅされたもので、配！！ＩＩ
Ｉ及びチνプマクン）１１に導電性の厚膜パターンを形
成し九セラ建ツク基板、該セラ建ｔり基板の孔に配設さ
れ該配＊Ｓの厚ｇ＃ｃ＊続し九ビン、該チＶプマウント
部にマクントされ友中導体チップ、皺半導体テＶグのボ
ｙディンダパッｙと鍍配線部間がワイヤで接続された半
導体セテ電ｖｌパｔケージにおいて、ノリ一二ンβされ
たメＩル７一ムを保持する所定形状の絶縁材を該セラｔ
ツタ基板上に設は該配線部の厚膜と該メタル７レームの
一端とが電気的に接続され、該メタル７レームの他端と
骸半導体チップのポンプイングツ（ット０とがワイヤで
結線されたことを特徴とする半導体セラ建ツクパｔケー
ジを提供するものである・　−以下本発明の実施例を詳
述する。The present invention addresses the above-mentioned points, and is arranged! ! II
A conductive thick film pattern is formed on 11 (I and chip) 11, and a conductive thick film pattern is formed on a nine cell-built substrate, which is arranged in the hole of the cell-built substrate, and the thickness of the layer *S is g#c* followed by nine bottles, The conductor chip mounted on the chip V mount part, the voided pad of the wrinkled semiconductor V board, and the plated wiring part were connected by wires in the semiconductor set electric VL package, and the glue was applied. The insulating material of a predetermined shape that holds the mail member 71 is
The thick film of the wiring part and one end of the metal 7 frame are electrically connected to each other on the vine board, and the other end of the metal 7 frame is connected to the pumping point (cut 0) of the skeleton semiconductor chip by a wire. Embodiments of the present invention will be described in detail below.

ｇｉｇｓは重置−の多ビンＩＣパｊケージの断面図−及
び上面ｌ！ｇｌ伽）である、菖１図と同一部分にクーで
は同一符号を用いた。Gigs is a cross-sectional view and top view of a stacked multi-bin IC package! The same symbols were used in Kuu for the same parts as in Iris 1.

重置ｇｌｉが従来と異ｔｈのは、第３図にその平面図で
示すようなメタル７レーム９を保持した耐熱性絶縁材を
セラｔｖり基板１上Ｏ所定位置に嬉雪図の如く耐熱性接
着剤で固定し、メタル７レーム９の一端をセライック基
［１上に印刷パメー轟ンダされた厚膜３或−はセラ々ｔ
り基板の孔にかしめたビン３＃／ｃ低鵬点ロク又はワイ
ヤで接続し、他端をＩＣ？ｙ７８０ボンデイングバｔド
・にワイヤ７で接続した点でＴｏ為。The difference between the overlapping GLI and the conventional one is that the heat-resistant insulating material holding the metal 7 frame 9 is placed in a predetermined position on the substrate 1 as shown in the plan view in Fig. 3. The metal 7 frame 9 is fixed with adhesive, and one end of the metal 7 frame 9 is coated with a thick film 3 or ceramic film 3 printed on the ceramic base 1.
Connect the bottle 3#/c to the hole in the board with a low-point lock or wire, and connect the other end to the IC? At the point where wire 7 was connected to the Y780 bonding board.

メタルフレーム９はポリインド醇の耐熱性絶縁材８上に
精度良く位置決めされているのでＩＣチップ５に対して
耐熱性絶縁材８を位置決めすることによＩ、ＩＣ？ｙプ
５のポンプイングツ（ラド６とメタルフレーム９のボン
ディング部とは精ｌ！曳く位置決めされる。従ってオー
トポｙデインダを信１１度よく行うことができる。Since the metal frame 9 is precisely positioned on the heat-resistant insulating material 8 made of polyimide, by positioning the heat-resistant insulating material 8 with respect to the IC chip 5, I, IC? The pumping parts (the bonding portions of the Rad 6 and the metal frame 9) of the YP 5 are precisely positioned. Therefore, the autopolymerization can be carried out with high reliability.

８に３図の如きメタルフレームを保持した耐熱性絶縁材
は、例えはＩフィルムキャリヤ方式によりフィルムテー
プに鋼（Ｃｍ）はくを張付轄、ＧＯＣｌｌはくをホトエ
Ｖチンダしてフレームを形′成し、フィルムを所定形状
に工ｔチンダおよびプレスで打抜いたりして形成する。The heat-resistant insulating material holding the metal frame as shown in Figure 8 and 3 can be made by applying a steel (Cm) foil to the film tape using the I film carrier method, and then forming the frame by applying the GOCll foil to a hot V-cinder. Then, the film is formed into a predetermined shape by punching or punching with a press.

該メタルフレームと保持用の絶縁フィルムの基板上への
職付けはガイドホールを利用し、外部接続端子の少くと
も２本以上に挿入し位置決めを行うようにすれはよい。The metal frame and the holding insulating film can be placed on the substrate by using guide holes, and by inserting and positioning the metal frame into at least two or more external connection terminals.

【図面の簡単な説明】[Brief explanation of the drawing]

菖１図は従来の多ビンセラ々ＶりＩＣノ（ツケージＯ断
面図と平面図、第２図は本発明の多ピンセライックＩＣ
パッケージのＩｆ向図と平面図、菖３図は本発明に用い
る耐熱性絶縁材で保持されたメタルフレームの要部平面
図である。 １；セラミック基板、２：厚漢、 ３：ピン、　　　　　　４：半田、 ５：ＩＣチップ、　　　６：ボンディングパッド、７：
ワイヤ、　　　　　８：耐熱性絶縁材、９：メタルフレ
ーム。 一一枦一　イ　Ｃ李］。 犀　２　門 奪３目 （ａ＞Figure 1 is a cross-sectional view and plan view of a conventional multi-pin cell IC. Figure 2 is a cross-sectional view and plan view of a conventional multi-pin cell IC.
The If direction view and plan view of the package, and the 3rd figure are plan views of essential parts of a metal frame held by a heat-resistant insulating material used in the present invention. 1; Ceramic board, 2: Thick plate, 3: Pin, 4: Solder, 5: IC chip, 6: Bonding pad, 7:
Wire, 8: Heat resistant insulation material, 9: Metal frame. 11 I C Lee]. Rhinoceros 2 gate robber 3 eyes (a>

Claims (1)

【特許請求の範囲】[Claims] 配置部及びテッグマクン）ＩＩＫ導電性の軍属バＩ−ン
を形成し九セラ々ツク基板、該セラ々ツタ基板Ｏ孔に配
設され該配線部の厚１ｌＥＫ接続したピン、該チップマ
ウント部にマウントされ九半導体チップ、該半導体チッ
プのボンディングパット°ト該配１１部間がワイヤで接
続され九半導体セッセＶクパッケージにお−で、パター
ンエングされたメタル７レームを保持する所定形状Ｏ絶
縁材を該セラ建ツタ基覆上に設は該配線部の厚膜と皺メ
タル７レーム〇一端とが電気的Ｖｃｌ！ａされ、該メタ
ル７レームの他鴫と骸半導体チップのポンディｙグパ！
Ｆド°とがワイヤで結線され九ことを特徴とする半導体
上う々ツタパッケージ。Arrangement part and test pin) IIK conductive military pin is formed on the ceramic board, the pin arranged in the O hole of the ceramic board and connected to the wiring part with a thickness of 11EK, and mounted on the chip mount part. The 9 semiconductor chips, the bonding pads of the semiconductor chips, and the 11 parts of the wiring are connected with wires, and the 9 semiconductor chips are placed in a V package, and an insulating material of a predetermined shape holding the patterned metal 7 frames is formed. The thick film of the wiring section and one end of the wrinkled metal 7 frame are connected to the electrical Vcl! A, and the metal 7 frame and other parts of the metal and the semiconductor chips are also included!
A semiconductor top package characterized by having F and ° connected with wires.
JP56139479A 1981-09-04 1981-09-04 Ceramic package for semiconductor Granted JPS5842259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56139479A JPS5842259A (en) 1981-09-04 1981-09-04 Ceramic package for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56139479A JPS5842259A (en) 1981-09-04 1981-09-04 Ceramic package for semiconductor

Publications (2)

Publication Number Publication Date
JPS5842259A true JPS5842259A (en) 1983-03-11
JPH022289B2 JPH022289B2 (en) 1990-01-17

Family

ID=15246203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56139479A Granted JPS5842259A (en) 1981-09-04 1981-09-04 Ceramic package for semiconductor

Country Status (1)

Country Link
JP (1) JPS5842259A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106635A (en) * 1985-11-01 1987-05-18 Mitsubishi Electric Corp Semiconductor device
US5093282A (en) * 1988-04-13 1992-03-03 Kabushiki Kaisha Toshiba Method of making a semiconductor device having lead pins and a metal shell
JPH0489926U (en) * 1990-02-14 1992-08-05

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638846A (en) * 1979-09-07 1981-04-14 Fujitsu Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638846A (en) * 1979-09-07 1981-04-14 Fujitsu Ltd Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106635A (en) * 1985-11-01 1987-05-18 Mitsubishi Electric Corp Semiconductor device
US5093282A (en) * 1988-04-13 1992-03-03 Kabushiki Kaisha Toshiba Method of making a semiconductor device having lead pins and a metal shell
JPH0489926U (en) * 1990-02-14 1992-08-05
JP2562090Y2 (en) * 1990-02-14 1998-02-04 旭光学工業株式会社 Field-of-view adjustment device for real image finder

Also Published As

Publication number Publication date
JPH022289B2 (en) 1990-01-17

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