JPS6286847A - Chip carrier - Google Patents

Chip carrier

Info

Publication number
JPS6286847A
JPS6286847A JP60228126A JP22812685A JPS6286847A JP S6286847 A JPS6286847 A JP S6286847A JP 60228126 A JP60228126 A JP 60228126A JP 22812685 A JP22812685 A JP 22812685A JP S6286847 A JPS6286847 A JP S6286847A
Authority
JP
Japan
Prior art keywords
electronic component
chip
printed circuit
component chip
printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60228126A
Other languages
Japanese (ja)
Inventor
Toru Higuchi
徹 樋口
Toshiyuki Yamaguchi
敏行 山口
Takeshi Kano
武司 加納
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP60228126A priority Critical patent/JPS6286847A/en
Publication of JPS6286847A publication Critical patent/JPS6286847A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49433Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the reliability of a wire bonding between an electronic part chip and printed circuits by extending the end of every other printed circuit to the electronic part chip side from other printed circuit to form the extension in a wide portion. CONSTITUTION:An electronic part chip 2 is mounted at the center on a circuit board 1, and many printed circuits 3a, 3b which arrive at between the vicinity of the chip 2 and the end of the board 1 are formed substantially radially on the board 1. The every other printed circuits 3a are formed smaller than the width of the other printed circuits 3b, the end of the chip 2 side of the circuit 3a formed smaller than the width is extended from the other printed circuit 3b to the chip 2 side to form the extension in a wide portion 4. The chip 2 and the ends of the printed circuits 3a, 3b are wire bonded at 5 therebetween.

Description

【発明の詳細な説明】 [技術分野] 本発明は、ICパッケージなどとして用いられるチップ
キャリアに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a chip carrier used as an IC package or the like.

[背景技術I ICパッケージなどのような電子素子は、半導体チップ
などの電子部品チップをリードフレームに取り付けた状
態で樹脂封止や気密封止してパッケージングすることに
よって作成されている。そしてこのような電子素子にあ
って、高集積化による端子数の増加に伴って電子部品チ
ップを支持するキャリアとしてリードフレームの替わり
に配線板を用いる試みがなされており、さらにこのよう
な端子数の増加【二対応して端子をキャリアとしての配
線板の四方から引き出すようにした試みもなされている
[Background Art I Electronic devices such as IC packages are manufactured by packaging an electronic component chip such as a semiconductor chip attached to a lead frame by resin sealing or airtight sealing. As the number of terminals in such electronic devices increases due to higher integration, attempts are being made to use wiring boards instead of lead frames as carriers to support electronic component chips. In response to the increase in the number of terminals, attempts have been made to draw out the terminals from all sides of the wiring board used as a carrier.

第2図はかかる端子を四方から引き出すようにしたチッ
プキャリアAの一例を示すものであり、配線基板1の表
面にリード#amのプリント回路3を放射状に多数本設
けると共に配線基板1の四方端部にそれぞれ設けた半円
状のスルーホール8の内周にスルーホールメッキ層9を
形成してこのスルーホールメッキ層つとプリント回路3
とを連続させ、配線基板1の中央部に実装した半導体装
置プなどの電子部品チップ2と各プリント回路3とをワ
イヤーボンディング5によって接続することによって形
成されている。このチップキャリアAはプリント配線な
どが施された配線ボード等の表面に実装され、配線ボー
ドの配線回路に端子部となるスルーホールメッキ層9を
半田付けなどで接続することによって使用に供される。
FIG. 2 shows an example of a chip carrier A in which such terminals are drawn out from all sides, in which a large number of printed circuits 3 having leads #am are provided radially on the surface of the wiring board 1, and the terminals are drawn out from all four sides of the wiring board 1. A through-hole plating layer 9 is formed on the inner periphery of the semicircular through-hole 8 provided in each section, and this through-hole plating layer and the printed circuit 3 are formed.
It is formed by connecting each printed circuit 3 to an electronic component chip 2 such as a semiconductor device mounted in the center of the wiring board 1 by wire bonding 5. This chip carrier A is mounted on the surface of a wiring board etc. on which printed wiring etc. are applied, and is put into use by connecting the through-hole plating layer 9, which will become a terminal part, to the wiring circuit of the wiring board by soldering etc. .

この第2図に示すようなチップキャリアAにあって、電
子部品チップ2の集積化が高度になると端子数が着しく
増加し、この端子数の増加に伴って配線基板1の表面に
設けるプリント回路3の本数も増加することになり、こ
のようにプリント回路3の本数が多くなるとプリント回
路3の形成密度が高くなる。そして配線基板1に放射状
に設けられる各プリント回路3は一方の端部が電子部品
チップ2に近接するように設けられることになるが、電
子部品チップ2の一辺の長さは短いためにこのようにプ
リント回路3の本数が増加すると第3図に示すように各
プリント回路3の電子部品チップ2側の端部の幅が非常
に狭くなる。しかしこの上うに各プリント回路3の幅が
狭くなると、電子部品チップ2とプリント回路3の端部
との間に施すワイヤボンディング5が難しくなり、ワイ
ヤボンディング5の信頼性が低下することになるもので
ある。正確なワイヤボンディング5のためにはプリント
回路3の幅寸法lは通′M100μ程度以上であること
が必要とされている。
In the chip carrier A shown in FIG. 2, as the integration of electronic component chips 2 becomes more advanced, the number of terminals steadily increases. The number of circuits 3 also increases, and as the number of printed circuits 3 increases in this way, the density of forming the printed circuits 3 increases. Each printed circuit 3 provided radially on the wiring board 1 is provided so that one end is close to the electronic component chip 2, but since the length of one side of the electronic component chip 2 is short, As the number of printed circuits 3 increases, the width of the end of each printed circuit 3 on the electronic component chip 2 side becomes extremely narrow, as shown in FIG. However, as the width of each printed circuit 3 becomes narrower, it becomes difficult to perform the wire bonding 5 between the electronic component chip 2 and the end of the printed circuit 3, and the reliability of the wire bonding 5 decreases. It is. For accurate wire bonding 5, the width l of the printed circuit 3 is required to be approximately 100 μm or more.

そこでこの幅寸法lを太き(形成するためには、第4図
に示すように電子部品チップ2とプリント回路3の端部
との開の距離りを大きくとる必要があるが、このように
距NILを大きくとると電子部品チップ2とプリント回
路3との間に施すワイヤボンディング5が長くなり、こ
の場合もワイヤボンディング5の信頼性が低下すること
になるものである。
Therefore, in order to make the width l thicker, it is necessary to increase the opening distance between the electronic component chip 2 and the end of the printed circuit 3 as shown in FIG. If the distance NIL is increased, the wire bonding 5 formed between the electronic component chip 2 and the printed circuit 3 becomes longer, and the reliability of the wire bonding 5 also decreases in this case.

[発明の目的] 本発明は、上記の点に鑑みて為されたものであり、電子
部品チップとプリント回路との間に施すワイヤボンディ
ングの信頼性に優れたチップキャリアを提供することを
目的とするものである。
[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a chip carrier with excellent reliability in wire bonding performed between an electronic component chip and a printed circuit. It is something to do.

[発明の開示J しかして本発明に係るチップキャリアは、配線基板1の
表面の中央部に電子部品チップ2を実装すると共に配線
基板1の表面に電子部品チップ2の近傍と配線基板1の
端部との間に至るプリント回路3 a、 3 bを略放
射状に多数本設け、一本おきのプリント回路3aを他の
プリント回路3bの幅寸法よりも小さく形成し、この幅
寸法を小さく形成したプリント回路3aの電子部品チッ
プ2fflllの端部を他のプリント回路3bよりも電
子部品チップ側2に延長してこの延長部を幅広部4に形
成し、電子部品チップ2と各プリント回路3 a、 3
 bの端部との開にワイヤボンディング5を施しで成る
ことを特徴とするものであり、一本おきのプリント回路
3aを他のプリント回路3bの幅寸法よりも小さく形成
すると共にこの幅寸法を小さく形成したプリント回路3
aの電子部品チップ2WIの端部な旭のプリント回路3
aよりも電子部品チップ側2に延長してこの!L艮部を
幅広部4に形成するようにして上記目的を達成したもの
であって、以下本発明を実施例により詳述する。
[Disclosure of the Invention J] However, the chip carrier according to the present invention has an electronic component chip 2 mounted on the central part of the surface of the wiring board 1, and a chip carrier in the vicinity of the electronic component chip 2 and the edge of the wiring board 1 on the surface of the wiring board 1. A large number of printed circuits 3a and 3b are provided in a substantially radial manner between the two printed circuits 3a and 3b, and every other printed circuit 3a is formed to be smaller in width than the other printed circuits 3b. The end of the electronic component chip 2ffllll of the printed circuit 3a is extended toward the electronic component chip side 2 from other printed circuits 3b, and this extended portion is formed into a wide part 4, and the electronic component chip 2 and each printed circuit 3a, 3
This circuit is characterized in that wire bonding 5 is applied to the opening with the end of the circuit b, and every other printed circuit 3a is formed to be smaller in width than the other printed circuits 3b, and this width dimension is Small printed circuit 3
Asahi's printed circuit 3, which is the end of the electronic component chip 2WI in a.
Extend this from a to the electronic component chip side 2! The above object has been achieved by forming the L-shaped part in the wide part 4, and the present invention will be described in detail below with reference to Examples.

配線基板1は積層板などの絶縁板の表面に銅箔やアルミ
ニウム箔などの金属箔を8!層接着したり、あるいは金
属板の表面に絶縁!1血層を介して金属箔を積層接着し
たりして形成されるもので、金属箔にエツチングなどの
常用手段を施して不要部分を除去することによって、多
数本のプリント回路3 a、 3 bを配線基板1の表
面に設けである。
The wiring board 1 has metal foil such as copper foil or aluminum foil on the surface of an insulating board such as a laminate. Layer adhesion or insulation on the surface of a metal plate! It is formed by laminating and bonding metal foils through a single layer, and by removing unnecessary parts by etching or other common methods on the metal foils, a large number of printed circuits 3a, 3b are formed. is provided on the surface of the wiring board 1.

このプリント回路3 a、 3 bは電子部品チップ2
を実装すべき部分と配線基板1の端部との間において放
射状に形成されるもので、各プリント回路3m、3bの
端部はplS2図のように配線基板1の端部に設けられ
た半円形のスルーホール8の内周に施したスルーホール
メッキff19と連続するようにしである。
These printed circuits 3a and 3b are electronic component chips 2
The printed circuits 3m and 3b are formed radially between the part to be mounted and the end of the wiring board 1, and the ends of each printed circuit 3m and 3b are connected to the half provided at the end of the wiring board 1 as shown in figure plS2. It is designed to be continuous with the through-hole plating ff19 applied to the inner periphery of the circular through-hole 8.

またこのプリント回路3 lit 3 bは池方のra
部がそれぞれ電子部品チップ2を実装すべき部分に近接
するに設けられるが、第1図に示すように各プリント回
路3 a、 3 bの一本おきのプリント回路3aの電
子部品チップ2側の端部の幅寸法11はそれぞれ他の一
本おきのプリント回路3bの電子部品チップ2側のi部
の幅寸法12よりも小さく形成しである。従ってプリン
ト回路3 a、 3 bの端部と電子部品チップ2との
間の距@Ll(Ll<L)を大きくとったりするような
必要なく、プリント回路3aの幅寸法11を小さくする
Xんプリント回路3bの幅寸法12(b=1>を大きく
とることができることになる。そして幅寸法11を小さ
く形成した各プリント回路3aにおいては第1図に示す
ように、プリント回路3らの端部よりも電子部品チップ
2fllへ回路が延長してあり、この回路の延長部分の
幅寸法を幅広にして幅広部4が形成しである1幅広部4
はその幅寸法!、が幅寸法12とほぼ等しい寸法になる
ように形成されるものである。
Also, this printed circuit 3 lit 3 b is Ikekata's RA
As shown in FIG. The width dimension 11 of each end portion is smaller than the width dimension 12 of the i portion on the electronic component chip 2 side of every other printed circuit 3b. Therefore, there is no need to increase the distance @Ll (Ll<L) between the ends of the printed circuits 3a, 3b and the electronic component chip 2, and the width dimension 11 of the printed circuit 3a can be reduced. This means that the width dimension 12 (b=1>) of the circuit 3b can be increased.In each printed circuit 3a in which the width dimension 11 is formed small, as shown in FIG. Also, a circuit is extended to the electronic component chip 2fll, and the width dimension of the extended portion of this circuit is widened to form a wide part 4.1 Wide part 4
is its width dimension! , is formed to be approximately equal to the width dimension 12.

このようにプリント回路3 m、 3 bを形成した配
線基板1の表面の中央部に半導体チップなどの電子部品
チップ2を搭載して実装し、そして電子部品チップ2と
各プリント回路3 at a bの電子部品チップ2g
Aの端部、すなわちプリント回路3aにおける幅広部4
やプリント回路3bのj1部との間に11図に鎖線で示
すようにワイヤボンディング5を施し、電子部品チップ
2と各プリント回路3a、3bとを電気的に接続するこ
とによって、プリント回路3 a、 3 bを施した配
線基板1をキャリアとしたチップキャリアAを作成する
ものである。
An electronic component chip 2 such as a semiconductor chip is mounted and mounted on the center part of the surface of the wiring board 1 on which the printed circuits 3 m and 3 b are formed in this way, and the electronic component chip 2 and each printed circuit 3 at a b are mounted. 2g of electronic component chips
The end of A, that is, the wide part 4 in the printed circuit 3a
By performing wire bonding 5 as shown by the chain line in FIG. 11 between the electronic component chip 2 and the j1 part of the printed circuit 3b, and electrically connecting the electronic component chip 2 and each printed circuit 3a, 3b, the printed circuit 3a , 3b, a chip carrier A is prepared using the wiring board 1 as a carrier.

ここでこのようにワイヤボンディング5を施すlこあた
って、プリント回路3IJはその端部を電子部品チップ
2から遠ざける必要な(その幅寸法12を大きく形成す
ることができ、またプリント回路3ali幅寸法11を
小さく形成されていても幅広部4の幅寸法13を大きく
形成することができるために、電子部品チップ2と幅寸
法が大トくなったプリン)3a、3bの端部との間でし
かも短い距離で、ワイヤボンディング5を確実におこな
うことができることになり、ワイヤボンディング5の信
頼性を高めることができることになるものである。そし
てこのように電子部品チップ2を実装したのちに、必要
に応じて電子部品チップ2をパフケーノングなとしてI
Cパッテージなどとして仕上げるものである。
In order to perform the wire bonding 5 in this way, the printed circuit 3IJ needs to have its end portion kept away from the electronic component chip 2 (its width dimension 12 can be made large, and the width dimension of the printed circuit 3IJ can be made large). 11 is formed small, the width dimension 13 of the wide part 4 can be made large, so that the width dimension 13 of the wide part 4 can be made large, so that there is Moreover, the wire bonding 5 can be reliably performed over a short distance, and the reliability of the wire bonding 5 can be improved. After the electronic component chip 2 is mounted in this manner, the electronic component chip 2 may be made into a puff canon if necessary.
It is finished as a C package.

[発明の効果1 上述のように本発明にあっては、配線基板の表面に電子
部品チップの近傍と配線基板の端部との間に至るプリン
ト回路を略放射状に多数本設け、一本おきのプリント回
路を他のプリント回路の幅寸法よりも小さく形成し、こ
の幅寸法を小さく形成したプリント回路の電子部品チッ
プ側の端部を他のプリント回路よりも電子部品チップ側
に延長してこのj!艮部を幅広部に形成し、電子部品チ
ップと各プリント回路の端部との間にワイヤボンディン
グを施すようにしたので、プリント回路の端部と電子部
品チップとの間の距離を大きくとったりするような必要
なく、一本おきのプリント回路の幅寸法を小さくするR
ん他の一本おきのプリント回路の幅寸法を大きく形成で
きることになり、また幅寸法を小さく形成したプリント
回路においては幅広部において回路の幅寸法を大きく形
成できることになり、電子部品チップと幅寸法が大きく
なったプリントの端部との間にしがも短い距離でワイヤ
ボンディングを確実におこなうことがで終ることになっ
て、ワイヤボンディングの信頼性を高めることができる
ものである。
[Effect of the invention 1 As described above, in the present invention, a large number of printed circuits are provided on the surface of the wiring board in a substantially radial manner extending between the vicinity of the electronic component chip and the end of the wiring board, and every other printed circuit is This printed circuit is made smaller in width than the other printed circuits, and the end of the printed circuit with the smaller width on the electronic component chip side is extended further toward the electronic component chip than the other printed circuits. j! The wire bonding part is formed into a wide part and wire bonding is performed between the electronic component chip and the end of each printed circuit, so it is possible to increase the distance between the end of the printed circuit and the electronic component chip. R to reduce the width dimension of every other printed circuit without the need for
This means that every other printed circuit can be made larger in width, and in printed circuits that are made smaller in width, the width of the circuit can be made larger in the wide part. As a result, wire bonding can be reliably performed at a short distance between the print edge and the edge of the print, which has a large size, and the reliability of wire bonding can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明におけるチップキャリアの一部の平面図
、第2図はチップキャリアの全体を示す縮小斜視図、第
3図は従来例におけるチップキャ+77の一部の平If
図、第4図は他の従来例におけるチップキャリアの一部
の平面図である。 1は配線基板、2は電子部品チップ、3はプリント回路
、4は幅広部、5はワイヤボンディングである。
FIG. 1 is a plan view of a portion of the chip carrier according to the present invention, FIG. 2 is a reduced perspective view showing the entire chip carrier, and FIG. 3 is a plan view of a portion of the chip carrier 77 in the conventional example.
FIG. 4 is a plan view of a part of a chip carrier in another conventional example. 1 is a wiring board, 2 is an electronic component chip, 3 is a printed circuit, 4 is a wide part, and 5 is a wire bonding.

Claims (1)

【特許請求の範囲】[Claims] (1)配線基板の表面の中央部に電子部品チップを実装
すると共に配線基板の表面に電子部品チップの近傍と配
線基板の端部との間に至るプリント回路を略放射状に多
数本設け、一本おきのプリント回路を他のプリント回路
の幅寸法よりも小さく形成し、この幅寸法を小さく形成
したプリント回路の電子部品チップ側の端部を他のプリ
ント回路よりも電子部品チップ側に延長してこの延長部
を幅広部に形成し、電子部品チップと各プリント回路の
端部との間にワイヤボンディングを施して成ることを特
徴とするチップキャリア。
(1) An electronic component chip is mounted in the center of the surface of the wiring board, and a large number of printed circuits are provided on the surface of the wiring board in a substantially radial manner extending between the vicinity of the electronic component chip and the edge of the wiring board. Every other printed circuit is formed to be smaller in width than the other printed circuits, and the end of the printed circuit with the smaller width on the electronic component chip side is extended closer to the electronic component chip than the other printed circuits. A chip carrier characterized in that the extension part of the lever is formed into a wide part and wire bonding is performed between the electronic component chip and the end of each printed circuit.
JP60228126A 1985-10-14 1985-10-14 Chip carrier Pending JPS6286847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60228126A JPS6286847A (en) 1985-10-14 1985-10-14 Chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60228126A JPS6286847A (en) 1985-10-14 1985-10-14 Chip carrier

Publications (1)

Publication Number Publication Date
JPS6286847A true JPS6286847A (en) 1987-04-21

Family

ID=16871619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60228126A Pending JPS6286847A (en) 1985-10-14 1985-10-14 Chip carrier

Country Status (1)

Country Link
JP (1) JPS6286847A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0371646U (en) * 1989-11-16 1991-07-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0371646U (en) * 1989-11-16 1991-07-19

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