JPS6286846A - Manufacture of chip carrier - Google Patents

Abstract

PURPOSE:To reduce an exfoliation occurring at a through hole plating layer in case of cutting a circuit board by cutting the board along a line displaced from the center of the hole to cut the board along a line passing the hole to form a chip carrier. CONSTITUTION:A round through hole 2 is formed in an insulating substrate 1, a through hole plating layer 3 is formed on the inner periphery of the hole 2, and a conductor circuit 3 continued to the layer 3 is formed on the substrate 1 to form a circuit board 5. The board 5 is punched by a line l passing the hole 2. At this time, the line l is displaced from the center O of the circle of the hole 2, the layer 3 is exposed to form the circular arc section of nonsemicircular shape, and the layer 3 is used as a terminal of a chip carrier A.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field 1] The present invention relates to a method for manufacturing a chip carrier used as a substrate for an electronic device such as an IC package.

[Back valve technique] Electronic devices such as IC packages are manufactured by attaching an electronic component chip such as a semiconductor chip to a lead frame, sealing it with resin or airtight, and then puffing it. As the number of terminals for such electronic devices increases, attempts have been made to use wiring boards instead of lead frames as carriers for supporting electronic component chips. Furthermore, in response to an increase in the number of terminals, attempts have been made to draw out the terminals from all sides of the wiring #i@ as a carrier.

FIG. 5 shows an example of a chip carrier A in which such terminals are drawn out from all sides, and a conductive circuit 4 for lead wires is provided on the surface of the wiring board 5.
Through-hole plating N3 is formed on the inner periphery of the semicircular through-holes 2 provided at the four ends of the wiring board 5, and the through-hole/stack layer 3 and the conductor circuit 4 are connected to each other.
It is formed by connecting an electronic component chip 11 such as a semiconductor chip mounted in the center of the board to each conductor circuit 4 by bonding 12 such as wire bonding. This chip carrier A is mounted on the surface of a wiring board etc. on which printed wiring etc. are applied, and is put into use by connecting the through-hole plating layer 3, which will serve as a terminal part, to the wiring circuit of the wiring board by soldering etc. .

The manufacturing of the chip carrier A shown in FIG. 5 is carried out as shown in FIGS. 6 and 7. That is, first, as shown in FIG. 6(a), a metal foil 14 such as t14M or aluminum foil is coated on the surface of the insulating substrate 1.
Glue 8!1 layer. The insulating base @1 is made by stacking multiple sheets of prepreg made by impregnating a glass cloth or the like with a thermosetting resin face such as epoxy resin or phenol resin and drying it, then molding it under heat and pressure. During this molding, the metal foil 14 is laminated at the same time as the insulating substrate 1 is molded by performing heat and pressure molding with the metal foil 14 overlaid on the surface of the outermost layer of the prepreg. 6 As the insulating substrate 1, a metal plate is used as the substrate and the surface is absolutely M01W.
tM can be used, and by using a metal plate as a substrate in this way, the chip carrier can effectively dissipate the heat generated by the electronic component chip due to the excellent thermal conductivity of the metal plate. can be created.

Next, as shown in FIG. 6(b), round through holes 2 are formed in the insulating substrate 1 on which the metal foils 14 are laminated in this manner, penetrating both sides. A plurality of through holes 2 are provided on a line forming a square. Thereafter, the metal @ 14 is processed by common means such as etching to remove unnecessary parts, and a conductor circuit 4 is formed at the periphery of the through hole 2 in continuity with the conductor circuit 4 as shown in FIG. A through-hole land 8 and a plated lead wire 15 formed continuously with the through-hole land 8 are provided, and electricity is applied from the plated lead wire 15 to the inner periphery of the through hole 2 as shown in FIG. 6(c). The through-hole plating layer 3 is provided by performing metal plating such as copper plating. In this way, it is possible to obtain a wiring board 5 in which a conductive circuit 4, through-hole lands 8, and plated lead wires 15 are provided on an insulating board 1 as shown in FIG. After this, the outer shape of the wiring board 5 is punched along a line l passing through each through hole 2 shown by the chain line in FIG. 7, and semicircular through holes 2 are formed on the outer peripheral end surface as shown in FIG. Through hole 7
A chip carrier A is obtained in which the 71 layer 3 is exposed as a terminal portion.

Conventionally, when punching the outer diameter of the wiring board 5 in this way, the wiring board 5 has been punched through each through hole 2.
However, if the wiring board 5 is punched and cut at ml passing through the center of the through-hole 2, the through-hole will be cut as shown by arrow C in Fig. 8. The plating layer 3 peels off from the inner peripheral surface of the through hole 2, causing the through hole to fail! When the fI rice cake 3 is used as a terminal portion of the chip carrier A, a problem arises in that reliability is reduced. This peeling of the through-hole plating layer 3 is performed by cutting along the line p passing through the center of the through-hole 2, so that the through-hole plating layer 3 is cut at the thinnest part. This is thought to be caused by the fact that the stress applied to the thinnest cut end surface of the through-hole plating layer 3 causes the through-hole plating layer 3 to buckle. , Therefore, when the thickness of the wiring board 5 increases, especially when the thickness becomes 0.8IB-
If the temperature exceeds this level, a large amount of stress is applied to the through-hole plating M3 when cutting the wiring board 5, and peeling of the through-hole/plating layer 3 is likely to occur.

[Object of the Invention] The present invention has been made in view of the above points, and provides a method for manufacturing a chip carrier that can reduce peeling that occurs in the through-hole plating layer when cutting a wiring board. The purpose is to

[Disclosure of the Invention 1 The method for manufacturing a chip carrier according to the present invention is to form a circular through hole 2 in an insulating substrate 1, and to apply through hole plating NJ3 on the inner periphery of the through hole 2 to the insulating substrate 1. A wiring board 5 is prepared by providing conductor circuits 4 connected to the through-hole plating M3 on the surface thereof, and the wiring board 5 is cut along a line that passes through the through-hole 2 and deviates from the center of the through-hole 2. and
The wiring board 5 is cut along a line that deviates from the center of the through hole 2 to reduce peeling of the through hole plating layer 3.The present invention will be described in detail below with reference to examples.

The wiring board 5 can be produced in the same manner as shown in FIGS. 6(a), 6(b), and 7(c) and FIG. 7 described above. Then, as described above, the wiring board 5 is created by laminating the metal foil 14 on the insulating board 1 as shown in FIG. 6(b).
Then, a plurality of round through holes 2 are drilled along the lines forming the square, and then the metal foil 14 is processed by conventional means such as etching to remove unnecessary parts, and the wiring base! ! A conductor circuit 4 is formed on the surface of i5, a through-hole land 8 is formed in a ring shape at the periphery of the through-hole 9 continuous with the conductor circuit 4, and a plated lead is formed continuously with the through-hole land 8. A line 15 is provided respectively. After this, by applying current from plating +7-)'#i15, metal plating such as copper plating is applied to the entire inner circumference of the through-hole 2 as shown in Fig. 6 (C) to form a through-hole plating layer 3. Do it like this.

After forming the through-hole plating layer 3, through-hole land 8, and conductor circuit 4 on the wiring board 5 in this way, the wiring board By punching and cutting 5, a chip carrier A having an outer diameter as shown in FIG. 5 can be obtained. At this time, the line I is set so as to deviate from the center O of the circle of each through hole 2, and this line I
By cutting the wiring board 5 along the lines shown in FIG. It is used as a terminal section.

If the wiring board 5 is cut along llAl, which is off the center of the through hole 2, as shown in FIG. Through-hole plating layer 3
The width of the cut Wr end surface can be made larger than the width a of the cut end surface where the wiring board 5 is cut, and the through-hole plating M3 can be cut with a large thickness. The cut end surface of the hole plating layer 3 becomes larger in area, causing the through hole plating M3 to buckle or break! ! This makes it possible to prevent the peeling needle from coming off the inner peripheral surface of the through hole 2 due to the peeling.

At this time, the direction in which the line 1 is deviated from the center of the through hole 2 may be either toward the outside of the portion of the wiring base [5 that is to become the chip carrier A] or toward the inside.

As the thickness of the insulating substrate 1 of the wiring board 5 increases, the stress during cutting also increases, so it is necessary to increase the amount of displacement of the cutting line l from the center of the through hole 2. That is, as shown in FIG. 3, the radius of the through hole 2 is R (mm), the dimension by which MAl should be displaced along the line passing through the center O of the through hole 2 is r (m-), and x=r/ If defined as RXJOO, that is, if x is the value of the percentage of the radius R of the through hole by which M/ should be shifted by 1°, then the thickness L of the insulating substrate 1 (
M so that it fits X that satisfies the following formula for mm)
It is preferable to set the position of a2.

100>x≧(200/11)Xt-i00/11 The relationship between X and t is shown in Figure 4, and the value of do it. In addition, in FIG. 3, the line ρ. With the right side closer to the outside of the part of the wiring board 5 that should become the chip carrier A, @
The left side of 1 o is shown as being closer to the inside of the portion of the wiring board 5 that should become the chip carrier A, and the right side of the center in the MS4 diagram is shown as 411. The portion to the left of the center is shown as being closer to the outside of the portion of the circuit board 5 that should become the chip carrier A, and the portion to the left of the center is shown as being closer to the inside of the portion of the wiring board 5 that should become the chip carrier A. From the graph in Figure 4, for example, when the thickness of the insulating substrate 1 is 1.5 mm+, X is 20%.
It is best to set the line l to #lρ. It can be seen that it is better to set the position closer to the outside or inside by about 20% or more of the radius R of the through hole 2.

[Effects of the Invention] As described above, in the present invention, when cutting a wiring board along a line passing through a through hole to create a chip carrier, the wiring board is cut along a line that deviates from the center of the through hole. Therefore, by increasing the width of the cut end surface where the through-hole plating layer is cut, it is possible to cut the through-hole plating layer with a thicker thickness, and the area of the through-hole plating layer is reduced by the stress when cutting the wiring board. This reduces the risk of the through-hole plating layer peeling off from the inner peripheral surface of the through-hole due to the increased cut end surface, which reduces reliability when the through-hole plating layer is used as a terminal part of a chip carrier. This can be prevented.

[Brief explanation of drawings]

Fig. 1 (aHb) is a plan view of a part of the wiring board and an enlarged view of the through-hole plating layer part in one manufacturing step in the present invention, Fig. 2 is an enlarged perspective view of a part of the same, and Fig. 3 is an enlarged view of the same through-hole part as above, Figure 4 is a graph showing the relationship between the displacement of the cutting line and the thickness of the insulating substrate, Figure 5 is a perspective view of the chip carrier, and Pt56 diagrams (a), (b) ( c) is a cross-sectional view of a part of each step of manufacturing the chip carrier, 7th
The figure is a plan view of one of the steps of manufacturing the same as above, and FIG. 8 is an enlarged perspective view of a part of the conventional chip carrier. 1 is an insulating substrate, 2 is a through hole, 3 is a through hole plating layer, 4 is a conductor circuit, and 5 is a #1 wiring board.

Claims (1)

[Claims] (1) A wiring board is formed by forming a round through hole through the insulating substrate, providing a through hole plating layer on the inner periphery of the through hole, and providing a conductor circuit connected to the through hole plating layer on the surface of the insulating substrate. A method for manufacturing a chip carrier, which comprises creating a wiring board, and cutting the wiring board along a line that passes through a through hole and deviates from the center of the through hole.