JPS56146256A - Hybrid ic device - Google Patents
Hybrid ic deviceInfo
- Publication number
- JPS56146256A JPS56146256A JP4933180A JP4933180A JPS56146256A JP S56146256 A JPS56146256 A JP S56146256A JP 4933180 A JP4933180 A JP 4933180A JP 4933180 A JP4933180 A JP 4933180A JP S56146256 A JPS56146256 A JP S56146256A
- Authority
- JP
- Japan
- Prior art keywords
- corners
- semiconductor element
- substrate
- solder layers
- fitted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Casings For Electric Apparatus (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
PURPOSE:To increase a mechanical strength and a radiation effect by a method wherein solder layers with range thereof is limited at four corners including a part corresponding to a semiconductor element are formed on the reverse side of a ceramic substrate fitted with the semiconductor element, and a metallic casing is attached through the solder layers. CONSTITUTION:The first solder layer 25 is formed on the reverse side of the ceramic substrate 11 fitted with the semiconductor element 12, so as to be extended to the corners 25a, 25b of the substrate 11 only within the range corresponding to the installation of the element 12 required for the radiating action. The second and third solder layers 26a, 26b are formed at other corners also to be attached to a metallic substrate 15. Thereby, the solderings can be performed without bubbles and gaps, and the hybrid integrated circuit satisfactory in the mechanical adhesive strength and the radiation characteristic can be formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4933180A JPS56146256A (en) | 1980-04-15 | 1980-04-15 | Hybrid ic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4933180A JPS56146256A (en) | 1980-04-15 | 1980-04-15 | Hybrid ic device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56146256A true JPS56146256A (en) | 1981-11-13 |
JPS6125222B2 JPS6125222B2 (en) | 1986-06-14 |
Family
ID=12827997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4933180A Granted JPS56146256A (en) | 1980-04-15 | 1980-04-15 | Hybrid ic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56146256A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0726988U (en) * | 1994-06-06 | 1995-05-19 | 三洋電機株式会社 | Optical recording disc |
EP0751569A2 (en) * | 1995-06-26 | 1997-01-02 | Siemens Aktiengesellschaft | Hybrid power circuit |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0530971Y2 (en) * | 1987-01-19 | 1993-08-09 |
-
1980
- 1980-04-15 JP JP4933180A patent/JPS56146256A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0726988U (en) * | 1994-06-06 | 1995-05-19 | 三洋電機株式会社 | Optical recording disc |
EP0751569A2 (en) * | 1995-06-26 | 1997-01-02 | Siemens Aktiengesellschaft | Hybrid power circuit |
EP0751569A3 (en) * | 1995-06-26 | 1998-12-16 | Siemens Aktiengesellschaft | Hybrid power circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6125222B2 (en) | 1986-06-14 |
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