JPS57176738A - Connecting structure for flip chip - Google Patents

Connecting structure for flip chip

Info

Publication number
JPS57176738A
JPS57176738A JP6179281A JP6179281A JPS57176738A JP S57176738 A JPS57176738 A JP S57176738A JP 6179281 A JP6179281 A JP 6179281A JP 6179281 A JP6179281 A JP 6179281A JP S57176738 A JPS57176738 A JP S57176738A
Authority
JP
Japan
Prior art keywords
substrate
layer
solder bump
interval
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6179281A
Other languages
Japanese (ja)
Inventor
Kunio Sakuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP6179281A priority Critical patent/JPS57176738A/en
Publication of JPS57176738A publication Critical patent/JPS57176738A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the improper connection caused by a thermal deformation by providing a spacer made of a conductor layer and a resin layer on a substrate to suitably restrict the interval between a substrate and an integrated circuit element when the element is electrically connected to the substrate with a solder bump. CONSTITUTION:An IC chip 1 having a solder bump 5 and a substrate having a conductor pattern 7 are restricted at a suitable interval by a spacer made of a conductor layer 10 and a resin layer 11. The material of the layer 10 is formed on the same material as the pattern 7 such as, copper, the layer 11 is formed of epoxy or polyurethane solder resist in a thickness of approx. 20mum. In this manner, the swelling at the center of the solder bump 5 can be suppressed by the operation of an interval control layer. Accordingly, the deformation produced due to the difference of the thermal expansion coefficient between the IC chip and the substrate can be readily absorbed, thereby reducing the improper connection.
JP6179281A 1981-04-23 1981-04-23 Connecting structure for flip chip Pending JPS57176738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6179281A JPS57176738A (en) 1981-04-23 1981-04-23 Connecting structure for flip chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6179281A JPS57176738A (en) 1981-04-23 1981-04-23 Connecting structure for flip chip

Publications (1)

Publication Number Publication Date
JPS57176738A true JPS57176738A (en) 1982-10-30

Family

ID=13181297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6179281A Pending JPS57176738A (en) 1981-04-23 1981-04-23 Connecting structure for flip chip

Country Status (1)

Country Link
JP (1) JPS57176738A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6073250U (en) * 1983-10-25 1985-05-23 セイコーインスツルメンツ株式会社 circuit board structure
JPS62206843A (en) * 1986-03-07 1987-09-11 Hitachi Ltd Connecting method for semiconductor element
US5196371A (en) * 1989-12-18 1993-03-23 Epoxy Technology, Inc. Flip chip bonding method using electrically conductive polymer bumps
US5879761A (en) * 1989-12-18 1999-03-09 Polymer Flip Chip Corporation Method for forming electrically conductive polymer interconnects on electrical substrates
US6137063A (en) * 1998-02-27 2000-10-24 Micron Technology, Inc. Electrical interconnections
EP0969503A3 (en) * 1998-06-30 2002-03-20 Seiko Instruments Inc. Electronic circuit device
US6946732B2 (en) * 2000-06-08 2005-09-20 Micron Technology, Inc. Stabilizers for flip-chip type semiconductor devices and semiconductor device components and assemblies including the same
US7670873B2 (en) 2006-02-08 2010-03-02 Fujitsu Limited Method of flip-chip mounting
US8101459B2 (en) 2001-08-24 2012-01-24 Micron Technology, Inc. Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6073250U (en) * 1983-10-25 1985-05-23 セイコーインスツルメンツ株式会社 circuit board structure
JPH0579170B2 (en) * 1986-03-07 1993-11-01 Hitachi Ltd
JPS62206843A (en) * 1986-03-07 1987-09-11 Hitachi Ltd Connecting method for semiconductor element
US6138348A (en) * 1989-12-18 2000-10-31 Polymer Flip Chip Corporation Method of forming electrically conductive polymer interconnects on electrical substrates
US5196371A (en) * 1989-12-18 1993-03-23 Epoxy Technology, Inc. Flip chip bonding method using electrically conductive polymer bumps
US5879761A (en) * 1989-12-18 1999-03-09 Polymer Flip Chip Corporation Method for forming electrically conductive polymer interconnects on electrical substrates
US5918364A (en) * 1989-12-18 1999-07-06 Polymer Flip Chip Corporation Method of forming electrically conductive polymer interconnects on electrical substrates
US5237130A (en) * 1989-12-18 1993-08-17 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
US6579744B1 (en) 1998-02-27 2003-06-17 Micron Technology, Inc. Electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive
US6355504B1 (en) 1998-02-27 2002-03-12 Micron Technology, Inc. Electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive
US6365842B1 (en) 1998-02-27 2002-04-02 Micron Technology, Inc. Electrical circuits, circuits, and electrical couplings
US6137063A (en) * 1998-02-27 2000-10-24 Micron Technology, Inc. Electrical interconnections
EP0969503A3 (en) * 1998-06-30 2002-03-20 Seiko Instruments Inc. Electronic circuit device
US6528889B1 (en) 1998-06-30 2003-03-04 Seiko Instruments Inc. Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip
US6946732B2 (en) * 2000-06-08 2005-09-20 Micron Technology, Inc. Stabilizers for flip-chip type semiconductor devices and semiconductor device components and assemblies including the same
US7041533B1 (en) 2000-06-08 2006-05-09 Micron Technology, Inc. Stereolithographic method for fabricating stabilizers for semiconductor devices
US8101459B2 (en) 2001-08-24 2012-01-24 Micron Technology, Inc. Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween
US7670873B2 (en) 2006-02-08 2010-03-02 Fujitsu Limited Method of flip-chip mounting

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