JPS54104286A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS54104286A
JPS54104286A JP1126478A JP1126478A JPS54104286A JP S54104286 A JPS54104286 A JP S54104286A JP 1126478 A JP1126478 A JP 1126478A JP 1126478 A JP1126478 A JP 1126478A JP S54104286 A JPS54104286 A JP S54104286A
Authority
JP
Japan
Prior art keywords
pad
input
adhering
metal ball
apply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1126478A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1126478A priority Critical patent/JPS54104286A/en
Publication of JPS54104286A publication Critical patent/JPS54104286A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE: To reduce input terminals of a package in number by deciding input states without changing a mask and extra connections, when an IC designed being given generality is used in several limited states.
CONSTITUTION: On the semiconductor substrate, input pad 1 is made via the insulation film and pads 2 and 3 are also made closely to both sides. By an IC mask pattern, pad 2 is connected to the earth potential VSS line inside of the IC, and pad 3 to the power potential VDD line inside of the IC. Adhering a metal ball with a nail head to position A makes it possible to apply VSS to input pad 1, and adhering a metal ball to position C markes it possible to apply VDD. When an external input signal is applied to pad 1, an ordinal line connection is made at position B. In this way, the remarkable effect of mounting on various products of the IC can be obtained.
COPYRIGHT: (C)1979,JPO&Japio
JP1126478A 1978-02-02 1978-02-02 Integrated circuit device Pending JPS54104286A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1126478A JPS54104286A (en) 1978-02-02 1978-02-02 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1126478A JPS54104286A (en) 1978-02-02 1978-02-02 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS54104286A true JPS54104286A (en) 1979-08-16

Family

ID=11773088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1126478A Pending JPS54104286A (en) 1978-02-02 1978-02-02 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS54104286A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132917A (en) * 1980-03-24 1981-10-17 Tokyo Shibaura Electric Co Automatic brewing apparatus of coffee
JPS57121251A (en) * 1981-01-20 1982-07-28 Nec Corp Integrated circuit device
JPS59163854A (en) * 1983-03-07 1984-09-14 Mitsubishi Electric Corp Semiconductor device
JPS6081852A (en) * 1983-10-11 1985-05-09 Nec Kansai Ltd Semiconductor device
US6803664B2 (en) * 2001-04-27 2004-10-12 Shinko Electric Industries Co., Ltd. Semiconductor package
US6809348B1 (en) 1999-10-08 2004-10-26 Denso Corporation Semiconductor device and method for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494994A (en) * 1972-04-27 1974-01-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494994A (en) * 1972-04-27 1974-01-17

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132917A (en) * 1980-03-24 1981-10-17 Tokyo Shibaura Electric Co Automatic brewing apparatus of coffee
JPS57121251A (en) * 1981-01-20 1982-07-28 Nec Corp Integrated circuit device
JPH0122735B2 (en) * 1981-01-20 1989-04-27 Nippon Electric Co
JPS59163854A (en) * 1983-03-07 1984-09-14 Mitsubishi Electric Corp Semiconductor device
JPS6081852A (en) * 1983-10-11 1985-05-09 Nec Kansai Ltd Semiconductor device
US6809348B1 (en) 1999-10-08 2004-10-26 Denso Corporation Semiconductor device and method for manufacturing the same
US6803664B2 (en) * 2001-04-27 2004-10-12 Shinko Electric Industries Co., Ltd. Semiconductor package
KR100896026B1 (en) * 2001-04-27 2009-05-11 신꼬오덴기 고교 가부시키가이샤 Semiconductor package

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