JPS6122358U - Pin grid array package - Google Patents

Pin grid array package

Info

Publication number
JPS6122358U
JPS6122358U JP1984105600U JP10560084U JPS6122358U JP S6122358 U JPS6122358 U JP S6122358U JP 1984105600 U JP1984105600 U JP 1984105600U JP 10560084 U JP10560084 U JP 10560084U JP S6122358 U JPS6122358 U JP S6122358U
Authority
JP
Japan
Prior art keywords
window
pin
wiring pattern
wiring
grid array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1984105600U
Other languages
Japanese (ja)
Other versions
JPH0134355Y2 (en
Inventor
一弘 須田
Original Assignee
株式会社東芝
東芝マイクロエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝, 東芝マイクロエレクトロニクス株式会社 filed Critical 株式会社東芝
Priority to JP1984105600U priority Critical patent/JPS6122358U/en
Publication of JPS6122358U publication Critical patent/JPS6122358U/en
Application granted granted Critical
Publication of JPH0134355Y2 publication Critical patent/JPH0134355Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ， ｂは本考案によるピングリッドアレイパ
ッケージの構造を示す斜視図およびそのＢ−Ｂ要部断面
図、第２図はそのピン配置例を説明するためのピングリ
ッドアレイパッケージ底面図、第３図は絶縁基板の構造
を示す斜視図、第４図は配線板の構造を示す斜視図、第
５図は従来のビングリッドパッケージのピンの配列状態
を示す底面図、第６図ａ， ｂは従来の配線構造を説明
するための斜視図及び部分断面図である。 １１ａ・・・・・・信号ピン、１１ｂ・・・・・・電源
ピン、２１・・・・・・パッケージ本体、２１ｅ′・・
・・・・配線層、１３６＊２２ａ・・・・・・ボンデイ
ングパッド、２３・・・・・・ホンデ，イングワイヤ、
２１・・・・・・電源ビン、２１ａ・・・・・・絶縁基
板、２１ｂ，２１ｈ・・・・・・孔、２１ｃ・・・・・
・金属膜、２１ｄ，２１ｋ・・・・・・窓部、２１ｅ・
・・・・・配線板、２１ｆ・・・・・・信号用配線パタ
ーン、２１ｆ′・・・・・・電源用の配線パターン、２
１ｇ・・・・・・スルーホール、２１ｉ・・・・・・粉
末金属、２１１・・・・・・絶縁層、２１ｍ・・・・・
・保持部。1A and 1B are perspective views showing the structure of a pin grid array package according to the present invention and a sectional view of essential parts thereof, and FIG. 2 is a bottom view of the pin grid array package for explaining an example of the pin arrangement. Fig. 3 is a perspective view showing the structure of the insulating substrate, Fig. 4 is a perspective view showing the structure of the wiring board, Fig. 5 is a bottom view showing the pin arrangement of a conventional bin lid package, Fig. 6a, b is a perspective view and a partial sectional view for explaining a conventional wiring structure. 11a...Signal pin, 11b...Power pin, 21...Package body, 21e'...
...Wiring layer, 136*22a...Bonding pad, 23...Honda, Ing wire,
21... Power bottle, 21a... Insulating board, 21b, 21h... Hole, 21c...
・Metal film, 21d, 21k...Window part, 21e・
...Wiring board, 21f...Signal wiring pattern, 21f'...Wiring pattern for power supply, 2
1g...Through hole, 21i...Powder metal, 211...Insulating layer, 21m...
・Holding part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 裏面に所定ピッチで複数の信号用および電源用のビンが
配設された絶縁基板上に、中央に窓部を有し、且つ、上
面に該窓部の近傍より前記各ピン位置に至る配線パター
ンをそれぞれ形成した配線層を一体に設けるとともに、
この配線層の上面は前記窓部位置に該窓部より開口寸法
の大きい窓を形成した被覆層で被覆し、また、前記配線
層の配線パターンは前記ピン位置より伸びるスルーホー
ルでそれそれ電気的に接続してなり、前記窓部には集積
回路チップを取付けて前記配線パターンとワイヤにて接
続するようにしたピングリッドアレイパッケージにおい
て、前記電源用のピンは前記窓部近傍位置に設けるとと
もに該電源用のピンに至る配線パターンは前記配線層に
スルーホールを設けて該配線層の裏面に導き、配線した
ことを特徴とするピングリッドアレイパッケージ。A wiring pattern that has a window in the center on an insulating substrate on which a plurality of signal and power supply bins are arranged at a predetermined pitch on the back surface, and that extends from the vicinity of the window to each of the pin positions on the top surface. In addition to integrally providing wiring layers each formed with
The upper surface of this wiring layer is covered with a covering layer in which a window with an opening size larger than that of the window is formed at the window position, and the wiring pattern of the wiring layer is formed by a through hole extending from the pin position. In the pin grid array package, in which an integrated circuit chip is attached to the window and connected to the wiring pattern by a wire, the power supply pin is provided near the window and is connected to the wiring pattern. A pin grid array package characterized in that a wiring pattern leading to a power supply pin is formed by providing a through hole in the wiring layer and guiding the wiring pattern to the back surface of the wiring layer.
JP1984105600U 1984-07-12 1984-07-12 Pin grid array package Granted JPS6122358U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984105600U JPS6122358U (en) 1984-07-12 1984-07-12 Pin grid array package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984105600U JPS6122358U (en) 1984-07-12 1984-07-12 Pin grid array package

Publications (2)

Publication Number Publication Date
JPS6122358U true JPS6122358U (en) 1986-02-08
JPH0134355Y2 JPH0134355Y2 (en) 1989-10-19

Family

ID=30664913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984105600U Granted JPS6122358U (en) 1984-07-12 1984-07-12 Pin grid array package

Country Status (1)

Country Link
JP (1) JPS6122358U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02230762A (en) * 1989-03-02 1990-09-13 Nec Corp Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57107059A (en) * 1980-12-25 1982-07-03 Fujitsu Ltd Semiconductor package
JPS5810846A (en) * 1981-07-10 1983-01-21 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57107059A (en) * 1980-12-25 1982-07-03 Fujitsu Ltd Semiconductor package
JPS5810846A (en) * 1981-07-10 1983-01-21 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02230762A (en) * 1989-03-02 1990-09-13 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0134355Y2 (en) 1989-10-19

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