JPS596563A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS596563A JPS596563A JP11653182A JP11653182A JPS596563A JP S596563 A JPS596563 A JP S596563A JP 11653182 A JP11653182 A JP 11653182A JP 11653182 A JP11653182 A JP 11653182A JP S596563 A JPS596563 A JP S596563A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- island
- pellet
- internal electrode
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は集積回路装置にかかり、とくにそのパッケージ
の電源用電極構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and particularly to a power source electrode structure of a package thereof.
近時集積回路の大規模化、高速化により集積回路に大き
な電流を供給する必要性が生じてきた。BACKGROUND ART In recent years, as integrated circuits have become larger and faster, it has become necessary to supply large currents to integrated circuits.
これに伴い従来無視出来たパッケージの電極及びその引
き出しによる電源電圧の降下及び動作時の過渡電流によ
る電源電圧の振れ等がより顕著になり、集積回路の電気
的マージンが減少し、更には誤動作の原因にまで発展す
る可能性がある。As a result, drop in power supply voltage due to package electrodes and their extraction, which could previously be ignored, and fluctuations in power supply voltage due to transient currents during operation have become more prominent, reducing the electrical margin of integrated circuits and further increasing the risk of malfunction. It may develop into a cause.
従来このような問題に対処する為、電源端子のインピー
ダンスを減少させた第１図に示すような集積回路パッケ
ージがある。第１図（ａ）は内部電極を設けたパッケー
ジ基板の上面図の１部である。Conventionally, in order to cope with such problems, there is an integrated circuit package as shown in FIG. 1 in which the impedance of the power supply terminal is reduced. FIG. 1(a) is a partial top view of a package substrate provided with internal electrodes.
第１図（ｂ）は断面図である。図中、１は集積回路のペ
レット、２はアイランド、２はアイランドのつりピン、
３はボンディング・ワイヤ、４はパッケージの基板、５
は電源用内部電極、６は信号用内部電極を表わす、この
ような集積パッケージにおいては、ペレットの電源パッ
ド（最低電位）とアイランド、アイランドのつりピンと
電源用内部電極とをボンディングすることにより電源端
子のインピーダンスを低くしチップに供給される電源電
圧の降下を小さくシ、動作時の過渡電流による電原電圧
の振れを小さくする考慮がなされている。FIG. 1(b) is a sectional view. In the figure, 1 is an integrated circuit pellet, 2 is an island, 2 is an island suspension pin,
3 is the bonding wire, 4 is the package substrate, 5
6 represents a power supply internal electrode, and 6 represents a signal internal electrode. In such an integrated package, the power supply terminal is connected by bonding the pellet's power supply pad (lowest potential) to the island, and the island's suspension pin to the power supply internal electrode. Consideration has been given to lowering the impedance of the chip to reduce the drop in the power supply voltage supplied to the chip, and to reduce fluctuations in the source voltage due to transient currents during operation.
しかしペレット上面の電源パッドとアイランド間をボン
ディングするためアイランド上のペレットのマウント位
置を中心からずらすため位置合わせが容易でない事、ペ
レット−アイランド間、電源用内部電極−アイランドの
つりピン間等段差が一定でない特殊なボンディングが必
要でオート・ボンダなどが使えない事等の欠点があった
。However, in order to bond between the power supply pad on the top surface of the pellet and the island, the mounting position of the pellet on the island is shifted from the center, so alignment is not easy. There were drawbacks such as the need for special bonding that was not consistent and the auto bonder etc. not being usable.
本発明は内部電極の内側にアイランドと導通した枠を設
けることにより、上記欠点を解消しインピーダンスの低
い電源端子を持つ集積回路パッケージを提供するもので
ある。The present invention solves the above-mentioned drawbacks by providing a frame inside the internal electrode that is electrically connected to the island, thereby providing an integrated circuit package having a power supply terminal with low impedance.
本発明は内部電極の内側にボンディング用の枠を設けた
パッケージの基板であって、前記枠がアイランド及びペ
レットの基板部と導通状態にあることを特徴とした集積
回路パッケージを有する集積回路装置である。又本発明
は前記アイランドとペレットの基板部が絶縁されている
ことを特徴とする前記載の集積回路装置である。The present invention relates to a package substrate having a bonding frame provided inside an internal electrode, and an integrated circuit device having an integrated circuit package characterized in that the frame is in a conductive state with the island and pellet substrate parts. be. Further, the present invention provides the above-described integrated circuit device, characterized in that the island and the substrate portion of the pellet are insulated.
本発明による実施例を１４２図に示す。第２図（Ｊｌ）
はパッケージ基板の上面図の１部である。第２図（ｂ）
は断面図である。図中、１は集積回路のペレット、２は
アイランド、３はボンディング・ワイヤ。An embodiment according to the present invention is shown in Figure 142. Figure 2 (Jl)
is a portion of a top view of the package substrate. Figure 2(b)
is a sectional view. In the figure, 1 is an integrated circuit pellet, 2 is an island, and 3 is a bonding wire.
４はパッケージの基板、５は電源用内部電極、６は信号
用内部電極、７は本発明により設けた枠を表わす。Reference numeral 4 represents a substrate of the package, 5 represents an internal electrode for power supply, 6 represents an internal electrode for signal, and 7 represents a frame provided according to the present invention.
以下、第２図により本発明による集積回路パッケージの
構造の特徴を説明する。ペレット１をマウントしたアイ
ランド２と内部電極の内側に設けた枠７とは導通状態に
ある。アイランドは通常最低電位となるため内部電極５
は最低電位用の電源端子となる。枠にはペレットのどの
部分からもボンディング可能でボンディングの本数を増
す事によりインピーダンスを減少させることが可能とな
る。又従来例のようにペレット上部とアイランド間をボ
ンディングする方法と同等の低インピーダンスの電源端
子が得られると共にアイランドにボンディングエリアを
用意する必要がないためペレットはアイランドの中央番
こマウントすることが出来、マウントの位置合せが容易
となる。更にボンディングの高低差もなくなりオート・
ボンダーによるボンディングも可能となる。信号用内部
電極とペレット間のボンディングは枠を越えてボンディ
ングされることになる。Hereinafter, the features of the structure of the integrated circuit package according to the present invention will be explained with reference to FIG. The island 2 on which the pellet 1 is mounted and the frame 7 provided inside the internal electrode are electrically connected. Since the island usually has the lowest potential, the internal electrode 5
becomes the power supply terminal for the lowest potential. Bonding can be done to the frame from any part of the pellet, and impedance can be reduced by increasing the number of bonds. In addition, a low-impedance power supply terminal equivalent to the conventional method of bonding between the upper part of the pellet and the island can be obtained, and there is no need to prepare a bonding area on the island, so the pellet can be mounted in the center of the island. , the positioning of the mount becomes easier. Furthermore, there is no difference in bonding height and auto
Bonding using a bonder is also possible. Bonding between the signal internal electrode and the pellet will be performed across the frame.
以上のように本発明は内部電極の内側に電源電極用の枠
を設けることにより、電源端子の低インピーダンス化を
図った上でペレットのマウントの簡単化、ボンディング
の簡単化がなされるという多大な効果のある集積回路パ
ッケージを有する集積回路装置である。As described above, the present invention provides a frame for the power supply electrode inside the internal electrode, thereby reducing the impedance of the power supply terminal, simplifying pellet mounting, and simplifying bonding. An integrated circuit device having an effective integrated circuit package.
第１図は従来の低インピーダンス電源端子を設けた集積
回路パッケージの上面図（ａ）と断面図（ｂ）である。
第２図は本発明による集積回路パッケージの上面図（ａ
）と断面図（ｂ）である。
尚、図において、ｌ・・・１集積回路のペレット、２・
・・・・・アイランド、２′・・・・・・アイランドの
つりピン。
３・・・・・・ボンディング・ワイヤ、４・・曲パッケ
ージの基板、５・・・・・・電源用内部電極、６・・画
信号用内部電極、７・・・・・・電極枠である。
ぢ’ｆ＝ １ しｄ＜ｂノ
）１２１４（レジFIG. 1 is a top view (a) and a cross-sectional view (b) of an integrated circuit package provided with a conventional low impedance power supply terminal. FIG. 2 is a top view of an integrated circuit package according to the present invention (a
) and a cross-sectional view (b). In the figure, l...1 integrated circuit pellet, 2...
...Island, 2'...Island hanging pin. 3...bonding wire, 4...substrate of curved package, 5...internal electrode for power supply, 6...internal electrode for image signal, 7...electrode frame be.ぢ'f= 1 sd<bノ)1214 (Register
Claims (3)
電極の枠を設け、前記枠がアイランドと導通状態にある
ことを特徴とした集積回路装置。(1) An integrated circuit device characterized in that a bonding electrode frame is provided inside the internal electrode of the package, and the frame is in electrical conduction with the island.
ていることを特徴とする特許請求の範囲第（１）項に記
載の集積回路装置。(2) The integrated circuit device according to claim (1), wherein electrical conduction is established between the island and the substrate portion of the pellet.
ていることを特徴とする特許請求の範囲第（１１項に記
載の集積回路装置。(3) The integrated circuit device according to claim 11, wherein the island and the substrate portion of the pellet are insulated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11653182A JPS596563A (en) | 1982-07-05 | 1982-07-05 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11653182A JPS596563A (en) | 1982-07-05 | 1982-07-05 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS596563A true JPS596563A (en) | 1984-01-13 |
Family
ID=14689425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11653182A Pending JPS596563A (en) | 1982-07-05 | 1982-07-05 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596563A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03171759A (en) * | 1989-11-30 | 1991-07-25 | Toshiba Corp | Semiconductor device |
| JPH04133341A (en) * | 1990-09-25 | 1992-05-07 | Matsushita Electric Works Ltd | Semiconductor chip carrier |
| US5343355A (en) * | 1992-06-30 | 1994-08-30 | Mitsubishi Denki Kabushiki Kaisha | Safety shutter device for drawout type switch gear |
| JPH0750313A (en) * | 1994-03-14 | 1995-02-21 | Hitachi Ltd | Semiconductor device |
| KR100273693B1 (en) * | 1995-03-31 | 2000-12-15 | 마이클 디. 오브라이언 | Semiconductor lead frame |
| US20180170576A1 (en) * | 2016-12-20 | 2018-06-21 | The Boeing Company | Conductive Fastening System for Composite Structures |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57107059A (en) * | 1980-12-25 | 1982-07-03 | Fujitsu Ltd | Semiconductor package |
-
1982
- 1982-07-05 JP JP11653182A patent/JPS596563A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57107059A (en) * | 1980-12-25 | 1982-07-03 | Fujitsu Ltd | Semiconductor package |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03171759A (en) * | 1989-11-30 | 1991-07-25 | Toshiba Corp | Semiconductor device |
| JPH04133341A (en) * | 1990-09-25 | 1992-05-07 | Matsushita Electric Works Ltd | Semiconductor chip carrier |
| US5343355A (en) * | 1992-06-30 | 1994-08-30 | Mitsubishi Denki Kabushiki Kaisha | Safety shutter device for drawout type switch gear |
| JPH0750313A (en) * | 1994-03-14 | 1995-02-21 | Hitachi Ltd | Semiconductor device |
| KR100273693B1 (en) * | 1995-03-31 | 2000-12-15 | 마이클 디. 오브라이언 | Semiconductor lead frame |
| US20180170576A1 (en) * | 2016-12-20 | 2018-06-21 | The Boeing Company | Conductive Fastening System for Composite Structures |
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