JPH0637421A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH0637421A
JPH0637421A JP4190706A JP19070692A JPH0637421A JP H0637421 A JPH0637421 A JP H0637421A JP 4190706 A JP4190706 A JP 4190706A JP 19070692 A JP19070692 A JP 19070692A JP H0637421 A JPH0637421 A JP H0637421A
Authority
JP
Japan
Prior art keywords
power
circuit
metal substrate
conductive path
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4190706A
Other languages
Japanese (ja)
Other versions
JP2919674B2 (en
Inventor
Hiroshi Hori
浩 堀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4190706A priority Critical patent/JP2919674B2/en
Publication of JPH0637421A publication Critical patent/JPH0637421A/en
Application granted granted Critical
Publication of JP2919674B2 publication Critical patent/JP2919674B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/207Diameter ranges
    • H01L2924/20752Diameter ranges larger or equal to 20 microns less than 30 microns
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/207Diameter ranges
    • H01L2924/20753Diameter ranges larger or equal to 30 microns less than 40 microns
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/207Diameter ranges
    • H01L2924/20754Diameter ranges larger or equal to 40 microns less than 50 microns
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/207Diameter ranges
    • H01L2924/2076Diameter ranges equal to or larger than 100 microns

Abstract

PURPOSE:To mount a power monotype semiconductor element in which a power circuit and a small signal circuit are made into a one chip. CONSTITUTION:A plurality of circuit elements are connected on a conductive path 3 formed on one main surface of a metal substrate formed through an insulating layer, an earth line or a power supply line of the conductive path 3 are electrically connected to the metal substrate 1 by a connection means 4, a power circuit part and a small signal group circuit part driving said power circuit part is made into a monolithic integrated circuit while ground potential is connected to the pads in the peripheries of a relatively thin wire 7 for a smal signal group circuit and a relatively thick wire 6 loaded on the metal substrate 1 with no mediation of an insulation layer 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は混成集積回路、特にパワ
ー部と小信号部とを集積化したパワーモノICを搭載し
た混成集積回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit equipped with a power mono IC in which a power section and a small signal section are integrated.

【0002】[0002]

【従来の技術】従来、パワー系の半導体素子を搭載した
混成集積回路は図2に示す如く、セラミックスあるいは
表面を陽極酸化したアルミニウム等の絶縁基板(11)
と、前記基板(11)上に任意の形状に設けられた導電
路(12)と、前記導電路(12)上に半田付けされた
ヒートシンク(13)とそのヒートシンク(13)上に
固着されたパワートランジスタ等のパワー系の素子(1
4)と、そのパワー素子(14)と周辺の導電路(1
2)とを接続するボンディングワイヤ線(15)とで構
成され、所望出力の混成集積回路が実現されている。
2. Description of the Related Art Conventionally, as shown in FIG. 2, a hybrid integrated circuit mounted with a power semiconductor element is an insulating substrate (11) made of ceramics or aluminum whose surface is anodized.
A conductive path (12) provided in an arbitrary shape on the substrate (11), a heat sink (13) soldered on the conductive path (12) and fixed on the heat sink (13). Power elements such as power transistors (1
4), its power element (14) and the surrounding conductive paths (1
2) and a bonding wire line (15) for connecting with (2), a hybrid integrated circuit of desired output is realized.

【0003】このような混成集積回路のヒートシンク上
に搭載されるパワー素子は、パワー段のみを構成する回
路が集積化されており、そのパワー素子を駆動させるド
ライバー用の小信号系の駆動用の回路素子は図では示さ
れてないがパワー素子の近傍の導電路上に接続され両者
が接続される。
The power element mounted on the heat sink of such a hybrid integrated circuit is an integrated circuit that constitutes only the power stage, and is used for driving a small signal system for a driver that drives the power element. Although not shown in the figure, the circuit element is connected on a conductive path in the vicinity of the power element and both are connected.

【0004】[0004]

【発明が解決しようとする課題】従って、従来の混成集
積回路ではパワー素子とそのパワー素子を駆動させる小
信号素子とが夫々別に搭載されているため約10A以上
の大出力を有するパワー用の混成集積回路が実現でき
る。しかし、最近、パワー部とそのパワー部を駆動させ
る小信号部とが1チップ化された(例えば高耐圧用のM
OSFET等)LSI素子が出現している。かかる素子
のパワー出力は前述した従来の混成集積回路の如き、大
出力ではなく約1〜10A位の大きさの出力である。
Therefore, in the conventional hybrid integrated circuit, the power element and the small signal element for driving the power element are separately mounted, so that a hybrid for power having a large output of about 10 A or more is provided. An integrated circuit can be realized. However, recently, the power section and the small signal section for driving the power section have been integrated into one chip (for example, M for high withstand voltage).
LSI elements such as OSFETs have appeared. The power output of such an element is not a large output as in the conventional hybrid integrated circuit described above, but an output of about 1 to 10 A.

【0005】しかしながら、放熱性を考慮するとヒート
シンクの厚みは最低でも2.5〜3mm位の厚みが必要
であり、パワー部の電極と導電路とを接続する約200
μm径の太いAlワイヤ線はボンディング接続できるも
のの、小信号部の電極と導電路とを接続する約40μm
径の細いAlワイヤ線はボンディング接続が行えず、パ
ワー部と小信号部とを備えた、いわゆるパワーモノIC
を従来の混成集積回路では実装することができなかっ
た。
However, in consideration of heat dissipation, the thickness of the heat sink needs to be at least 2.5 to 3 mm, and about 200 for connecting the electrode of the power section and the conductive path.
Although a thick Al wire wire with a diameter of μm can be connected by bonding, it is about 40 μm for connecting the electrode of the small signal portion and the conductive path.
A so-called power mono IC having a power portion and a small signal portion cannot be bonded to an Al wire wire having a small diameter.
Could not be implemented with conventional hybrid integrated circuits.

【0006】この発明は、上述した課題に鑑みてなされ
たものであり、この発明の目的は、パワー回路部とその
パワー回路部を駆動させる小信号系回路とがモノIC化
されたパワー半導体素子を搭載できる混成集積回路を提
供することにある。
The present invention has been made in view of the above problems, and an object of the present invention is a power semiconductor element in which a power circuit section and a small signal system circuit for driving the power circuit section are integrated into a mono IC. It is to provide a hybrid integrated circuit capable of mounting the.

【0007】[0007]

【課題を解決するための手段】上述した課題を解決し、
目的を達成するため、この発明に係わる混成集積回路
は、金属基板の一主面上に絶縁層を介して形成された導
電路上に複数の回路素子が接続され、導電路のアースラ
イン又は電源ラインと金属基板とを電気的に接続し、パ
ワー回路部とそのパワー回路部を駆動させる小信号系回
路部とがモノIC化されたパワー半導体素子が絶縁層を
介えすことなく金属基板上に搭載され、周辺のパッドと
ワイヤ線で接続したことを特徴としている。
[Means for Solving the Problems]
In order to achieve the object, a hybrid integrated circuit according to the present invention has a plurality of circuit elements connected on a conductive path formed on one main surface of a metal substrate via an insulating layer, and a ground line or a power line of the conductive path. And the metal substrate are electrically connected to each other, and the power semiconductor element in which the power circuit portion and the small signal system circuit portion for driving the power circuit portion are integrated into a mono IC is mounted on the metal substrate without an insulating layer. It is characterized in that it is connected to peripheral pads with wire wires.

【0008】また、この発明に係わる混成集積回路は、
金属基板の一主面上に絶縁層を介して形成された導電路
上に複数の回路素子が接続され、導電路のアースライン
又は電源ラインと金属基板とを電気的に接続し、パワー
回路部とそのパワー回路部を駆動させる小信号系回路部
とがモノIC化され且つグランド電位がその基板にある
パワー半導体素子が絶縁層を介えすことなく金属基板上
に搭載され、小信号系回路用の比較的細いワイヤ線とパ
ワー回路部用の比較的太いワイヤ線が周辺のパッドと接
続されたことを特徴としている。
Further, the hybrid integrated circuit according to the present invention is
A plurality of circuit elements are connected on a conductive path formed on one main surface of the metal substrate via an insulating layer, electrically connecting a ground line or a power supply line of the conductive path to the metal substrate, and a power circuit unit. A small signal system circuit part for driving the power circuit part is integrated into a mono IC, and a power semiconductor element having a ground potential on the substrate is mounted on a metal substrate without an insulating layer interposed. It is characterized in that a relatively thin wire line and a relatively thick wire line for the power circuit section are connected to peripheral pads.

【0009】[0009]

【作用】以上のように構成される混成集積回路において
は、従来の構造では実装不可能であった、パワー回路部
とそのパワー回路部を駆動させる小信号系回路とが1チ
ップ化されたパワーモノ型のパワー半導体素子を固着実
装することができる。即ち、細線(約30μ〜40μ)
と太線(約200μ〜300μ)とのボンディングワイ
ヤ接続を必要とするパワーモノ型の半導体素子を固着実
装することができる。
In the hybrid integrated circuit configured as described above, the power in which the power circuit section and the small signal system circuit for driving the power circuit section are integrated into one chip, which cannot be implemented by the conventional structure, is provided. A mono type power semiconductor element can be fixedly mounted. That is, fine wire (about 30μ-40μ)
It is possible to fix and mount a power mono type semiconductor element that requires bonding wire connection between a thick wire (about 200 μ to 300 μ) and a bonding wire.

【0010】また、この様に構成される混成集積回路で
は、金属基板がグランド電位となり、その金属基板上に
直接シリコン基板がグランド電位となっているパワーモ
ノICを固着するためにパワーモノICの誤動作を防止
することができる。
In the hybrid integrated circuit having such a structure, the metal substrate has the ground potential, and the power mono IC having the silicon substrate directly having the ground potential is fixed on the metal substrate. It is possible to prevent malfunction.

【0011】[0011]

【実施例】以下に図1に示した実施例に基づいて本発明
を説明する。図1は本発明の混成集積回路の要部拡大断
面図であり、(1)は混成集積回路基板、(2)は絶縁
樹脂層、(3)は導電路、(5)はパワー半導体素子、
(6)(7)はワイヤ線である。
The present invention will be described below based on the embodiment shown in FIG. FIG. 1 is an enlarged cross-sectional view of a main part of a hybrid integrated circuit according to the present invention, where (1) is a hybrid integrated circuit board, (2) is an insulating resin layer, (3) is a conductive path, and (5) is a power semiconductor element.
(6) and (7) are wire lines.

【0012】金属基板(1)は良熱伝導性に優れたアル
ミニウム基板が用いられ、その表面は周知技術である陽
極酸化法により、酸化アルミニウム膜が形成されてい
る。基板(1)上にはエポキシ樹脂等の絶縁樹脂層
(2)を介して、銅箔あるいは金属メッキ等の手段によ
り所望形状の導電路(3)が形成されている。導電路
(3)上の所定位置には、図示されないがトランジス
タ、チップ抵抗、チップコンデンサー等の複数の回路素
子が固着実装されている。そして、導電路(3)のアー
スライン又は電源は、金属基板(1)特有の浮遊容量に
よる回路誤動作を抑制するために、金属基板(1)とワ
イヤーボンディング等の接続手段(4)により電気接続
され、電位の安定化が保たれている。
As the metal substrate (1), an aluminum substrate excellent in good thermal conductivity is used, and an aluminum oxide film is formed on the surface thereof by the well-known anodic oxidation method. On the substrate (1), a conductive path (3) having a desired shape is formed by means such as copper foil or metal plating via an insulating resin layer (2) such as epoxy resin. Although not shown, a plurality of circuit elements such as transistors, chip resistors, and chip capacitors are fixedly mounted at predetermined positions on the conductive path (3). Then, the ground line or the power source of the conductive path (3) is electrically connected to the metal substrate (1) by connecting means (4) such as wire bonding in order to suppress circuit malfunction due to stray capacitance peculiar to the metal substrate (1). Therefore, the stabilization of the potential is maintained.

【0013】本実施例で使用されるパワー半導体素子
(5)はパワートランジスタの如き、パワー回路のみが
形成されるものではなく、パワー回路部とそのパワー回
路部を駆動させる小信号系回路とがモノIC化(1チッ
プ化)された、例えば高耐圧用MOSFET等のパワー
モノICが使用される。かかる素子(5)を基板(1)
上の導電路(3)と接続する場合二種類のワイヤ線
(6)(7)を必要とする。即ち、パワー回路部領域に
形成された電極は約200μ〜500μ径の比較的太い
Alワイヤ線(6)が用いられて接続され、小信号回路
領域に形成された電極は約20μ〜50μ径の比較的細
いAl等のワイヤ線(7)が用いられて接続される。
The power semiconductor element (5) used in this embodiment is not one in which only a power circuit such as a power transistor is formed, but a power circuit section and a small signal system circuit for driving the power circuit section. A power mono IC that is a mono IC (made into one chip), such as a high breakdown voltage MOSFET, is used. The device (5) is mounted on the substrate (1)
Two types of wire wires (6) and (7) are required when connecting to the upper conductive path (3). That is, the electrodes formed in the power circuit area are connected using a relatively thick Al wire wire (6) having a diameter of about 200 μ to 500 μ, and the electrodes formed in the small signal circuit area have a diameter of about 20 μ to 50 μ. A relatively thin wire wire (7) of Al or the like is used for connection.

【0014】上述したパワー半導体素子(5)はその基
板、即ち、素子(5)のシリコン基板がグランド電位で
あるものが用いられているために、パワー半導体素子
(5)を安定化させるためには素子(5)の基板をグラ
ンド電位とする必要がある。そこで、本発明では絶縁樹
脂層(2)を介すことなく、金属基板(1)上に直接パ
ワー半導体素子(5)を固着実装する。基板(1)の表
面に上述したような酸化アルミニウムがある場合には、
かかる酸化膜をエッチングあるいはドリル等によって除
去して基板(1)の表面を露出させる必要がある。
In order to stabilize the power semiconductor element (5), the above-mentioned power semiconductor element (5) is used because its substrate, that is, the silicon substrate of the element (5) is at the ground potential. Requires the substrate of the element (5) to be at ground potential. Therefore, in the present invention, the power semiconductor element (5) is fixedly mounted directly on the metal substrate (1) without interposing the insulating resin layer (2). When aluminum oxide as described above is present on the surface of the substrate (1),
It is necessary to remove the oxide film by etching, drilling or the like to expose the surface of the substrate (1).

【0015】パワー半導体素子(5)は基板(1)上に
Agペースト等のろう材により固着された後、パワー半
導体素子(5)の周辺に延在形成された固着パッドと上
述した二種類のワイヤ線(6)(7)によって電気的に
接続される。即ち、パワー半導体素子(5)の小信号回
路領域に形成された電極と固着パッドが細いAl線等の
ワイヤ線(7)で接続され、パワー回路領域に形成され
た例えば、ベース、エミッタ電極と他の固着パッドが太
いAl線等のワイヤ線(6)で接続される。
The power semiconductor element (5) is fixed onto the substrate (1) with a brazing material such as Ag paste, and then fixed pads extending around the periphery of the power semiconductor element (5) and the above-described two types of fixing pads. It is electrically connected by wire lines (6) (7). That is, the electrodes formed in the small signal circuit region of the power semiconductor element (5) are connected to the fixing pads by the wire line (7) such as a thin Al wire, and, for example, the base and emitter electrodes formed in the power circuit region are connected. Other fixing pads are connected by wire wires (6) such as thick Al wires.

【0016】かかる、本発明に依れば、集積回路のグラ
ンド電位が金属基板(1)にあるその金属基板(1)上
に直接、グランド電位がシリコン基板にあるパワーモノ
ICを固着実装することにより、パワーモノIC(5)
と基板(1)との表面差が約1μ〜1.5μm程度とな
り、従来実装できなかったパワーモノICを実装するこ
とができる。
According to the present invention, the power mono IC having the ground potential on the silicon substrate is fixedly mounted directly on the metal substrate (1) having the ground potential of the integrated circuit on the metal substrate (1). Power Mono IC (5)
The surface difference between the substrate and the substrate (1) is about 1 μm to 1.5 μm, and it is possible to mount a power mono IC which could not be mounted conventionally.

【0017】また、基板(1)がグランド電位であるた
めにパワーモノIC(5)が誤動作することなく安定化
し、信頼性の優れた混成集積回路を提供することができ
る。
Since the substrate (1) is at the ground potential, the power mono IC (5) is stabilized without malfunction and a highly reliable hybrid integrated circuit can be provided.

【0018】[0018]

【発明の効果】以上に詳述した如く、本発明に依れば、
従来構造では実装困難であったパワー回路部とそのパワ
ー回路部を駆動させる小信号回路とが1チップ化され
た、いわゆるパワーモノICを放熱特性をあまり低下さ
せることなく実装することが可能とできる。
As described in detail above, according to the present invention,
It is possible to mount a so-called power mono IC in which a power circuit section and a small signal circuit for driving the power circuit section, which are difficult to be mounted in the conventional structure, are integrated into one chip without significantly lowering heat dissipation characteristics. .

【0019】また、本発明に依れば、金属基板上に直接
グランド電位が基板にあるパワーモノICを固着実装す
ることにより、パワーモノICの動作を安定化させるこ
とができる。その結果、信頼性の優れた混成集積回路を
提供することができる。
Further, according to the present invention, the operation of the power mono IC can be stabilized by directly fixing and mounting the power mono IC having the ground potential on the substrate on the metal substrate. As a result, a highly reliable hybrid integrated circuit can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す要部拡大断面図である。FIG. 1 is an enlarged sectional view of an essential part showing an embodiment of the present invention.

【図2】従来例を示す断面図である。FIG. 2 is a sectional view showing a conventional example.

【符号の説明】[Explanation of symbols]

(1) 金属基板 (2) 絶縁樹脂層 (3) 導電路 (4) 接続手段 (5) パワー半導体素子 (6)(7) ワイヤ線 (1) Metal substrate (2) Insulating resin layer (3) Conductive path (4) Connecting means (5) Power semiconductor element (6) (7) Wire wire

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H05K 1/05 Z 8727−4E // H05K 1/02 N 7047−4E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H05K 1/05 Z 8727-4E // H05K 1/02 N 7047-4E

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 金属基板の一主面上に絶縁層を介して形
成された導電路上に複数の回路素子が接続され、前記導
電路のアースライン又は電源ラインと前記金属基板とが
電気的に接続された混成集積回路であって、 パワー回路部とそのパワー回路部を駆動させる小信号系
回路部とがモノIC化されたパワー半導体素子が前記絶
縁層を介えすことなく前記金属基板上に搭載され、周辺
のパッドとワイヤ線で接続されたことを特徴とする混成
集積回路。
1. A plurality of circuit elements are connected on a conductive path formed on one main surface of a metal substrate via an insulating layer, and an earth line or a power supply line of the conductive path and the metal substrate are electrically connected to each other. A connected hybrid integrated circuit, wherein a power semiconductor element in which a power circuit section and a small signal system circuit section for driving the power circuit section are integrated into a mono IC is provided on the metal substrate without interposing the insulating layer. A hybrid integrated circuit that is mounted and connected to peripheral pads by wire lines.
【請求項2】 金属基板の一主面上に絶縁層を介して形
成された導電路上に複数の回路素子が接続され、前記導
電路のアースライン又は電源ラインと前記金属基板とが
電気的に接続された混成集積回路であって、 パワー回路部とそのパワー回路部を駆動させる小信号系
回路部とがモノIC化され且つグランド電位がその基板
にあるパワー半導体素子が前記絶縁層を介えすことなく
前記金属基板上に搭載され、小信号系回路用の比較的細
いワイヤ線とパワー回路部用の比較的太いワイヤ線が周
辺のパッドと接続されたことを特徴とする混成集積回
路。
2. A plurality of circuit elements are connected on a conductive path formed on one main surface of a metal substrate via an insulating layer, and an earth line or a power supply line of the conductive path and the metal substrate are electrically connected to each other. In a connected hybrid integrated circuit, a power semiconductor element in which a power circuit section and a small-signal system circuit section for driving the power circuit section are integrated into a mono IC and a ground potential is on the substrate via the insulating layer. A hybrid integrated circuit which is mounted on the metal substrate without being connected, and relatively thin wire lines for a small signal system circuit and relatively thick wire lines for a power circuit unit are connected to peripheral pads.
JP4190706A 1992-07-17 1992-07-17 Hybrid integrated circuit Expired - Fee Related JP2919674B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4190706A JP2919674B2 (en) 1992-07-17 1992-07-17 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4190706A JP2919674B2 (en) 1992-07-17 1992-07-17 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPH0637421A true JPH0637421A (en) 1994-02-10
JP2919674B2 JP2919674B2 (en) 1999-07-12

Family

ID=16262487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4190706A Expired - Fee Related JP2919674B2 (en) 1992-07-17 1992-07-17 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JP2919674B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0052793A1 (en) * 1980-11-24 1982-06-02 E.I. Du Pont De Nemours And Company Oligomer pellets of ethylene terephthalate
JP2001013883A (en) * 1999-06-30 2001-01-19 Fujitsu Ltd Driver ic mounting module and flat plate type display device using the same
JP2007005839A (en) * 2006-10-13 2007-01-11 Mitsubishi Electric Corp Surface mounting package and semiconductor device
WO2009001554A1 (en) * 2007-06-27 2008-12-31 Sanyo Electric Co., Ltd. Circuit device
JP2011193015A (en) * 2006-03-17 2011-09-29 Samsung Electro-Mechanics Co Ltd Anodized metal substrate module
JP2015517226A (en) * 2012-05-04 2015-06-18 アー.ベー.ミクロエレクトロニクゲゼルシャフト ミト ベシュレンクテル ハフツング Circuit board, in particular circuit board for a power module comprising a conductive substrate

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0052793A1 (en) * 1980-11-24 1982-06-02 E.I. Du Pont De Nemours And Company Oligomer pellets of ethylene terephthalate
JP2001013883A (en) * 1999-06-30 2001-01-19 Fujitsu Ltd Driver ic mounting module and flat plate type display device using the same
JP2011193015A (en) * 2006-03-17 2011-09-29 Samsung Electro-Mechanics Co Ltd Anodized metal substrate module
JP2007005839A (en) * 2006-10-13 2007-01-11 Mitsubishi Electric Corp Surface mounting package and semiconductor device
JP4563980B2 (en) * 2006-10-13 2010-10-20 三菱電機株式会社 Surface mount type package and semiconductor device
WO2009001554A1 (en) * 2007-06-27 2008-12-31 Sanyo Electric Co., Ltd. Circuit device
US8363419B2 (en) 2007-06-27 2013-01-29 Sanyo Electric Co., Ltd. Circuit device
JP2015517226A (en) * 2012-05-04 2015-06-18 アー.ベー.ミクロエレクトロニクゲゼルシャフト ミト ベシュレンクテル ハフツング Circuit board, in particular circuit board for a power module comprising a conductive substrate
US9648736B2 (en) 2012-05-04 2017-05-09 A.B. Mikroelektronik Gesellschaft Mit Beschraenkter Haftung Circuit board, particularly for a power-electronic module, comprising an electrically-conductive substrate
US10091874B2 (en) 2012-05-04 2018-10-02 Ab Mikroelektronik Gesellschaft Mit Beschraenkter Haftung Circuit board, particulary for a power-electronic module, comprising an electrically-conductive substrate

Also Published As

Publication number Publication date
JP2919674B2 (en) 1999-07-12

Similar Documents

Publication Publication Date Title
JP4037589B2 (en) Resin-encapsulated power semiconductor device
JP3051011B2 (en) Power module
US6087721A (en) Semiconductor device with a high-frequency bipolar transistor on an insulating substrate
JP2919674B2 (en) Hybrid integrated circuit
JP2735912B2 (en) Inverter device
JP2000031325A (en) Semiconductor power module and inverter device using the same
KR100771262B1 (en) Multi-chip module for use in high-power applications
JP3048707B2 (en) Hybrid integrated circuit
JPH07321160A (en) Semiconductor device
JP3183064B2 (en) Semiconductor device
JP2691352B2 (en) Electronic component mounting device
JP3296626B2 (en) Hybrid integrated circuit device
JP2735920B2 (en) Inverter device
JP3011502B2 (en) Hybrid integrated circuit
JPH05343603A (en) Semiconductor device
JP2583507B2 (en) Semiconductor mounting circuit device
JPH05235567A (en) Hybrid integrated circuit device
JPH06120271A (en) Semiconductor device
JPS60206673A (en) Thermal head
JP2879503B2 (en) Surface mount type electronic circuit device
JPH05144985A (en) Hybrid integrated circuit device
JPH0625978Y2 (en) Semiconductor device
JPH0864719A (en) Hybrid integrated circuit
JPH05315470A (en) Multichip module
JP2880817B2 (en) Semiconductor integrated circuit device

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090423

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090423

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100423

Year of fee payment: 11

LAPS Cancellation because of no payment of annual fees