JPH06120271A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06120271A JPH06120271A JP4266391A JP26639192A JPH06120271A JP H06120271 A JPH06120271 A JP H06120271A JP 4266391 A JP4266391 A JP 4266391A JP 26639192 A JP26639192 A JP 26639192A JP H06120271 A JPH06120271 A JP H06120271A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- insulating film
- semiconductor
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数の半導体素子ある
いは半導体集積回路 (ＩＣ) の半導体基体を同一金属基
板上に搭載した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of semiconductor elements or semiconductor substrates of semiconductor integrated circuits (ICs) mounted on the same metal substrate.
【０００２】[0002]
【従来の技術】パワー用半導体素子と制御用ＩＣを同一
基板上に搭載することにより、回路配線を短くすること
によってパワー用素子のスイッチング応答性を向上させ
たり、過熱保護回路を搭載したＩＣとパワー素子との温
度差を無くして保護協調性を高めることが行われてい
る。金属板は放熱性が良好なため、そのようなパワー用
素子を制御用ＩＣを搭載する基板として適している。金
属基板を使用する場合、各半導体基体の基板側の電極が
同電位の場合は、金属基板を各素子あるいはＩＣの接続
に利用することができるが、その電位が異なる場合に
は、金属基板と半導体基体の間を絶縁する必要が生ず
る。そこで、例えば図２(a) 、(b) に示すように、トラ
ンジスタチップ11ははんだ13により直接、銅フレーム14
に固着するが、ＩＣチップ12は絶縁板15を介してはんだ
13によりフレーム14に搭載する。そして、各チップ11、
12の電極と金属リード16の間、およびトランジスタチッ
プ11のベース電極とＩＣチップの端子電極との間をアル
ミニウム線17を用いて接続し、モールド樹脂18で被覆す
る。図２と共通の部分に同一の符号を付した図３(a) 、
(b)は別の従来例で、基板としてアルミニウム板に直接
あるいはアルマイトを介して絶縁樹脂層で被覆した基板
21を用い、その上に設けた銅箔パターン22の上にトラン
ジスタチップ11がはんだ13により固着された銅フレーム
23をはんだ13により固着し、ＩＣチップ12は別の銅箔パ
ターン22の上にはんだ付けし、銅フレーム24とAl線17に
より接続する。2. Description of the Related Art By mounting a power semiconductor element and a control IC on the same substrate, the switching response of the power element is improved by shortening the circuit wiring, and an IC equipped with an overheat protection circuit. It is performed to eliminate the temperature difference from the power element and improve protection cooperation. Since the metal plate has a good heat dissipation property, such a power element is suitable as a substrate on which a control IC is mounted. When a metal substrate is used, if the electrodes on the substrate side of each semiconductor substrate have the same potential, the metal substrate can be used for connecting each element or IC. It becomes necessary to insulate between the semiconductor substrates. Therefore, for example, as shown in FIGS. 2A and 2B, the transistor chip 11 is directly connected to the copper frame 14 by the solder 13.
, But the IC chip 12 is soldered through the insulating plate 15.
Mounted on frame 14 by 13. And each chip 11,
An aluminum wire 17 is used to connect between the electrodes 12 and the metal leads 16 and between the base electrode of the transistor chip 11 and the terminal electrode of the IC chip, and they are covered with a mold resin 18. 3 (a), in which the same parts as those in FIG.
(b) is another conventional example, which is a substrate coated with an insulating resin layer on an aluminum plate as a substrate directly or through alumite.
21 and a copper frame in which a transistor chip 11 is fixed by solder 13 on a copper foil pattern 22 provided thereon.
23 is fixed by the solder 13, the IC chip 12 is soldered on another copper foil pattern 22, and the copper frame 24 and the Al wire 17 are connected.
【０００３】[0003]
【発明が解決しようとする課題】しかし、図２の場合
は、絶縁板15を用いることによりフレーム14の平面寸法
が大きくなる、組立上の部品点数が多くなり、組立工数
が複雑となって組立コストが高くなるなどの欠点があ
る。また、図３の場合は、基板21表面の絶縁樹脂層の耐
熱温度が115 〜150 ℃と低い、基板21上に外部引出し端
子を有するCuフレーム23を固着するので基板の平面寸法
が大きくなる、あるいは組立工程が複雑になるなどの欠
点があった。However, in the case of FIG. 2, by using the insulating plate 15, the plane size of the frame 14 becomes large, the number of parts for assembling increases, and the number of assembling steps becomes complicated. There are drawbacks such as high cost. In the case of FIG. 3, the heat resistant temperature of the insulating resin layer on the surface of the substrate 21 is as low as 115 to 150 ° C., and since the Cu frame 23 having the external lead terminal is fixed on the substrate 21, the planar dimension of the substrate becomes large. Alternatively, there is a drawback that the assembly process becomes complicated.
【０００４】本発明の目的は、上述の欠点を除き、平面
寸法の小さい基板上に簡単な組立工程で複数の半導体素
子あるいはＩＣを実装できる半導体装置を提供すること
にある。An object of the present invention is to provide a semiconductor device capable of mounting a plurality of semiconductor elements or ICs on a substrate having a small plane size by a simple assembly process, except for the above-mentioned drawbacks.
【０００５】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、同一金属基板上に複数の半導体基体が
搭載される半導体装置において、各半導体基体の基板側
が全面絶縁膜で被覆され、その絶縁膜の少なくとも中央
部がろう付け性良好な表面を有する金属膜で覆われたも
のとする。そして、半導体基体の絶縁膜で被覆される面
の外周部が中央部に比して低くされ、その場合半導体基
体の外周部が階段状に低くされたこと、あるいは傾斜面
によって低くされたことが有効である。また、半導体基
体面を被覆する絶縁膜が酸化シリコンよりなること、そ
の酸化シリコンよりなる絶縁膜を覆う金属膜が絶縁膜側
の第一層がAl膜である多層金属膜であることが有効であ
る。In order to achieve the above object, the present invention is a semiconductor device in which a plurality of semiconductor substrates are mounted on the same metal substrate, and the substrate side of each semiconductor substrate is covered with an entire surface insulating film. It is assumed that at least the central portion of the insulating film is covered with a metal film having a surface with good brazing property. The outer peripheral portion of the surface of the semiconductor substrate covered with the insulating film is made lower than the central portion, and in that case, the outer peripheral portion of the semiconductor substrate is stepwise lowered or lowered by the inclined surface. It is valid. Further, it is effective that the insulating film covering the semiconductor substrate surface is made of silicon oxide, and that the metal film covering the insulating film made of silicon oxide is a multi-layer metal film in which the first layer on the insulating film side is an Al film. is there.
【０００６】[0006]
【作用】半導体基体の支持基板側の面が全面絶縁膜で覆
われていることにより基板の表面の絶縁膜あるいは中間
に挿入する絶縁板が不要になり、かつその絶縁膜の少な
くとも中央部の表面上にろう付け性良好な表面を有する
金属膜があるので、各半導体基体を同一方法で金属基板
上に固着できる。また絶縁膜による絶縁耐圧の不足は、
絶縁膜で被覆される面の外周部を中央部に比して低くし
て金属基板との距離を長くし、沿面耐圧を上げることに
より補われる。Since the entire surface of the semiconductor substrate on the side of the supporting substrate is covered with the insulating film, the insulating film on the surface of the substrate or the insulating plate inserted in the middle is unnecessary, and the surface of at least the central portion of the insulating film is eliminated. Since the metal film having a surface having good brazing property is provided on the upper side, each semiconductor substrate can be fixed on the metal substrate by the same method. Insufficient dielectric strength due to insulation film
This is supplemented by lowering the outer peripheral portion of the surface covered with the insulating film as compared with the central portion to increase the distance to the metal substrate and increasing the creeping breakdown voltage.
【０００７】[0007]
【実施例】図１(a) 、(b) は、図２、図３と同様にパワ
ートランジスタおよび制御用ＩＣを実装した半導体装置
における本発明の一実施例を示し、図２、図３と共通の
部分には同一の符号が付されている。この半導体装置で
は、銅フレーム14の上にトランジスタチップ11および制
御用ＩＣチップ12共に直接はんだ13により固着されてい
る。この場合に用いられているＩＣチップ12のウエーハ
から分割する前の断面を図４(a) 、(b) に示す。図４に
おいて、約500 μｍの厚さのシリコン基板１には鎖線２
で囲んだ領域にＩＣ回路パターンが形成されている。そ
して同図(a)のＸ−Ｘ線断面図である同図(b) に示すよ
うに、裏面側ではチップに分割される各領域の周辺部に
深さ100 〜200 μｍの角形溝３が設けられている。そし
て裏面全面には厚さ１〜２μｍのSiＯ2 からなる絶縁膜
４が形成されている。さらに角形溝３に囲まれた中央部
の絶縁膜４の上にはSiＯ2 に接する側がAl膜、表面側が
NiあるいはAlよりなってはんだ付け性の良い金属膜から
なる多層金属膜５が被着している。このウエーハをダイ
シングにより分割して得られる実線で示したＩＣチップ
は、周辺に沿面絶縁距離を増す階段状の段差を有し、中
央のＩＣ回路パターンの形成された領域２の下に多層金
属膜が形成されており、この膜を利用して図１に示した
ように銅フレーム14にはんだ13によって容易に固着する
ことができる。そしてＩＣ回路で発生した熱はこのはん
だ付け部分を介して銅フレーム14に放熱される。1 (a) and 1 (b) show an embodiment of the present invention in a semiconductor device mounted with a power transistor and a control IC as in FIGS. 2 and 3, and FIG. The common parts are given the same reference numerals. In this semiconductor device, both the transistor chip 11 and the control IC chip 12 are directly fixed to the copper frame 14 by solder 13. The cross section of the IC chip 12 used in this case before being divided from the wafer is shown in FIGS. 4 (a) and 4 (b). In FIG. 4, a chain line 2 is formed on a silicon substrate 1 having a thickness of about 500 μm.
An IC circuit pattern is formed in a region surrounded by. Then, as shown in FIG. 7B, which is a cross-sectional view taken along line XX of FIG. 1A, a rectangular groove 3 having a depth of 100 to 200 μm is formed in the peripheral portion of each region divided into chips on the back surface side. It is provided. An insulating film 4 made of SiO 2 having a thickness of 1 to 2 μm is formed on the entire back surface. Further, on the central insulating film 4 surrounded by the rectangular groove 3, the side in contact with SiO 2 is the Al film, and the surface side is
A multi-layer metal film 5 consisting of a metal film made of Ni or Al and having good solderability is deposited. An IC chip shown by a solid line obtained by dividing this wafer by dicing has a step-like step around the periphery to increase the creepage insulation distance, and a multi-layer metal film under the region 2 where the central IC circuit pattern is formed. Is formed and can be easily fixed to the copper frame 14 by the solder 13 as shown in FIG. 1 using this film. Then, the heat generated in the IC circuit is radiated to the copper frame 14 via the soldered portion.
【０００８】図５に示した実施例では、チップに分割さ
れる各領域の周辺部に三角溝６が掘られており、分割し
て得られるチップ裏面の周辺部には傾斜面が生ずる。こ
れによってもチップと銅フレームとの間の沿面絶縁距離
を増加させることができる。しかし、絶縁耐圧が絶縁膜
４のみで十分のときは、図１のチップ11に示したように
周辺部に段差あるいは傾斜面のない平坦な裏面のままに
しておいてもよい。その場合は、多層金属膜５は裏面全
面に形成される。いずれの場合も、絶縁膜４がSiＯ2 よ
りなるので、表面絶縁基板を用いる場合に比して耐熱性
が大幅に改善される。In the embodiment shown in FIG. 5, triangular grooves 6 are dug in the peripheral portion of each area divided into chips, and an inclined surface is formed in the peripheral portion of the chip back surface obtained by the division. This can also increase the creepage insulation distance between the chip and the copper frame. However, when the withstand voltage is sufficient with only the insulating film 4, it may be left as a flat back surface having no step or inclined surface in the peripheral portion as shown in the chip 11 of FIG. In that case, the multilayer metal film 5 is formed on the entire back surface. In any case, since the insulating film 4 is made of SiO 2 , the heat resistance is greatly improved as compared with the case where the surface insulating substrate is used.
【０００９】[0009]
【発明の効果】本発明によれば、半導体素子あるいはＩ
Ｃの半導体基体の裏面全面を絶縁膜で被覆することによ
り、金属基板に搭載する際に絶縁板をはさむことも、あ
るいは表面に絶縁膜を有する金属基板を用いることな
く、さらにその絶縁膜の上にろう付け可能な表面を有す
る金属膜を被着することにより、搭載面の電位が異なる
複数の半導体基体をろう付けにより容易に放熱性良好な
金属基板に容易に実装することができる。従って、でき
上がった半導体装置の小形化、組立工程の簡単化が達成
できる。According to the present invention, a semiconductor device or I
By covering the entire back surface of the semiconductor substrate of C with an insulating film, the insulating plate is not sandwiched when the semiconductor substrate is mounted on the metal substrate, or a metal substrate having an insulating film on the surface is not used. By depositing a metal film having a brazable surface on the semiconductor substrate, a plurality of semiconductor substrates having different mounting surface potentials can be easily mounted on a metal substrate having a good heat dissipation property by brazing. Therefore, the miniaturization of the completed semiconductor device and the simplification of the assembling process can be achieved.
【図１】本発明の一実施例の半導体装置を示し、(a) が
透視平面図、(b) が透視側面図FIG. 1 shows a semiconductor device according to an embodiment of the present invention, in which (a) is a perspective plan view and (b) is a perspective side view.
【図２】従来の半導体装置の一例を示し、(a) が透視平
面図、(b) が透視側面図FIG. 2 shows an example of a conventional semiconductor device, in which (a) is a perspective plan view and (b) is a perspective side view.
【図３】従来の半導体装置の別の例を示し、(a) が透視
平面図、(b) が透視側面図3A and 3B show another example of a conventional semiconductor device, in which FIG. 3A is a perspective plan view and FIG. 3B is a perspective side view.
【図４】本発明の一実施例に用いるＩＣの半導体基体を
示し、(a) が平面図、(b) が(a) のＸ−Ｘ線断面図FIG. 4 shows a semiconductor substrate of an IC used in one embodiment of the present invention, (a) is a plan view, and (b) is a sectional view taken along line XX of (a).
【図５】本発明の別の実施例に用いるＩＣの半導体基体
の断面図FIG. 5 is a sectional view of a semiconductor substrate of an IC used in another embodiment of the present invention.
１ シリコン基板 ２ ＩＣ回路パターン部 ３ 角形溝 ４ 絶縁膜 ５ 多層金属膜 ６ 三角溝 １１ トランジスタチップ １２ トランジスタチップ １３ はんだ １４ 金属フレーム 1 Silicon Substrate 2 IC Circuit Pattern Section 3 Square Groove 4 Insulating Film 5 Multilayer Metal Film 6 Triangular Groove 11 Transistor Chip 12 Transistor Chip 13 Solder 14 Metal Frame
Claims (6)
されるものにおいて、各半導体基体の基板側が全面絶縁
膜で被覆され、その絶縁膜の少なくとも中央部がろう付
け性良好な表面を有する金属膜で覆われたことを特徴と
する半導体装置。1. In a plurality of semiconductor substrates mounted on the same metal substrate, the substrate side of each semiconductor substrate is entirely covered with an insulating film, and at least the central portion of the insulating film has a surface having a good brazing property. A semiconductor device characterized by being covered with a metal film.
部が中央部に比して低くされた請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the outer peripheral portion of the surface of the semiconductor substrate covered with the insulating film is made lower than the central portion.
請求項２記載の半導体装置。3. The semiconductor device according to claim 2, wherein the outer peripheral portion of the semiconductor substrate is stepwise lowered.
された請求項２記載の半導体装置。4. The semiconductor device according to claim 2, wherein the outer peripheral portion of the semiconductor substrate is lowered by the inclined surface.
コンよりなる請求項１ないし４のいずれかに記載の半導
体装置。5. The semiconductor device according to claim 1, wherein the insulating film covering the surface of the semiconductor substrate is made of silicon oxide.
なる絶縁膜を覆う金属膜が絶縁膜側の第一層がアルミニ
ウム膜である多層金属膜である請求項５記載の半導体装
置。6. The semiconductor device according to claim 5, wherein the metal film covering the insulating film made of silicon oxide covering the surface of the semiconductor substrate is a multi-layer metal film in which the first layer on the insulating film side is an aluminum film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4266391A JP3036256B2 (en) | 1992-10-06 | 1992-10-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4266391A JP3036256B2 (en) | 1992-10-06 | 1992-10-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06120271A true JPH06120271A (en) | 1994-04-28 |
| JP3036256B2 JP3036256B2 (en) | 2000-04-24 |
Family
ID=17430287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4266391A Expired - Fee Related JP3036256B2 (en) | 1992-10-06 | 1992-10-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3036256B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239381B1 (en) | 1996-04-18 | 2001-05-29 | Kabushiki Kaisha Eastern | Circuit board for a semiconductor device and method of making the same |
| JP2008041885A (en) * | 2006-08-04 | 2008-02-21 | Torex Semiconductor Ltd | Semiconductor device and method for manufacturing insulating layer |
| JP2009267071A (en) * | 2008-04-25 | 2009-11-12 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2009272413A (en) * | 2008-05-06 | 2009-11-19 | Anden | Semiconductor device for load driving |
-
1992
- 1992-10-06 JP JP4266391A patent/JP3036256B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239381B1 (en) | 1996-04-18 | 2001-05-29 | Kabushiki Kaisha Eastern | Circuit board for a semiconductor device and method of making the same |
| JP2008041885A (en) * | 2006-08-04 | 2008-02-21 | Torex Semiconductor Ltd | Semiconductor device and method for manufacturing insulating layer |
| JP2009267071A (en) * | 2008-04-25 | 2009-11-12 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2009272413A (en) * | 2008-05-06 | 2009-11-19 | Anden | Semiconductor device for load driving |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3036256B2 (en) | 2000-04-24 |
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| LAPS | Cancellation because of no payment of annual fees |