JP2848068B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2848068B2 JP2848068B2 JP32487491A JP32487491A JP2848068B2 JP 2848068 B2 JP2848068 B2 JP 2848068B2 JP 32487491 A JP32487491 A JP 32487491A JP 32487491 A JP32487491 A JP 32487491A JP 2848068 B2 JP2848068 B2 JP 2848068B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- insulating substrate
- semiconductor device
- control circuit
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はパワートランジスタモジ
ュールなどを対象とした半導体装置の構成に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device for a power transistor module or the like.
【0002】[0002]
【従来の技術】半導体装置の回路基板として、昨今では
製品コスト,加工性,量産性,放熱性などの面から、金
属絶縁基板を採用する例が普及する傾向にある。次に、
パワートランジスタモジュールを例に、金属絶縁基板を
採用した半導体装置の従来構造を図3に示す。図におい
て、1は金属ベース1a,良伝熱性の絶縁層1b,金属
箔1cを一体化し、かつ金属箔1cに回路パターンを形
成した金属絶縁基板、2はパワートランジスタ(ベアチ
ップ)、3は制御回路用の各種部品、4は外部導出端
子、5は樹脂ケースである。ここで、パワートランジス
タ2は放熱用金属板6を介して金属絶縁基板1の金属箔
1cにマウントされ、他の部品3,外部導出端子4はそ
れぞれ金属絶縁基板1の回路パターンに振り分け実装し
て半田接合されており、かつパワートランジスタ2との
間がワイヤ7を介して内部接続(ワイヤボンディング)
されている。なお、ベアチップのパワートランジスタ2
はケース5の内部にゲル状充填材を充填するか、あるい
はチップに封止樹脂を,コーティング,ポッティングす
るなどして樹脂封止される。2. Description of the Related Art In recent years, as a circuit board of a semiconductor device, an example in which a metal insulating substrate is adopted tends to be widespread in terms of product cost, workability, mass productivity, heat dissipation, and the like. next,
FIG. 3 shows a conventional structure of a semiconductor device employing a metal insulating substrate, taking a power transistor module as an example. In the figure, reference numeral 1 denotes a metal insulating substrate in which a metal base 1a, an insulating layer 1b having good heat conductivity, and a metal foil 1c are integrated and a circuit pattern is formed on the metal foil 1c, 2 denotes a power transistor (bare chip), and 3 denotes a control circuit. And 4 are external lead-out terminals and 5 is a resin case. Here, the power transistor 2 is mounted on the metal foil 1c of the metal insulating substrate 1 via the metal plate 6 for heat dissipation, and the other components 3 and the external lead terminals 4 are distributed and mounted on the circuit pattern of the metal insulating substrate 1, respectively. Internal connection (wire bonding) between the power transistor 2 and the power transistor 2 via a wire 7
Have been. The bare chip power transistor 2
Is filled with a gel filler inside the case 5, or the chip is sealed with resin by coating, potting, or the like with a sealing resin.
【0003】[0003]
【発明が解決しようとする課題】ところで、前記したパ
ワートランジスタモジュールなどの電力用半導体装置
は、その容量がますます増加する傾向にある一方で、半
導体装置を小形化することが設計上での大きな課題とな
っている。かかる点、図3のように全ての回路部品を一
枚の金属絶縁基板上に直接実装した構造では、次のよう
な理由で装置の小形化には限界がある。By the way, the power semiconductor devices such as the power transistor module described above tend to have an increasing capacity, while miniaturization of the semiconductor device is a major design problem. It has become a challenge. In this regard, in the structure in which all the circuit components are directly mounted on one metal insulating substrate as shown in FIG. 3, there is a limit to downsizing of the device for the following reasons.
【0004】(1)金属絶縁基板1の金属箔1cをパタ
ーンニングして導体パターンを形成したものでは、互い
に分離した導体パターンの相互間に印加電圧に見合った
絶縁沿面距離を確保する必要がある。特に主回路と制御
回路との間には使用時に大きな電圧差が加わることか
ら、パワートランジスタ2をマウントした導体パターン
と制御回路のチップ部品3を実装した導体パターンとの
間には大きな沿面距離が必要となり、この結果として金
属絶縁基板の所要面積がそれだけ増大して装置全体が大
形化する。(1) In the case where a conductor pattern is formed by patterning the metal foil 1c of the metal insulating substrate 1, it is necessary to secure an insulation creepage distance commensurate with the applied voltage between the conductor patterns separated from each other. . In particular, since a large voltage difference is applied between the main circuit and the control circuit during use, a large creepage distance exists between the conductor pattern on which the power transistor 2 is mounted and the conductor pattern on which the chip component 3 of the control circuit is mounted. This necessitates the required area of the metal insulating substrate to be increased, and the overall size of the device is increased.
【0005】(2)また、パワートランジスタ2の通電
に伴う発熱は金属板6,金属絶縁基板1を伝熱してヒー
トシンクに放熱されるわけであるが、前記のように金属
絶縁基板1の金属箔1cをパターンニングしてそのパタ
ーンの一部に実装した構造では、パワートランジスタ2
から金属絶縁基板1の金属ベース1aに至る伝熱路が狭
い範囲に制限されるため十分な放熱性が得られない。そ
こで十分な放熱性を確保するには、金属絶縁基板として
大面積のものを使用することが必要になる。(2) The heat generated by the power transistor 2 being energized is transmitted to the metal plate 6 and the metal insulating substrate 1 and is radiated to the heat sink. 1c is patterned and mounted on a part of the pattern.
Since the heat transfer path from the substrate to the metal base 1a of the metal insulating substrate 1 is limited to a narrow range, sufficient heat dissipation cannot be obtained. Therefore, in order to secure sufficient heat dissipation, it is necessary to use a metal insulating substrate having a large area.
【0006】(3)さらに、同じ金属絶縁基板に主回路
部品,制御回路部品などを並べて実装した構造では、特
に制御回路に対するノイズ耐量が低下する。すなわち、
主回路にパルス状ノイズが侵入すると、金属絶縁基板1
の絶縁層(誘電体)1b,金属箔1cの導体パターンを
経由して制御回路部品にノイズ電流が流れる。しかも絶
縁層1bは伝熱性を考慮して極薄いのでノイズ電流が大
きくなり、半導体装置が誤動作するおそれがある。(3) Further, in a structure in which main circuit components, control circuit components, and the like are mounted side by side on the same metal insulating substrate, noise immunity to a control circuit in particular is reduced. That is,
When pulsed noise enters the main circuit, the metal insulating substrate 1
The noise current flows to the control circuit component via the conductor pattern of the insulating layer (dielectric) 1b and the metal foil 1c. In addition, since the insulating layer 1b is extremely thin in consideration of heat conductivity, the noise current increases, and the semiconductor device may malfunction.
【0007】本発明は上記の点にかんがみなされたもの
であり、その目的は電力用半導体装置を対象に、高い放
熱性,ノイズ耐量を確保しつつ、金属絶縁基板の所要面
積を縮減して装置全体の小形化が図れるように構成した
半導体装置を提供することにある。The present invention has been made in view of the above points, and has as its object to reduce the required area of a metal insulating substrate for a power semiconductor device while ensuring high heat dissipation and noise immunity. An object of the present invention is to provide a semiconductor device configured so that the entire device can be reduced in size.
【0008】[0008]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置は、外囲器である樹脂ケース内
の中段位置に半導体チップの実装域を欠如して金属絶縁
基板の上面域を覆う中仕切壁を設け、該中仕切壁の上面
側に外部導出端子, 制御回路部品およびその配線導体を
配置して構成するものとする。In order to achieve the above object, a semiconductor device according to the present invention is characterized in that a semiconductor chip mounting area is not provided at a middle position in a resin case, which is an envelope, so that a top surface of a metal insulating substrate is not provided. A partition wall that covers the area is provided, and external lead-out terminals, control circuit components, and their wiring conductors are arranged on the upper surface side of the partition wall.
【0009】また、前記構成の実施態様として、次のよ
うな構成がある。 (1)外部導出端子, 制御回路部品の配線導体をあらか
じめケースの中仕切壁にインサートして一体成形する。 (2)金属絶縁基板の全面域に金属箔を被着させたま
ま、この上に放熱用金属板を介して半導体チップをマウ
ントする。さらに、前記の放熱用金属板は金属絶縁基板
の金属箔の略全面域を覆って伝熱的に接合する。Further, as an embodiment of the above configuration, there is the following configuration. (1) The external lead-out terminal and the wiring conductor of the control circuit component are inserted into the partition wall of the case in advance and integrally molded. (2) A semiconductor chip is mounted on a metal insulating substrate via a metal plate for heat radiation while a metal foil is adhered over the entire surface of the metal insulating substrate. Further, the heat-dissipating metal plate covers substantially the entire area of the metal foil of the metal insulating substrate and is thermally conductively bonded.
【0010】[0010]
【作用】上記の構成によれば、金属絶縁基板には半導体
チップ(パワーチップ)のみがマウントされ、他の制御
回路部品およびその配線導体,外部導出端子などは全て
金属絶縁基板と隔離し、樹脂ケースの中仕切壁にインサ
ートするなどして配備されている。これにより、まず、
主回路部品である半導体チップと他の回路部品との間の
絶縁耐量はケースの中仕切壁により十分に確保されるの
で、金属絶縁基板上で必要な絶縁沿面距離を確保するな
どの必要がなく、装置全体としての実装密度を高められ
る。また、半導体チップ(パワーチップ)の通電に伴う
発生熱は他の実装部品の配置に阻害されることなく、放
熱用金属板を通じて熱流束が金属絶縁基板の全面域に拡
散して伝熱するので高い放熱性が確保される。加えて、
制御回路のチップ部品などは主回路部品である半導体チ
ップとケースの中仕切壁を隔てて隔離されているので金
属絶縁基板に全ての部品を実装した構成のものと比べて
外来ノイズに対する高い耐量が確保できる。According to the above construction, only the semiconductor chip (power chip) is mounted on the metal insulating substrate, and all other control circuit components, their wiring conductors, and external lead terminals are isolated from the metal insulating substrate. It is installed by inserting it into the partition wall of the case. With this, first,
The dielectric strength between the semiconductor chip, which is the main circuit component, and other circuit components is sufficiently ensured by the partition wall of the case, so there is no need to secure the required insulation creepage distance on the metal insulating substrate. Thus, the mounting density of the entire device can be increased. In addition, the heat generated by energization of the semiconductor chip (power chip) is not disturbed by the arrangement of other mounting components, and the heat flux is diffused to the entire surface of the metal insulating substrate through the heat-dissipating metal plate to conduct heat. High heat dissipation is ensured. in addition,
The control circuit chip components are separated from the main circuit components by the semiconductor chip and the case partition walls. Can be secured.
【0011】[0011]
【実施例】以下本発明の実施例を図面に基づいて説明す
る。なお、図中で図3に対応する同一部材には同じ符号
が付してある。 実施例1:図1において、まず樹脂ケース5に組み込ん
だ金属絶縁基板1は、絶縁層1bの全面に金属箔1cが
形成されたままで、パターンニングされてない状態(通
称「べた」パターン状態と言う)のものが使用され、こ
の金属絶縁基板1の所定位置にパワートランジスタ2が
放熱用金属板(例えば銅板)6を介してマウントされて
いる。一方、樹脂ケース5の内部の中段位置にはパワー
トランジスタ2の実装域を欠如して金属絶縁基板1の上
面域を覆うように中仕切壁5aを備えており、この中仕
切壁5aの上面側に制御回路部品3を接続する配線導体
8および外部導出端子4が設置され、かつ制御回路部品
3が配線導体8の上に半田付けされている。なお、外部
導出端子4,配線導体8はケース5をモールド成形する
際にインサートして一体形成するものとする。Embodiments of the present invention will be described below with reference to the drawings. In the figure, the same members corresponding to FIG. 3 are denoted by the same reference numerals. Example 1 In FIG. 1, the metal insulating substrate 1 incorporated in the resin case 5 is unpatterned with the metal foil 1c formed on the entire surface of the insulating layer 1b (commonly referred to as a “solid” pattern state). The power transistor 2 is mounted at a predetermined position of the metal insulating substrate 1 via a heat-dissipating metal plate (for example, a copper plate) 6. On the other hand, a middle partition wall 5a is provided at a middle position inside the resin case 5 so as to cover the upper surface area of the metal insulating substrate 1 without the mounting area of the power transistor 2, and the upper surface side of the middle partition wall 5a. A wiring conductor 8 for connecting the control circuit component 3 and an external lead-out terminal 4 are provided, and the control circuit component 3 is soldered on the wiring conductor 8. The external lead-out terminals 4 and the wiring conductors 8 are integrally formed by inserting them when the case 5 is molded.
【0012】かかる構成によれば、主回路,制御回路部
品の相互間に必要な絶縁耐量はケース5の中仕切壁5a
自身で確保されるので、それだけ高実装密度が可能とな
る。また、パワートランジスタ2での通電に伴う発生熱
は他の部品に邪魔されることなく、金属板6を通じて熱
流束が金属絶縁基板1の全面域に拡散するように伝熱
し、その金属ベース1aより外部のヒートシンクなどに
放熱する。したがって、小面積の金属絶縁基板でも大電
力容量のパワートランジスタ2に対する高い放熱性を確
保しつつ、しかも装置全体をより小形に構成できる。な
お、制御回路部品3などの通電に伴う発生熱は極僅かで
あり、ケース5の中仕切壁5aに設置しても実用面で何
等支障はない。また、制御回路部品3などはパワートラ
ンジスタ2,金属絶縁基板1と隔離して中仕切板5aに
配置されているので、図3の構成と比べて外来ノイズに
対し高いノイズ耐量が得られる。According to such a configuration, the insulation withstand required between the main circuit and the control circuit components is determined by the partition wall 5 a of the case 5.
Since it is secured by itself, a higher mounting density is possible. Further, the heat generated by energization in the power transistor 2 is transmitted through the metal plate 6 such that the heat flux is diffused to the entire surface of the metal insulating substrate 1 without being disturbed by other components, and is transmitted from the metal base 1a. Dissipates heat to an external heat sink. Therefore, even if the metal insulating substrate has a small area, high heat dissipation to the power transistor 2 having a large power capacity can be ensured, and the entire device can be made smaller. In addition, the heat generated by energization of the control circuit component 3 and the like is very small, and there is no problem in practical use even if the heat is installed on the partition wall 5a of the case 5. Further, since the control circuit components 3 and the like are arranged on the intermediate partition plate 5a separately from the power transistor 2 and the metal insulating substrate 1, higher noise immunity to external noise can be obtained as compared with the configuration of FIG.
【0013】実施例2:図2は先記した実施例1をさら
に発展させて放熱性を高めるようにしたものであり、放
熱用金属板6として金属絶縁基板1の金属箔1cの略全
面域を覆うような大面積の金属板が組み込まれ、その全
面が金属絶縁基板の金属箔1cと伝熱的に接合されてい
る。かかる構成により、通電に伴うパワートランジスタ
2の発生熱は大面積の放熱用金属板6に拡散して金属絶
縁基板1に伝熱するので、それだけ放熱経路の熱抵抗が
低くより高い放熱性が得られるようになる。Second Embodiment FIG. 2 shows a further development of the first embodiment described above in which the heat radiation is enhanced. The heat radiation metal plate 6 has a substantially entire area of the metal foil 1c of the metal insulating substrate 1. A metal plate having a large area covering the metal foil is incorporated, and the entire surface is thermally conductively bonded to the metal foil 1c of the metal insulating substrate. With this configuration, the heat generated by the power transistor 2 due to energization is diffused to the large-area metal plate 6 for heat dissipation and is transferred to the metal insulating substrate 1, so that the heat resistance of the heat dissipation path is low and higher heat dissipation is obtained. Will be able to
【0014】[0014]
【発明の効果】以上述べたように、本発明による半導体
装置の構成によれば、パワートランジスタモジュールな
どの電力用半導体装置を対象に、高い絶縁耐量,ノイズ
耐量を確保しつつ、高実装密度化とともに金属絶縁基板
の所要面積を縮減して装置全体の小形化を図ることがで
きる。As described above, according to the configuration of the semiconductor device according to the present invention, a high packaging density can be achieved for a power semiconductor device such as a power transistor module while ensuring a high insulation resistance and a noise resistance. At the same time, the required area of the metal insulating substrate can be reduced, and the size of the entire device can be reduced.
【図1】本発明の実施例1に対応する半導体装置の構成
断面図FIG. 1 is a configuration sectional view of a semiconductor device according to a first embodiment of the present invention;
【図2】本発明の実施例2に対応する半導体装置の構成
断面図FIG. 2 is a configuration sectional view of a semiconductor device according to a second embodiment of the present invention;
【図3】パワートランジスタモジュールを対象とした従
来における半導体装置の構成断面図FIG. 3 is a configuration sectional view of a conventional semiconductor device for a power transistor module.
1 金属絶縁基板 1a 金属ベース 1b 絶縁層 1c 金属箔 2 パワートランジスタ(半導体チップ) 3 制御回路部品 4 外部導出端子 5 樹脂ケース 5a 中仕切壁 6 放熱用金属板 7 ボンディングワイヤ 8 配線導体 REFERENCE SIGNS LIST 1 metal insulating substrate 1 a metal base 1 b insulating layer 1 c metal foil 2 power transistor (semiconductor chip) 3 control circuit component 4 external lead-out terminal 5 resin case 5 a partition wall 6 heat-dissipating metal plate 7 bonding wire 8 wiring conductor
Claims (4)
板にマウントした半導体チップ, 制御回路部品, および
外部導出端子を組み込み、半導体チップと制御回路部
品, 外部導出端子との間をワイヤボンディングして内部
接続した半導体装置において、前記ケース内の中段位置
に半導体チップの実装域を欠如して金属絶縁基板の上面
域を覆う中仕切壁を設け、該中仕切壁の上面側に外部導
出端子,制御回路部品,およびその配線導体を配置した
ことを特徴とする半導体装置。A metal case is mounted on a resin case, a semiconductor chip mounted on the metal insulating substrate, a control circuit component, and an external lead-out terminal, and wire bonding is performed between the semiconductor chip and the control circuit component and the external lead-out terminal. In the semiconductor device connected internally, a partition wall that covers the upper surface area of the metal insulating substrate without the mounting area of the semiconductor chip is provided at a middle position in the case, and an external lead terminal is provided on the upper surface side of the partition wall. A semiconductor device comprising a control circuit component and a wiring conductor thereof.
導出端子, 制御回路部品の配線導体をケースの中仕切壁
にインサートして一体成形したことを特徴とする半導体
装置。2. The semiconductor device according to claim 1, wherein the external lead-out terminal and the wiring conductor of the control circuit component are inserted into a partition wall of the case and are integrally formed.
絶縁基板の全面域に金属箔を被着させたまま、この上に
放熱用金属板を介して半導体チップをマウントしたこと
を特徴とする半導体装置。3. A semiconductor device according to claim 1, wherein a semiconductor chip is mounted on a metal insulating substrate via a heat-dissipating metal plate while a metal foil is adhered over the entire surface of the metal insulating substrate. Semiconductor device.
用金属板が金属絶縁基板の金属箔の略全面域を覆って伝
熱的に接合されていることを特徴とする半導体装置。4. The semiconductor device according to claim 3, wherein the heat-dissipating metal plate covers substantially the entire surface of the metal foil of the metal insulating substrate and is thermally conductively bonded.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32487491A JP2848068B2 (en) | 1991-12-10 | 1991-12-10 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32487491A JP2848068B2 (en) | 1991-12-10 | 1991-12-10 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05304248A JPH05304248A (en) | 1993-11-16 |
JP2848068B2 true JP2848068B2 (en) | 1999-01-20 |
Family
ID=18170604
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32487491A Expired - Fee Related JP2848068B2 (en) | 1991-12-10 | 1991-12-10 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2848068B2 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4418426B4 (en) * | 1993-09-08 | 2007-08-02 | Mitsubishi Denki K.K. | Semiconductor power module and method of manufacturing the semiconductor power module |
JP3316714B2 (en) * | 1994-05-31 | 2002-08-19 | 三菱電機株式会社 | Semiconductor device |
DE19726534A1 (en) * | 1997-06-23 | 1998-12-24 | Asea Brown Boveri | Power semiconductor module with closed submodules |
US6147869A (en) * | 1997-11-24 | 2000-11-14 | International Rectifier Corp. | Adaptable planar module |
DE19808986A1 (en) * | 1998-03-03 | 1999-09-09 | Siemens Ag | Semiconductor component with several semiconductor chips |
US6166464A (en) * | 1998-08-24 | 2000-12-26 | International Rectifier Corp. | Power module |
JP4527292B2 (en) * | 2001-01-04 | 2010-08-18 | 三菱電機株式会社 | Semiconductor power module |
JP2006179856A (en) * | 2004-11-25 | 2006-07-06 | Fuji Electric Holdings Co Ltd | Insulating substrate and semiconductor device |
JP2007329387A (en) * | 2006-06-09 | 2007-12-20 | Mitsubishi Electric Corp | Semiconductor device |
CN104160502A (en) | 2012-03-09 | 2014-11-19 | 三菱电机株式会社 | Semiconductor module |
JP2013258321A (en) | 2012-06-13 | 2013-12-26 | Fuji Electric Co Ltd | Semiconductor device |
DE112013007390B4 (en) | 2013-08-29 | 2020-06-25 | Mitsubishi Electric Corporation | Semiconductor module, semiconductor device and vehicle |
JP6323325B2 (en) | 2014-04-21 | 2018-05-16 | 三菱電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
JP2015173299A (en) * | 2015-07-06 | 2015-10-01 | 三菱電機株式会社 | semiconductor module |
CN116435264B (en) * | 2023-06-12 | 2023-10-27 | 江苏宏微科技股份有限公司 | Power semiconductor module |
-
1991
- 1991-12-10 JP JP32487491A patent/JP2848068B2/en not_active Expired - Fee Related
Also Published As
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---|---|
JPH05304248A (en) | 1993-11-16 |
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