JPH05114776A - Bare chip lsi mounting structure - Google Patents

Bare chip lsi mounting structure

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Publication number
JPH05114776A
JPH05114776A JP3266596A JP26659691A JPH05114776A JP H05114776 A JPH05114776 A JP H05114776A JP 3266596 A JP3266596 A JP 3266596A JP 26659691 A JP26659691 A JP 26659691A JP H05114776 A JPH05114776 A JP H05114776A
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JP
Japan
Prior art keywords
bare chip
circuit
conductor
surface
chip lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3266596A
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Japanese (ja)
Other versions
JP2973646B2 (en
Inventor
Yasuhide Kuroda
Hiroyuki Takabayashi
Kenichiro Tsubone
健一郎 坪根
博幸 高林
康秀 黒田
Original Assignee
Fujitsu Ltd
富士通株式会社
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Application filed by Fujitsu Ltd, 富士通株式会社 filed Critical Fujitsu Ltd
Priority to JP3266596A priority Critical patent/JP2973646B2/en
Publication of JPH05114776A publication Critical patent/JPH05114776A/en
Application granted granted Critical
Publication of JP2973646B2 publication Critical patent/JP2973646B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. IMC (insert mounted components)

Abstract

PURPOSE: To provide a bare chip LSI mounting structure where a bare chip LSI is directly mounted on a multilayered circuit board as sealed and which is lessened in size and enhanced in mounting density, heat dissipating property, and EMI countermeasure.
CONSTITUTION: The mount of a multilayered circuit board 1 where a bare chip LSI 9 is mounted is formed into a stepped recess 2, an inner plane spreading wide is provided to the base of the recess, an inner conductor 3 where the LSI 9 is die-bonded is exposed, circuit terminals 4 connected to the bare chip LSI 9 are provided to steps 21 at opposed positions through an inner conductor. A ring-shaped conductor pattern 11 connected to a ground circuit is provided to the surface edge of the stepped recess 2, the stepped recess 2 is covered with a cap 5 provided with a full conductor plane 51 formed on one side and an insulated circuit pattern 52 formed on the other side, the inside of the stepped recess 2 is sealed up by bringing the full conductor plane 51 into close contact with the conductor pattern 11, and the circuit pattern 52 is connected to the surface circuit pattern 12 of the circuit board 1.
COPYRIGHT: (C)1993,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は直接ベアチップLSIを多層構成の回路基板に密封実装するベアチップLSIの実装構造に関する。 The present invention relates to a mounting structure of the bare chip LSI to seal directly mounted bare chip LSI on the circuit board having a multilayer structure.

【0002】最近、LSI(Large Scale Integratedci [0002] In recent years, LSI (Large Scale Integratedci
rcuit) の高速化、高発熱化に対応した高密度実装構造(回路基板技術、封止技術、放熱技術の合成による)の検討が進められており、簡単な構造で要求特性を満足し、コストパフォーマンスに優れたベアチップLSIの実装技術を開発することが要望されている。 Faster Rcuit), high-density packaging structure (circuit board technology for high heat generation, and studied advanced sealing techniques, by synthesis radiator technology), satisfy the required characteristics with a simple structure, cost it has been desired to develop an implementation technology of excellent bare chip LSI performance.

【0003】 [0003]

【従来の技術】図2に従来例のベアチップLSIの実装構造を示し、(a) は樹脂封止、(b) はキャップ封止である。 BACKGROUND OF THE INVENTION show a mounting structure of the bare chip LSI of the conventional example in FIG. 2 is a (a) a resin sealing, (b) the cap seal.

【0004】図2の(a) に示す樹脂封止は、一般的なC [0004] resin sealing shown in FIG. 2 (a), the general C
OB (Chip on Board)実装であり、ベアチップLSI9 OB (Chip on Board) is an implementation, bare chip LSI9
を回路基板15の表面に固着させ、表面回路パターン12に接続端子をワイヤボンディングして接続してから、電気的絶縁性の封止用の樹脂99を盛り上げてベアチップLS Was adhered to the surface of the circuit board 15, bare chip connection terminal after connecting by wire bonding to the surface circuit pattern 12, boost the resin 99 for sealing the electrical insulating LS
I9を完全に埋没させて封止して実装する、極めて簡単なものである。 I9 to completely bury implemented sealed is extremely simple.

【0005】図2の(b) のキャップ封止は、回路モジュールの薄型化に対応した実装例であり、回路基板15に段付凹部25を設け、底部にベアチップLSI9を固着させ、段部26に配設した回路端子とワイヤボンディングした後に、段付凹部15の開口にキャップ55を覆い、密着接着して内部を封止して実装する。 [0005] Cap Sealing of (b) in FIG. 2 is an implementation that corresponds to the thickness of the circuit module, provided with the circuit board 15 with bunk recess 25, thereby fixing the bare chip LSI9 the bottom, the step portion 26 after the circuit terminals and the wire bonding which is disposed to cover the cap 55 to the opening of the stepped recess 15 is mounted to seal the interior in close contact adhesion.

【0006】 [0006]

【発明が解決しようとする課題】しかしながら、 前記従来例は何れもベアチップLSI9の実装領域が配線上の完全なデッドスペースとなり、高密度実装のネックとなる。 [SUMMARY OF THE INVENTION However, the conventional mounting area of ​​both the bare chip LSI9 becomes full dead space on the wiring, a neck-density mounting. 又ベアチップLSI9をEMI(Electro Magnetic The bare chips LSI9 EMI (Electro Magnetic
Interference;電磁波障害)等から守る構造においても問題がある。 Also there is a problem in the structure to protect against electromagnetic interference) or the like; Interference. 一方、放熱性については、回路基板15が有機系材料の場合、放熱用にスルーホールを設けて放熱させる構造があるが、放熱効果は少ない。 On the other hand, the heat radiation, when the circuit board 15 is an organic material, there is a structure for heat dissipation through holes provided for the heat dissipation, the heat radiation effect is small. 等の問題点があった。 There has been a problem point etc. is.

【0007】本発明は、かかる問題点に鑑みて、回路モジュールの小形化、高密度実装化及び高放熱化が図れ、 [0007] The present invention, in view of the above problems, Hakare is miniaturized, high-density mounting and high heat dissipation of the circuit module,
且つEMI対策も講じられたベアチップLSIの実装構造を提供することを目的とする。 And an object thereof is to provide a mounting structure of the bare chip LSI also been taken EMI countermeasure.

【0008】 [0008]

【課題を解決するための手段】上記目的は、図1に示す如く、 [1] 多層構成の回路基板1のベアチップLSI9の搭載部が段付凹部2を成し、底面には内層の広範囲に広がり面を有し、ベアチップLSI9をダイボンディングさせる内層導体3が露出し、段部21にはベアチップLSI9 Above object In order to achieve the above, as shown in FIG. 1, [1] constitute mounting portions of the bare chip LSI9 circuit board 1 of the multilayer structure is a stepped recess 2, the bottom lining of the extensively has a spreading surface, the bare chip LSI 9 exposed inner conductor 3 for die bonding, bare chips with the stepped portion 21 LSI 9
の端子と接続する回路端子4が、対向位置に内層導体により形成配設してあり、段付凹部2の表面縁部には接地回路に通じる環状の導体パターン11を有し、一面が全導体面51を成し、他の面に絶縁して回路パターン52を形成させたキャップ5にて、段付凹部2を覆い、全導体面51 Circuit terminals 4 to be connected to the terminal, Yes forms provided by the inner layer conductor to the opposite position, the surface edge of the stepped recess 2 has an annular conductive pattern 11 leading to the ground circuit, one side all conductor It forms a surface 51 at the cap 5 to form a circuit pattern 52 and insulating the other surface, covering the stepped recess 2, the total conductive surface 51
を前記導体パターン11に密着固定させて段付凹部2内部を密封し、回路パターン52を回路基板1の表面回路パターン12に接続させて成る、本発明のベアチップLSIの実装構造により達成される。 The by tightly fixed to the conductor pattern 11 to seal the recess 2 internal stepped, made by connecting the circuit pattern 52 on the surface circuit pattern 12 of the circuit board 1 is achieved by the mounting structure of the bare chip LSI of the present invention. [2] 又、ベアチップLSI9をダイボンディングする内層導体3にスルーホール6を設け、スルーホール6に、 [2] In addition, a through hole 6 provided bare LSI9 the inner conductor 3 of die bonding, the through holes 6,
回路基板1の金属カバー7又は回路基板1を収容する金属ケースに突設した金属ピン71を挿入固着させて成る、 Comprising inserting fixed to cause the metal pin 71 projecting from the metal case that houses the metal cover 7 or circuit board 1 of the circuit board 1,
上記発明のベアチップLSIの実装構造によっても適えられる。 It is met by the mounting structure of the bare chip LSI of the present invention. [3] 更に、キャップ5の回路パターン52を形成した面に表面実装型部品91を実装する、上記発明のベアチップL [3] In addition, to implement the surface mount component 91 to the surface formed with the circuit pattern 52 of the cap 5, the bare chip L of the invention
SIの実装構造によっても達成される。 Also achieved by mounting structure of SI.

【0009】 [0009]

【作用】即ち、ベアチップLSI9は回路基板1の段付凹部2に収容し、キャップ5にて蓋して密封実装し、ダイボンディングした内層導体3と、キャップ5の全導体面51とにより上下両面が導体にて覆われ、外側の全導体面51は導体パターン11を介して回路基板1の接地回路に接地されるので、EMIに対する遮蔽効果を有する。 [Action] That is, the bare chip LSI9 is ​​accommodated in the stepped recess 2 of the circuit board 1, a lid was sealed implemented by the cap 5, an inner layer conductor 3 that is die-bonded, the upper and lower surfaces by the total conductive surface 51 of the cap 5 There is covered with the conductor, the outer of the total conductive surface 51 is grounded to the ground circuit of the circuit board 1 via the conductive pattern 11 has a shielding effect against EMI.

【0010】又、キャップ5の表側面には、回路基板1 [0010] In addition, the front surface of the cap 5, the circuit board 1
の表面回路パターン12と接続する回路パターン52が形成されるので、ベアチップLSI9の実装領域にも配線が行われることとなり、更には、表面実装型部品91も実装できるので、実装密度が高められる。 Since the circuit pattern 52 connected to the surface circuit pattern 12 is formed, it becomes possible to interconnect to the mounting area of ​​the bare chip LSI9 is ​​performed, furthermore, since the surface-mounted components 91 can also be mounted, the mounting density is increased.

【0011】ベアチップLSI9の放熱性は、ダイボンディングした内層導体3が広範囲に広がり面を有しており、その導体厚及び面積を増やすことにより放熱性を高める効果が有る。 [0011] heat dissipation of the bare chip LSI9 has a surface spread wide inner layer conductor 3 that is die-bonded, there is the effect of enhancing the heat dissipation by increasing the conductor thickness and area.

【0012】より高放熱性を要するものには、更に、内層導体3にスルーホール6を設け、これに金属カバー7 [0012] to those from requiring high heat dissipation property, further, the through hole 6 provided in the inner conductor 3, this metal cover 7
や金属ケースに突設した金属ピン71を挿着させて、スルーホール6から金属ピン71を介して金属カバー7に伝熱させ、外部に放熱させる。 And metal case is inserted a metal pin 71 which projects through the metal pin 71 is conducted to the metal cover 7 from the through hole 6, it is radiated to the outside. 金属カバー7や金属ケースは、回路基板1と同じ大きさ以上と十分に大きく、放熱量を十分に大きく得ることができる。 Metal cover 7 and the metal case is the same size or larger and sufficiently large and the circuit board 1, it is possible to obtain a sufficiently large heat dissipation.

【0013】かくして、本発明により、回路モジュールの小形化、高密度実装化及び高放熱化が図れ、且つEM [0013] Thus, the present invention, Hakare is miniaturized, high-density mounting and high heat dissipation of a circuit module, and EM
I対策も講じられたベアチップLSIの実装構造を提供することが可能となる。 It is possible to provide a mounting structure of the bare chip LSI which I have measures also taken.

【0014】 [0014]

【実施例】以下図面に示す実施例によって本発明を具体的に説明する。 EXAMPLES Specific examples illustrate the present invention shown in the drawings below. 全図を通し同一符号は同一対象物を示す。 Same reference numerals throughout the drawings denote the same object. 図1に本発明の一実施例の構造断面図を示す。 It shows a structural cross-sectional view of an embodiment of the present invention in FIG.

【0015】図1に示す如く、セラミック基材の多層構成の回路基板1には、ベアチップLSI9の実装位置に段付凹部2が設けられ、底面には内層の略回路基板1の全面に広がり、回路配線より厚手の内層導体3を露出させており、段部21にはベアチップLSI9の端子と接続する回路端子4が、対向位置に内層導体により形成され配設してある。 [0015] As shown in FIG. 1, the circuit board 1 in the multilayer structure of the ceramic substrate, stepped recess 2 is provided on the mounting position of the bare chip LSI 9, spread over the entire surface of substantially the circuit board 1 of the inner layer to the bottom surface, and exposing a thick inner layer conductor 3 than the circuit wiring, the stepped portion 21 circuit terminal 4 to be connected to the terminal of the bare chip LSI9 is, are arranged is formed by the inner conductor to the opposite position. 更に、段付凹部2の表面縁部には、接地回路に通じる環状の導体パターン11が形成してある。 Further, the surface edge of the stepped recess 2 is formed an annular conductive pattern 11 leading to the ground circuit.

【0016】更に、段付凹部2の周りに近く、ベアチップLSI9をダイボンディングした内層導体3に通じるスルーホール6が設けてある。 Furthermore, close around the stepped recess 2, through-holes 6 communicating the bare chip LSI9 the inner conductor 3 of the die bonding is provided. 回路基板1を覆う金属カバー7には、このスルーホール6に挿入させる銅の金属ピン71が、対応位置毎に鑞付けして垂設してある。 The metal cover 7 for covering the circuit board 1, a metal pin 71 of copper is inserted into the through hole 6, it is then vertical set in brazed to each corresponding position.

【0017】段付凹部2を覆うキャップ8は、銅薄板の一面に合成樹脂の絶縁層、導体層を積層させたもので、 The cap 8 covering the stepped recess 2, an insulating layer of synthetic resin on one surface of the copper sheet, in which a laminate of the conductive layer,
裏面が全導体面51を成し、表面に絶縁して回路パターン Back surface forms a whole conductive surface 51, the circuit is insulated on the surface pattern
52を形成させており、更に、表面実装型部品91を搭載実装している。 52, to form a further, are mounted implement surface mount component 91.

【0018】ベアチップLSI9を段付凹部2の底面の内層導体3にダイボンディングし、その端子と、段部21 The die-bonded to bare LSI9 the bottom surface of the inner layer conductor 3 of the stepped recess 2, and its terminals, stepped portion 21
の回路端子4とをワイヤボンディングして接続する。 And a circuit terminal 4 connected to wire bonding. 次に、キャップ5を段付凹部2にあてがい、全導体面51を縁部の導体パターン11に半田付けして段付凹部2内部を密封する。 Next, Ategai cap 5 in the stepped recess 2, the entire conductor surface 51 is soldered to the conductor pattern 11 of the edges to seal the recess 2 internal stepped.

【0019】最後に、キャップ5の回路パターン52の端部と、回路基板1の対向する表面回路パターン12とを、 [0019] Finally, an end portion of the circuit pattern 52 of the cap 5, and a surface circuit pattern 12 facing the circuit board 1,
ワイヤボンディングして回路接続する。 Circuitry connected to the wire bonding. 上記実施例は一例を示し、各部の形状、材料は上記のものに限定するものではない。 The above embodiment shows an example, each part of the shape, the material is not limited to those described above.

【0020】ベアチップLSI9と回路端子4、キャップ5の回路パターン52と回路基板1の表面回路パターン The bare chip LSI9 and circuit terminal 4, the surface circuit pattern of the circuit pattern 52 and the circuit board 1 of the cap 5
12とのワイヤボンディングを、TAB(Tape Automated Wire bonding with 12, TAB (Tape Automated
Bon-ding) による接続でも差支えない。 Bon-ding) no problem even by the connection.

【0021】回路基板1はセラミック基材としたが、紙や布、ガラス等の繊維と合成樹脂から成る積層基材でも良く、又、キャップ5も銅薄板の基材としたが回路基板1と同基材でも良い。 [0021] While the circuit board 1 is a ceramic base material, paper or cloth may be a laminated substrate composed of fibers with synthetic resins such as glass, and the cap 5 also base material of the copper sheet was but the circuit board 1 it may be the same substrate.

【0022】 [0022]

【発明の効果】以上の如く、本発明のベアチップLSI Effect of the Invention] As mentioned above, the bare chip LSI of the present invention
の実装構造により、回路モジュールの小形化、高密度実装化が行え、且つ放熱特性の向上が図れ、更に、EMI The mounting structure, miniaturization of circuit modules, can do high-density packaging, and model improves heat dissipation characteristics, and further, EMI
対策も講じられた実装構造が得られ、電気特性及び信頼性の向上が可能となる。 Measures also have mounting structure is obtained taken, thereby improving the electrical characteristics and reliability.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の一実施例の構造断面図 Structural cross-sectional view of an embodiment of the present invention; FIG

【図2】 従来例のベアチップLSIの実装構造 (a) 樹脂封止 (b) キャップ封止 [Figure 2] mounting structure of the bare chip LSI in the prior art (a) a resin sealing (b) a cap sealing

【符号の説明】 DESCRIPTION OF SYMBOLS

1,15 回路基板 2,25 段付凹部 3 1, 15 circuit board 2,25 stepped recess 3
内層導体 4 回路端子 5,55 キャップ 6 Innerlayer conductor 4 circuit terminals 5 and 55 the cap 6
スルーホール 7 金属カバー 9 ベアチップLSI 11 Through-hole 7 metal cover 9 bare chip LSI 11
導体パターン 12 表面回路パターン 21,26 段部 51 The conductor pattern 12 surface circuit pattern 21, 26 step portion 51
全導体面 52 回路パターン 71 金属ピン 91 All conductive surfaces 52 circuit pattern 71 metal pin 91
表面実装型部品 99 樹脂 Surface mount components 99 resin

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 多層構成の回路基板(1) のベアチップL 1. A bare chip of the circuit board having a multilayer structure (1) L
    SI(9) の搭載部が段付凹部(2) を成し、 底面には内層の広範囲に広がり面を有し、該ベアチップLSI(9) をダイボンディングさせる内層導体(3) が露出し、 段部(21)には該ベアチップLSI(9) の端子と接続する回路端子(4) が、対向位置に内層導体により形成配設してあり、 該段付凹部(2) の表面縁部には接地回路に通じる環状の導体パターン(11)を有し、 一面が全導体面(51)を成し、他の面に絶縁して回路パターン(52)を形成させたキャップ(5) にて、該段付凹部 SI (9) mounting portion forms a recess stepped (2) of having a spreading surface in a wide range of the inner layer on the bottom, the inner conductor (3) for die-bonding the bare chip LSI (9) is exposed, stepped portions (21) circuit terminal (4) connected to the terminals of the bare chip LSI (9) in the, Yes forms provided by the inner layer conductor to the opposite position, the surface edge of the recess (2) with stepped has an annular conductor pattern leading to a ground circuit (11), in a cap with one side to form a form a total conductor surface (51), the circuit pattern and insulating the other side (52) (5) , recess with stepped
    (2) を覆い、該全導体面(51)を前記導体パターン(11)に密着固定させて段付凹部(2) 内部を密封し、該回路パターン(52)を該回路基板(1) の表面回路パターン(12)に接続させて成ることを特徴とするベアチップLSIの実装構造。 (2) covering the, 該全 conductor surface (51) is sealed inside contact fixed so recess stepped (2) to the conductor pattern (11), the circuit pattern (52) a circuit board (1) mounting structure of the bare chip LSI which is characterized by comprising by connected to the surface circuit pattern (12).
  2. 【請求項2】 ベアチップLSI(9) をダイボンディングする内層導体(3)にスルーホール(6) を設け、該スルーホール(6) に、回路基板(1) の金属カバー(7) 又は該回路基板(1)を収容する金属ケースに突設した金属ピン Wherein a through hole (6) provided bare chip LSI (9) to the inner conductor (3) which is die-bonded, to the through-hole (6), a metal cover of the circuit board (1) (7) or the circuit metal pin projecting from the metal case for accommodating the substrate (1)
    (71)を挿入固着させて成ることを特徴とする請求項1記載のベアチップLSIの実装構造。 Mounting structure of the bare chip LSI according to claim 1, wherein (71) is inserted fixed, characterized by comprising.
  3. 【請求項3】 キャップ(5) の回路パターン(52)を形成した面に表面実装型部品(91)を実装することを特徴とする請求項1記載のベアチップLSIの実装構造。 3. A cap (5) mounting structure of the bare chip LSI according to claim 1, wherein the implementing a surface mount component (91) to form the surface of the circuit pattern (52) of.
JP3266596A 1991-10-16 1991-10-16 Mounting structure of the bare chip lsi Expired - Fee Related JP2973646B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3266596A JP2973646B2 (en) 1991-10-16 1991-10-16 Mounting structure of the bare chip lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3266596A JP2973646B2 (en) 1991-10-16 1991-10-16 Mounting structure of the bare chip lsi

Publications (2)

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JPH05114776A true JPH05114776A (en) 1993-05-07
JP2973646B2 JP2973646B2 (en) 1999-11-08

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08148800A (en) * 1994-11-16 1996-06-07 Nec Corp Mounting structure of circuit part
US5875100A (en) * 1996-05-31 1999-02-23 Nec Corporation High-density mounting method and structure for electronic circuit board
WO2001065604A3 (en) * 2000-02-28 2002-01-31 Ericsson Inc Functional lid for rf power package

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267449A (en) 2000-03-15 2001-09-28 Nec Corp Lsi package and internal connection method for use therein

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08148800A (en) * 1994-11-16 1996-06-07 Nec Corp Mounting structure of circuit part
US5875100A (en) * 1996-05-31 1999-02-23 Nec Corporation High-density mounting method and structure for electronic circuit board
WO2001065604A3 (en) * 2000-02-28 2002-01-31 Ericsson Inc Functional lid for rf power package

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Publication number Publication date
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