JPH0732216B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0732216B2 JPH0732216B2 JP31896888A JP31896888A JPH0732216B2 JP H0732216 B2 JPH0732216 B2 JP H0732216B2 JP 31896888 A JP31896888 A JP 31896888A JP 31896888 A JP31896888 A JP 31896888A JP H0732216 B2 JPH0732216 B2 JP H0732216B2
- Authority
- JP
- Japan
- Prior art keywords
- high thermal
- semiconductor device
- thermal conductive
- conductive plate
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、樹脂封止型半導体装置に関して、熱抵抗を
低くして放熱性を高めようとするものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a resin-encapsulated semiconductor device in which thermal resistance is reduced to enhance heat dissipation.
第６図は従来の樹脂封止型半導体装置を示す平面断面図
であり、第７図は第６図のVII−VII線断面図である。図
において、１は半導体集積回路装置（以下ICと称する）
チップ、２は上記ICチップ１を搭載するアイランド、３
は上記アイランド２を固定する吊リード、４はアイラン
ド２を囲むように配置されたインナーリード、５は上記
ICチップ１上の電極とインナーリード４とを接続する金
属細線（金線等）、６はモールド樹脂である。FIG. 6 is a plan sectional view showing a conventional resin-encapsulated semiconductor device, and FIG. 7 is a sectional view taken along line VII-VII of FIG. In the figure, 1 is a semiconductor integrated circuit device (hereinafter referred to as an IC)
Chip 2 is an island on which the IC chip 1 is mounted, 3
Is a suspension lead for fixing the island 2, 4 is an inner lead arranged so as to surround the island 2, and 5 is the above
Thin metal wires (gold wire or the like) for connecting the electrodes on the IC chip 1 and the inner leads 4 and 6 are molding resins.
上記の様な従来の樹脂封止型半導体装置では、構成材料
であるモールド封止樹脂の熱伝導率が低いため、パッケ
ージ全体に熱が放散せず、放熱性が悪かった。In the conventional resin-encapsulated semiconductor device as described above, the heat conductivity of the mold-encapsulating resin, which is a constituent material, is low, so that heat is not radiated to the entire package and the heat dissipation is poor.
この発明は上記のような問題点を解消するためになされ
たもので、パッケージの全体の熱抵抗を低くして、放熱
性を高めることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object thereof is to reduce the heat resistance of the entire package and improve the heat dissipation.
この発明に係る半導体装置は、半導体集積回路チップを
搭載したリードフレームと、位置決め及び仮固定用の突
起並びに支持用の突起を有する広面積の高熱伝導板を備
え、前記高熱伝導板の位置決め及び仮固定用の突起を前
記リードフレームに設けた穴部に係合し、さらに支持用
の突起を外部より保持して樹脂封止成形したものであ
る。A semiconductor device according to the present invention includes a lead frame on which a semiconductor integrated circuit chip is mounted, a wide area high thermal conductive plate having a protrusion for positioning and temporary fixing, and a protrusion for supporting, and positioning and temporary positioning of the high thermal conductive plate. The fixing projection is engaged with a hole provided in the lead frame, and the supporting projection is held from the outside, and is resin-sealed and molded.
この発明の半導体装置は、高熱伝導板を半導体集積回路
チップを搭載したアイランドに近づけることができ、チ
ップで発生した熱を抵抗なく高熱伝導板に伝えることが
でき、さらに高熱伝導板が広面積を有しているので装置
全体に放熱される。さらに高熱伝導板に設けた支持用突
起を外部より支持して樹脂封止することにより伝導板自
体が流れることがない。In the semiconductor device of the present invention, the high thermal conductive plate can be brought close to the island on which the semiconductor integrated circuit chip is mounted, the heat generated in the chip can be transferred to the high thermal conductive plate without resistance, and the high thermal conductive plate has a large area. Since it has it, heat is radiated to the entire device. Furthermore, the support plate provided on the high heat conductive plate is supported from the outside by resin sealing, so that the conductive plate itself does not flow.
第１図は、この発明の一実施例による半導体装置の構成
部品であるリードフレームを示す平面図、第２図は上記
実施例の半導体装置の構成部品である高熱伝導材を示す
平面図、第３図は第２図のIII−III線断面図である。ま
た、第４図は第１図のリードフレームと第２図の高熱伝
導板を用いて樹脂封止成形した半導体装置の平面断面
図、第５図は第４図のＶ−Ｖ線断面図である。FIG. 1 is a plan view showing a lead frame which is a component of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view showing a high thermal conductive material which is a component of the semiconductor device of the above embodiment. FIG. 3 is a sectional view taken along line III-III in FIG. 4 is a plan sectional view of a semiconductor device resin-molded using the lead frame of FIG. 1 and the high thermal conductive plate of FIG. 2, and FIG. 5 is a sectional view taken along line VV of FIG. is there.
図において、１は半導体集積回路（以下ICと称する）チ
ップ、２は上記ICチップ１を搭載するアイランド、３は
上記アイランド２を固定する吊リード、４はインナーリ
ード、５は金属細線、６は封止樹脂、７はリードフレー
ムの吊リード３に設けられた位置決め及び仮固定用の穴
である。８は高熱伝導材10の一方に設けられた突起であ
り、上記穴７に係合して位置決め及び仮固定の役目を果
たすものである。９は高熱伝導部材10の他の一方に設け
られた突起であり、樹脂封止作業中に封止樹脂６の流れ
により高熱伝導部材が働くことのないように支持するた
めのものである。また上記仮固定用の突起７はできるだ
け短くして、組立時にリードフレームのアイランド２と
できるだけ接近する構成とする。そして高熱伝導板10は
放熱性を良くするためできるだけ広範囲に拡がる形状と
するのが望ましい。In the figure, 1 is a semiconductor integrated circuit (hereinafter referred to as IC) chip, 2 is an island on which the IC chip 1 is mounted, 3 is a suspension lead for fixing the island 2, 4 is an inner lead, 5 is a fine metal wire, and 6 is Sealing resin 7 is a hole for positioning and temporary fixing provided in the suspension lead 3 of the lead frame. Reference numeral 8 denotes a protrusion provided on one side of the high thermal conductive material 10, which engages with the hole 7 and serves for positioning and temporary fixing. Reference numeral 9 is a protrusion provided on the other side of the high thermal conductivity member 10, and is for supporting the high thermal conductivity member so that it does not work due to the flow of the sealing resin 6 during the resin sealing work. Further, the provisional fixing projection 7 is made as short as possible so as to be as close as possible to the island 2 of the lead frame during assembly. It is desirable that the high thermal conductive plate 10 has a shape that spreads in as wide a range as possible in order to improve heat dissipation.
上記のように構成された半導体装置において、リードフ
レームの穴７はあらかじめエッチング及びパンチング等
により形成されており、又高熱伝導材10もエッチング又
はパンチング等によりパターンが形成され、曲げ加工等
で突起部8,9が形成されている。In the semiconductor device configured as described above, the hole 7 of the lead frame is previously formed by etching and punching, and the high thermal conductive material 10 is also formed with a pattern by etching or punching. 8 and 9 are formed.
次に組立工程について説明する。まずICチップ１をアイ
ランド２に半田等により接続する。そして、ICチップ１
とインナーリード４間を金属細線５で電気的に接続す
る。そして、このフレームをICチップ１を下面にして、
樹脂封止金型に設置する。更にこのリードフレームの穴
７に高熱伝導材10の突起８を差し込み、位置決め及び仮
固定を行う。この状態で、封止樹脂６を注入して樹脂封
止成形する。この時、高熱伝導材10の突起９を外部より
支持して樹脂の流れで高熱伝導材10が動かないようにし
ている。その後は従来通り、メッキ及びリード加工を行
う。上記実施例において、ICチップ１を搭載したアイラ
ンド２と高熱伝導板10との間を狭く構成しているため、
その間の封止樹脂６が薄くなり熱抵抗は低くなる。さら
に装置全体に熱伝導性の良い板が広がる様に構成したの
で、熱が装置全体に広がり、結果的に装置全面からの放
熱となって放熱性が良好となる。Next, the assembly process will be described. First, the IC chip 1 is connected to the island 2 by soldering or the like. And IC chip 1
And the inner lead 4 are electrically connected with a thin metal wire 5. Then, with this frame with the IC chip 1 as the bottom surface,
Install in a resin-sealed mold. Further, the protrusion 8 of the high thermal conductive material 10 is inserted into the hole 7 of this lead frame to perform positioning and temporary fixing. In this state, the sealing resin 6 is injected to mold the resin. At this time, the protrusion 9 of the high thermal conductive material 10 is supported from the outside so that the high thermal conductive material 10 does not move due to the resin flow. After that, plating and lead processing are performed as usual. In the above-described embodiment, since the space between the island 2 on which the IC chip 1 is mounted and the high thermal conductive plate 10 is narrow,
During that time, the sealing resin 6 becomes thin and the thermal resistance becomes low. Further, since the plate having good heat conductivity is spread over the entire device, heat is spread over the entire device, and as a result, heat is radiated from the entire surface of the device, and the heat dissipation is improved.
以上のようにこの発明によれば、高熱伝導板を簡単な方
法で取りつけることができ、熱抵抗が低くて放熱性の良
好な半導体装置が得られる効果がある。As described above, according to the present invention, it is possible to attach the high thermal conductive plate by a simple method, and it is possible to obtain a semiconductor device having low heat resistance and good heat dissipation.
第１図はこの発明の一実施例による半導体装置のリード
フレームを示す平面図、第２図は上記実施例の半導体装
置の高熱伝導板を示す平面図、第３図は第２図のIII−I
II線断面図、第４図は上記実施例による半導体装置の完
成品を示す平面断面図、第５図は第４図のＶ−Ｖ線断面
図、第６図は従来の半導体装置を示す平面断面図、第７
図は第６図のVII−VII線断面図である。 図において、１は半導体集積回路チップ、２はアイラン
ド、３は吊リード、４はインナーリード、５は金属細
線、６は封止樹脂、７は穴、10は高熱伝導板、8,9は突
起である。 なお、図中同一符号は同一又は相当部分を示す。FIG. 1 is a plan view showing a lead frame of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view showing a high thermal conductive plate of the semiconductor device of the above embodiment, and FIG. 3 is III- of FIG. I
II sectional view, FIG. 4 is a plan sectional view showing a completed semiconductor device according to the above embodiment, FIG. 5 is a sectional view taken along line VV of FIG. 4, and FIG. 6 is a plan view showing a conventional semiconductor device. Sectional view, No. 7
The figure is a sectional view taken along line VII-VII of FIG. In the figure, 1 is a semiconductor integrated circuit chip, 2 is an island, 3 is a suspension lead, 4 is an inner lead, 5 is a thin metal wire, 6 is a sealing resin, 7 is a hole, 10 is a high thermal conductive plate, and 8 and 9 are protrusions. Is. The same reference numerals in the drawings indicate the same or corresponding parts.
Claims (1)
レームと、位置決め及び仮固定用の突起並びに支持用の
突起を有する広面積の高熱伝導板を備え、前記高熱伝導
板の位置決め及び仮固定用の突起を前記リードフレーム
に設けた穴部に係合し、さらに支持用の突起を外部より
保持して樹脂封止成形した半導体装置。1. A lead frame on which a semiconductor integrated circuit chip is mounted, and a wide area high thermal conductive plate having a protrusion for positioning and temporary fixing and a protrusion for supporting, and for positioning and temporarily fixing the high thermal conductive plate. A semiconductor device in which a protrusion is engaged with a hole provided in the lead frame, and further, a supporting protrusion is externally held and resin-molded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31896888A JPH0732216B2 (en) | 1988-12-16 | 1988-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31896888A JPH0732216B2 (en) | 1988-12-16 | 1988-12-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02163954A JPH02163954A (en) | 1990-06-25 |
| JPH0732216B2 true JPH0732216B2 (en) | 1995-04-10 |
Family
ID=18105005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31896888A Expired - Fee Related JPH0732216B2 (en) | 1988-12-16 | 1988-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732216B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387554A (en) * | 1992-09-10 | 1995-02-07 | Vlsi Technology, Inc. | Apparatus and method for thermally coupling a heat sink to a lead frame |
| JP2912134B2 (en) * | 1993-09-20 | 1999-06-28 | 日本電気株式会社 | Semiconductor device |
| JP3123482B2 (en) | 1997-10-08 | 2001-01-09 | 日本電気株式会社 | Low thermal resistance semiconductor package and method of manufacturing low thermal resistance semiconductor package |
| US7084494B2 (en) * | 2004-06-18 | 2006-08-01 | Texas Instruments Incorporated | Semiconductor package having integrated metal parts for thermal enhancement |
| JP5096812B2 (en) * | 2007-06-28 | 2012-12-12 | 株式会社三井ハイテック | Semiconductor device using composite lead frame |
-
1988
- 1988-12-16 JP JP31896888A patent/JPH0732216B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02163954A (en) | 1990-06-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |