KR940007537B1 - Sheet type semiconductor package and manufacturing method thereof - Google Patents

Sheet type semiconductor package and manufacturing method thereof Download PDF

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Publication number
KR940007537B1
KR940007537B1 KR1019910007761A KR910007761A KR940007537B1 KR 940007537 B1 KR940007537 B1 KR 940007537B1 KR 1019910007761 A KR1019910007761 A KR 1019910007761A KR 910007761 A KR910007761 A KR 910007761A KR 940007537 B1 KR940007537 B1 KR 940007537B1
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South Korea
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chip
fixed
bumps
lead
semiconductor package
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KR1019910007761A
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Korean (ko)
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KR920022460A (en
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고준수
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금성일랙트론 주식회사
문정환
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Priority to KR1019910007761A priority Critical patent/KR940007537B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

The method manufactures the sheet type semiconductor package which can simultaneously use both the TAB technology and the conventional PCB circuit patterns. The method comprises the steps of: (A) formualting several Au bumps (12)(12') on a semiconductor chip, (B) fixing the inner leads (13)(13') of the TAB tape to the bumps, (C) covering the surface of the chip with polyimid (14) or epoxy (15), (D) placeing the lead frames (17)(17') on the heat block using the adhesive (16) such as polyimid, (E) after the fixing of the inner leads on the convexes (17a)(17'a) of the lead frames, eliminating the heat blocks.

Description

시트형 반도체 패키지 및 그 제조방법Sheet-shaped semiconductor package and manufacturing method thereof

제 1 도는 일반적인 플라스틱 반도체 패키지 제조방법을 설명하기 위한 제조공정도.1 is a manufacturing process diagram for explaining a general plastic semiconductor package manufacturing method.

제 2 도는 제 1 도에 의한 QFP의 전형적인 일례를 보인 단면도.2 is a cross-sectional view showing a typical example of the QFP according to FIG.

제 3 도는 일반적인 TAB 기술에 의한 반도체 패키지 제조방법을 설명하기 위한 제조공정도.3 is a manufacturing process diagram for explaining a method for manufacturing a semiconductor package by a general TAB technology.

제 4 도의 a 및 b는 본 발명에 의한 시트형 반도체 패키지의 전형적인 일시예를 보인 QFP의 단면도.4A and 4B are cross-sectional views of a QFP showing a typical temporary example of a sheet-shaped semiconductor package according to the present invention.

제 5 도는 본 발명에 의한 시트형 반도체 제조방법을 설명하기 위한 공정흐름도.5 is a process flow chart for explaining the sheet-like semiconductor manufacturing method according to the present invention.

제 6 도의 a 내지 e는 제 4 도에 의한 QFP의 제조공정을 순차적으로 보인 제조공정도.6 is a manufacturing process diagram sequentially showing the manufacturing process of the QFP according to FIG.

제 7 도의 a는 본 발명에 의한 시트형 반도체 패키지의 일실시예를 보인 정면도. b는 본 발명에 의한 시트형 반도체 패키지의 다른 실시예를 보인 정면도.7 is a front view showing an embodiment of a sheet-shaped semiconductor package according to the present invention. b is a front view showing another embodiment of the sheet-shaped semiconductor package according to the present invention.

제 8 도는 제 6 도 d의 하측 도면에 대응되는 평면도.8 is a plan view corresponding to the lower view of FIG.

제 9 도는 본 발명에 따른 실시예를 보인것으로, SOP에 적용된 상태를 보인 제 6 도 d의 하측 도면에 대응되는 평면도.9 is a plan view corresponding to the lower view of FIG. 6 d showing a state applied to the SOP, showing an embodiment according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : IC칩 12, 12' : 범프11: IC chip 12, 12 ': bump

13, 13' : 인너리드 14, 16 : 폴리이미드13, 13 ': inner lead 14, 16: polyimide

15 : 에폭시 17, 17' : 리드프레임15: epoxy 17, 17 ': lead frame

17a, 17'a : 절곡부 18 : 히트블럭17a, 17'a: bending portion 18: heat block

본 발명은 시트(sheet)형 반도체 패키지(semiconduct package) 및 그 제조방법에 관한것으로, 특히 TAB(Tape Automatic Bonding)기술을 기존의 PCB(Printeel Circuit Board) 패턴을 그대로 이용할 수 있는 리드 프레임에 적용하여 소자의 박형(thin)에 기여하고, 제조원가를 절감시킴과 아울러 생산성을 향상시킬 수 있게 한 시트형 반도체 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a sheet-type semiconductor package (semiconduct package) and a method of manufacturing the same, in particular by applying a tape automatic bonding (TAB) technology to a lead frame that can use the existing PCB (Printeel Circuit Board) pattern as it is The present invention relates to a sheet-shaped semiconductor package and a method for manufacturing the same, which contribute to thin device, reduce manufacturing cost and improve productivity.

일반적으로 반도체 패키지를 제조함에 있어서는, 여러가지 방법의 제조기술이 알려지고 있는바, 플라스틱 패키지 기술과, TAB(Tape Automatic Bonding) 기술에 대하여 설명하면 다음과 같다.In general, in manufacturing a semiconductor package, various manufacturing techniques are known. The plastic packaging technique and the tape automatic bonding (TAB) technique will be described below.

먼저, 플라스틱 패키지 제조방법은 제 1 도에 도시한 바와같이, 웨이퍼(wafer)로 부터 칩(chip)을 절단(saw)하는 칩절단 공정과, 리드 프레임(lead frame)의 패들(paddle)에 에폭시(epoxy)를 도포한 상태에서 칩을 부착하는 다이본딩(die bonding)공정가, 패들에 부착된 칩의 패드(pad)에 리드 프레임의 인너리드(inner lead)를 와이어(wire)로 연결하는 와이어 본딩(wire bonding)공정과, 칩이 얹혀지는 패들 부위 및 인너리드를 포함하는 일정면적을 에폭시 수지로 몰딩(molding)하는 몰딩공정과, 리드 프레임과 패들을 연결하는 소포트바(support bar) 및 각 리드를 연결하는 댐버(damber), 그리고 섹션바(section bar)를 절단하는 트림(trim) 공정과, 마지막으로 패키지의 각 아웃리드(out lead)를 소정형태로 절곡하는 포밍(froming) 공정의 순서로 진행된다.First, as shown in FIG. 1, the plastic package manufacturing method includes a chip cutting process of cutting a chip from a wafer, and an epoxy on a paddle of a lead frame. A die bonding process for attaching a chip in an epoxy coated state, and a wire bonding connecting an inner lead of a lead frame to a pad of a chip attached to a paddle by wire. (wire bonding) process, molding process of molding a certain area including the paddle part and inner lead on which the chip is placed, with epoxy resin, support bar connecting each lead frame and paddle, and each A sequence of dams connecting leads, a trim process of cutting section bars, and finally a forming process of bending each out lead of a package into a predetermined shape. Proceeds.

제 2 도는 상기한 바와 같은 플라스틱 패키지 제조방법에 의한 QFP(Quad Flat Package)의 전형적인 일례를 보인 것으로, 패들(1)의 상면에 에폭시등의 접착제(adhesive)(2)가 도포되어 칩(3)이 부착고정되고, 상기 칩(3)의 패드(도시되지 않음)과 리드 프레임의 인너리드(4)가 와이어(5)로 본딩되며, 상기 패들(1) 및 칩(3)을 포함하는 소정부위가 에폭시 수지(6)로 몰딩되고, 상기 인너리드(4)로부터 연장형성되는 아웃리드(4')가 인쇄회로기판(printed circuit board)(7)에 접속 고정되도록 소정의 형태로 절곡 형성된 구조로 되어 있다.2 shows a typical example of a quad flat package (QFP) according to the method of manufacturing a plastic package as described above. An adhesive (2) such as epoxy is applied to the upper surface of the paddle (1), thereby providing a chip (3). The fixing is fixed, the pad (not shown) of the chip 3 and the inner lead 4 of the lead frame are bonded to the wire 5, and a predetermined portion including the paddle 1 and the chip 3 Is molded with epoxy resin 6, and the outlead 4 'extending from the inner lead 4 is bent into a predetermined shape so as to be connected to and fixed to a printed circuit board 7 It is.

또한, TAB기술은 제 3 도에 도시한 바와같이, 웨이퍼 범핑 공정과, IC칩을 소정크기로 절단하는 절단(saw)공정과, TAB테이프의 인너리드를 본딩하는 인너리드 본딩공정과, 인캡슐레이션 공정과, 마킹(marking) 공정의 순서로 진행된다.Further, as shown in FIG. 3, the TAB technology includes a wafer bumping process, a sawing process of cutting an IC chip into a predetermined size, an inner lead bonding process of bonding an inner lead of a TAB tape, and an encapsulation. It proceeds in the order of the migration process and the marking process.

그러나 상기한 바와같은 종래의 기술에 있어서, 플라스틱 패키지 제조방법은 와이어(5)의 사용으로 인한 와이어 루프 높이(wire loop height)의 영향으로 패키지의 전체적인 두께(thickness)를 감소시키는 데 한계가 있으며, 또한 패드 영역중 실링(sealing)되지 않고 직접 에폭시수지(6)가 접촉되는 부분이 있으므로 소자의 신뢰성에 문제가 발생되는 단점이 있었다.However, in the prior art as described above, the plastic package manufacturing method has a limitation in reducing the overall thickness of the package due to the influence of the wire loop height due to the use of the wire (5), In addition, since there is a portion of the pad region in which the epoxy resin 6 is directly contacted without sealing, there is a problem in that the reliability of the device is generated.

한편, TAB기술은 본딩 패드(bonding pad)가 모두 메탈로 실링(sealing)되어 얇은 두께로 가질수 있으나, 기존의 PCB기판을 그대로 응용하기가 용이하지 못하여 실용화에 많은 어려움이 있었다.Meanwhile, in the TAB technology, all of the bonding pads are sealed with metal and may have a thin thickness, but there are many difficulties in practical application because it is not easy to apply the existing PCB substrate as it is.

즉, 기존 PCB의 패턴과 TAB 아웃리드(out lead)의 패턴이 서로 호환성(compatible)이 없으므로 TAB 아웃리드의 패턴에 어울리는 별도의 PCB를 제작하여야 하는 문제점이 있었다.That is, since the existing PCB pattern and the TAB out lead pattern are not compatible with each other, there is a problem in that a separate PCB suitable for the TAB outlead pattern needs to be manufactured.

한편, 일본 공개실용신안공보 소 62-17128(87, 2, 2)에 도전층으로 덮혀진 소자탑재부와 이 소자탑재부와 도통되는 전원전극부가 캐비티 내부에 설치되는 패키지와, 상기 소자탑재부에 고착된 반도체소자와, 상기 전원전극부에 접속된 상기 도전층을 개하여 상기 반도체소자와 도통하는 인출용 금속세선을 구비한 반도체장치에 있어서, 상기 전원전극부를 상기 캐비티 내부에 일체적으로 형성시킨 돌기부와, 이 돌기부의 상부에 형성되고 상기 도전층과 접속되고 또한 상기 금속세선과 접속되는 도전막을 구성한 것을 특징으로 하는 반도체장치가 알려지고 있으나, 그 반도체 역시 금속세선의 사용으로 패키지의 전체적인 두께를 감소시키지 못하는 등, 종래의 문제점을 완전하게 해결하지 못하였다.On the other hand, in the Japanese Utility Model Publication No. 62-17128 (87, 2, 2), an element mounting portion covered with a conductive layer and a power electrode portion conducting with the element mounting portion are installed in the cavity, and the element mounting portion is fixed to the element mounting portion. A semiconductor device comprising: a semiconductor device; and a lead metal thin wire for opening the conductive layer connected to the power supply electrode part to conduct with the semiconductor device, wherein the projection part integrally formed with the power electrode part in the cavity; A semiconductor device is known, which is formed on top of the protruding portion and constitutes a conductive film connected to the conductive layer and connected to the fine metal wire, but the semiconductor also does not reduce the overall thickness of the package by using the fine metal wire. Such problems did not completely solve the conventional problems.

본 발명의 목적은 상기한 바와같은 종래의 문제점을 해소하기 위하여 창안한 것으로, Al 패드부분이 메탈(Au)로 실링되어 신뢰성이 향상된 TAB 기술에 의한 패키지와, 기존의 PCB회로 패턴을 그대로 이용할 수 있도록 미리 성형(froming)된 리드 프레임을 접착시킴으로써 소자의 박형화에 기여함은 물로 TAB 기술에 필요한 별도의 PCB를 제작할 필요가 없으므로 제조원가를 절감시킬 뿐만 아니라 생산성을 향상시킬 수 있게한 시트형 반도체 패키지 및 그 제조방법을 제공함에 있다.An object of the present invention was devised to solve the above-mentioned problems, and the Al pad portion is sealed with metal (Au), and the package according to the improved TAB technology and the existing PCB circuit pattern can be used as it is. Contributing to the thinning of the device by gluing the lead frame preformed from so that it is not necessary to manufacture a separate PCB for the TAB technology with water, thereby reducing the manufacturing cost and improving the productivity To provide a manufacturing method.

이하, 본 발명의 일실시예를 첨부된 도면에 의하여 상세하게 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

본 발명에 의한 시트형 반도체 패키지는, 제 4 도에 a 및 b에 도시한 바와 같이, IC칩(반도체 칩이라고도 함)(11)의 상면 양측에 Au의 범프(12)(12')가 각각 형성되고, 상기 범프(12)(12')에 1-층(layer) TAB 테이프의 인너리드(copper)(13)(13')가 각각 부착고정되며, 상기 IC칩(11)의 상면에 폴리이미드(14) 또는 범프(12)(12')를 포함하는 소정면적에 에폭시(15)가 형성되고, 상기 IC칩(11)의 하면에 리드 프레임(17)(17')이 폴리이미드(16)등의 접착제로 접착고정되며, 상기 리드 프레임(17)(17')의 상부 절곡부(17a)(17a')에 상기 인너리드(13)(13')가 접착고정된 구조로 되어있다.In the sheet-shaped semiconductor package according to the present invention, bumps 12 and 12 'of Au are formed on both sides of the upper surface of the IC chip (also referred to as semiconductor chip) 11, as shown in Figs. Inner bumps 13 and 13 'of the 1-layer TAB tape are attached and fixed to the bumps 12 and 12', respectively, and a polyimide is formed on the upper surface of the IC chip 11. Epoxy 15 is formed in a predetermined area including 14 or bumps 12 and 12 ', and lead frames 17 and 17' are formed on the lower surface of the IC chip 11 to form polyimide 16. The inner leads 13 and 13 'are bonded to and fixed to the upper bent portions 17a and 17a' of the lead frames 17 and 17 '.

도면중 미설명부호 18은 리드 프레임(17)(17')의 본딩을 위한 블럭(heat block), 19, 19'는 솔더를 보인 것이다.In the drawing, reference numeral 18 denotes a heat block for bonding the lead frames 17 and 17 ', and 19 and 19' show solder.

상기한 바와같은 구조의 시트형 반도체 패키지를 제조하기 위한 제조방법을 제 5 도의 공정흐름도와, 제 6 도의 제조공정도를 참고로 설명하면 다음과 같다.The manufacturing method for manufacturing the sheet-like semiconductor package having the above-described structure will be described with reference to the process flow diagram of FIG. 5 and the process flow chart of FIG.

본 발명에 의한 시트형 반도체 패키지의 제조방법은, 제6도의 a에 도시한 바와같이, IC칩(11)의 상면 양측에 Au의 범프(12)(12')를 각각 형성하는 범핑공정과, 상기 범프(12)(12')에 1-층(layer) TAB 테이프의 인너리드(copper)(13)(13')를 각각 부착고정하는 인너리드 본딩공정과, c에 도시한 바와같이, IC칩(11)의 상면에 폴리이미드(14)를 형성하거나, (c')에 도시한 바와같이 범프(12)(12')를 포함하는 소정면적에 에폭시(15)를 씌우는 인캡슐레이션(encapsulation)공정과, d 및 제 8 도에 도시한 바와같이, 기존의 통상적인 PCB의 푸트 프린트(foot print)를 이용할 수 있도록 제작되어 폴리이미드(16)등의 접착제가 형성되고 소정형태로 포밍(forming)된 리드프레임(17)(17')을 e 및 (e')에 도시한 바와같이 히트블럭(18)에 얹은 다음, 리드 프레임(17)(17')의 상부 절곡부(17a)(17a')에 인너리드(13)(13')를 각각 부착고정하는 싱글 포인트 본딩(single point bonding)에 의한 2차 본딩공정으로 진행된다.A method for manufacturing a sheet-shaped semiconductor package according to the present invention includes a bumping step of forming bumps 12 and 12 'of Au on both sides of an upper surface of the IC chip 11, as shown in a of FIG. Inner lead bonding process of attaching inner leads 13 and 13 'of 1-layer TAB tape to bumps 12 and 12', respectively, and an IC chip as shown in c. Encapsulation to form polyimide 14 on the upper surface of (11) or to cover epoxy 15 on a predetermined area including bumps 12 and 12 'as shown in (c'). As shown in the process and d and 8, the foot print of an existing conventional PCB can be used to form an adhesive such as polyimide 16 and to form a predetermined shape. The lead frames 17 and 17 'onto the heat blocks 18 as shown in e and (e'), and then the upper bent portions 17a and 17a 'of the lead frames 17 and 17'. Inner lead (13) (13 ') The secondary bonding process by a single point bonding (single point bonding) to attach and fix each.

상기한 2차 본딩의 완료후에는 히터 블럭(18)을 제거시킴으로써 제 7 도의 a 및 b에 도시한 바와같은 본 발명의 시트형 반도체 패키지(QFP)가 제조되는 것이며, 상기 시트형 반도체 패키지는 통상적인 PCB기판에 실장된다.After completion of the secondary bonding, the sheet-shaped semiconductor package (QFP) of the present invention as shown in Figs. A and b is manufactured by removing the heater block 18, and the sheet-shaped semiconductor package is a conventional PCB. It is mounted on a substrate.

상기한 바와같은 본 발명의 실시예에서는 QFP에 적용한 경우를 설명하였으나, 본 발명은 QFP에만 적용되는 것은 아니며, 제 9 도에 도시한 바와같은 SOP(Small Outline Package) 및 그 외에 다른 형태의 패키지에도 적용할 수 있는 것이다.In the embodiment of the present invention as described above has been described in the case of applying to the QFP, the present invention is not only applied to the QFP, but also to the SOP (Small Outline Package) as shown in FIG. It is applicable.

제 8 도 및 제 9 도는 본 발명에 의한 시트형 반도체 패키지의 제조방법에 있어서, 제 6 도d의 하측 도면에 대응되는 평면도를 각각 보인 것이다.8 and 9 show plan views corresponding to the lower view of FIG. 6D in the method for manufacturing a sheet-shaped semiconductor package according to the present invention.

이상에서 설명한 바와같이 본 발명은 패드부분이 메탈로 실링되어 신뢰성이 TAB 패키지와, 기존의 PCB회로패턴을 이용할 수 있는 미리 성형된 리드 프레임을 접착시킴으로써 소자의 박형화에 기여할 뿐만 아니라 별도의 TAB 기술에 별도의 PCB를 제작할 필요가 없으므로 제조원가를 절감시키고 생산성을 향상시키는 효과가 있다.As described above, the present invention not only contributes to the thinning of the device by attaching a TAB package and a preformed lead frame that can use a conventional PCB circuit pattern because the pad portion is sealed with metal, and contributes to a separate TAB technology. There is no need to manufacture a separate PCB, which reduces manufacturing costs and improves productivity.

Claims (6)

IC칩(11)의 범퍼(12)(12')에 1-층 TAB테이프의 인너리드(13)(13')가 각각 고정됨과 아울러 IC칩(11)의 상면에 폴리이미드(14)가 형성되고, 상기 IC칩(11)의 하면에 상부 절곡부(17a)(17a')가 형성된 리드 프레임(17)(17')이 고정되며, 상기 리드 프레임(17)(17')의 상부 절곡부(17a)(17a')에 상기 인너리드(13)(13')가 고정된 것임을 특징으로 하는 시트형 반도체 패키지.The inner leads 13 and 13 'of the one-layer TAB tape are fixed to the bumpers 12 and 12' of the IC chip 11, and a polyimide 14 is formed on the upper surface of the IC chip 11. The lead frames 17 and 17 'having the upper bent portions 17a and 17a' are fixed to the lower surface of the IC chip 11, and the upper bent portions of the lead frames 17 and 17 'are fixed. And the inner leads (13) and (13 ') are fixed to (17a) and (17a'). 제 1 항에 있어서, 상기 리드 프레임(17)(17')의 상면에는 폴리이미드(16)가 도포되어 그 폴리이미드(16)에 IC칩(11)이 접착고정된 것임을 특징으로 하는 시트형 반도체 패키지.2. The sheet semiconductor package according to claim 1, wherein a polyimide (16) is coated on the upper surfaces of the lead frames (17) and (17 '), and the IC chip (11) is fixed to the polyimide (16). . 반도체 칩(11)에 범프(12)(12')를 형성하는 범핑공정과, 상기 범프(12)(12')에 인너리드(13)(13')를 부착고정하는 인너리드 본딩 공정과, 범프(12)(12')를 포함하는 소정면적에 에폭시(15)를 충진하는 인캡슐레이션공정과, 소정 형상의 상부 절곡부(17a)(17a')가 형성되고 폴리이미드(16)등의 접착제가 부착된 리드 프레임(17)(17')에 상기 반도체 칩(11)과 범프(12)(12')에 부착고정된 인너리드(13)(13')를 본딩하는 2차 본딩 공정으로 진행됨을 특징으로 하는 시트형 반도체 패키지의 제조방법.A bumping step of forming bumps 12 and 12 'on the semiconductor chip 11, an inner lead bonding step of fixing the inner leads 13 and 13' to the bumps 12 and 12 ', An encapsulation process of filling the epoxy 15 into a predetermined area including the bumps 12 and 12 ', and upper bent portions 17a and 17a' having a predetermined shape are formed to form a polyimide 16 or the like. The secondary bonding process of bonding the inner lead 13 and 13 'attached to the semiconductor chip 11 and the bumps 12 and 12' to the lead frames 17 and 17 'to which the adhesive is attached. A method of manufacturing a sheet-shaped semiconductor package, characterized in that the progress. 제 3 항에 있어서, 상기 2차 본딩공정시 리드 프레임(17)(17')을 히트 블럭(18)에 얹은 다음, 리드 프레임(17)(17')의 상부 절곡부(17a)(17a') 상면에 인너리드(13)(13')의 하면을 싱글 포인트 본딩으로 접착고정함을 특징으로 하는 시트형 반도체 패키지의 제조방법.4. The upper bending portion (17a) (17a ') of the lead frame (17) (17') after placing the lead frames (17) (17 ') on the heat block (18) during the secondary bonding process. A method of manufacturing a sheet-shaped semiconductor package, characterized in that the lower surface of the inner lead (13) (13 ') is fixed to the upper surface by single point bonding. IC칩(11)의 범프(12)(12')에 1-층 TAB 테이프의 인너리드(13)(13')가 각각 고정됨과 아울러 IC칩(11)의 상면에 범프(2)(2')를 포함하는 소정면적에 에폭시(15)가 형성되고, 상기 IC칩(11)의 하면에 상부 절곡부(17a)(17a')가 형성된 리드 프레임(17)(17')이 고정되며, 상기 리드 프레임(17)(17')의 상부 절곡부(17a)(17a')에 상기 인너리드(13)(13')가 고정된 것임을 특징으로 하는 시트형 반도체 패키지.Inner leads 13 and 13 'of the one-layer TAB tape are respectively fixed to the bumps 12 and 12' of the IC chip 11, and bumps 2 and 2 'are disposed on the upper surface of the IC chip 11, respectively. Epoxy (15) is formed in a predetermined area including a), and lead frames (17) and (17 ') formed with upper bent portions (17a) and (17a') are fixed to a lower surface of the IC chip (11). And the inner lead (13) (13 ') is fixed to the upper bent portion (17a) (17a') of the lead frame (17) (17 '). 제 5 항에 있어서, 상기 리드 프레임(17)(17')의 상면에 폴리이미드(16)가 도포되어 그 폴리이미드(16)에 IC칩(11)이 접착고정된 것임을 특징으로 하는 시트형 반도체 패키지.The sheet semiconductor package according to claim 5, wherein the polyimide (16) is coated on the upper surfaces of the lead frames (17) and (17 '), and the IC chip (11) is fixed to the polyimide (16). .
KR1019910007761A 1991-05-14 1991-05-14 Sheet type semiconductor package and manufacturing method thereof KR940007537B1 (en)

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