JPH04133341A - Semiconductor chip carrier - Google Patents
Semiconductor chip carrierInfo
- Publication number
- JPH04133341A JPH04133341A JP2255848A JP25584890A JPH04133341A JP H04133341 A JPH04133341 A JP H04133341A JP 2255848 A JP2255848 A JP 2255848A JP 25584890 A JP25584890 A JP 25584890A JP H04133341 A JPH04133341 A JP H04133341A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- semiconductor chip
- semiconductor mounting
- bonding
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000007747 plating Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
本発明は、ＰＧＡなと多層の回路構造を持つ半導体チッ
プキャリアに関するものである。The present invention relates to a semiconductor chip carrier having a multilayer circuit structure such as PGA.
樹脂積層板を基板とするプリント配線板をキャリア基板
１として用いた半導体チップキャリアが従来から提供さ
れている。このものは第４図のようにキャリア基板ｌの
上面の中央部に半導体搭載部２を設けると共にキャリア
基板１の背面がら突出するように多数の端子４，４・・
・を取着し、キャリア基板ｌの表面に外層の回路５を、
キャリア基板１の内部に内層の回路６をそれぞれ設けで
ある。これら回路５．６は端子４，４・・・に接続され
るものであるが、内層回路６はスルーホール１ｏを介し
て外層に設けた接続用回路１５に接続するようにしであ
る。また半導体搭載部２の周縁に沿って多数本のボンデ
ィングフィンガー３．３・・・が設けてあり、外層の各
回路５及び各接続用回路１５の一端がこのボンディング
フィンガー３．３・・・に接続しである。そして半導体
搭載部２にＩＣ等の半導体チップ７を搭載して、半導体
チップ７と各ボンディングフィンガー３．３・・・とに
金線などのワイヤー１４をボンディングすることによっ
て、半導体チップ７を外層回路５によって端子４に、あ
るいは接続用回路１５からスルーホール１０と内層回路
６を通じて端子４に、それぞれ電気的に接続するように
しである。2. Description of the Related Art A semiconductor chip carrier using a printed wiring board having a resin laminate as a carrier substrate 1 has been conventionally provided. As shown in FIG. 4, a semiconductor mounting portion 2 is provided at the center of the upper surface of the carrier board 1, and a large number of terminals 4, 4, .
・Attach the outer layer circuit 5 to the surface of the carrier board l,
Inner layer circuits 6 are provided inside the carrier substrate 1, respectively. These circuits 5, 6 are connected to the terminals 4, 4, . . . , and the inner layer circuit 6 is connected to a connecting circuit 15 provided on the outer layer via a through hole 1o. Also, a large number of bonding fingers 3.3... are provided along the periphery of the semiconductor mounting portion 2, and one end of each circuit 5 and each connection circuit 15 on the outer layer is connected to the bonding fingers 3.3... It is connected. Then, a semiconductor chip 7 such as an IC is mounted on the semiconductor mounting portion 2, and a wire 14 such as a gold wire is bonded to the semiconductor chip 7 and each bonding finger 3. 5 to the terminal 4, or from the connection circuit 15 to the terminal 4 through the through hole 10 and the inner layer circuit 6, respectively.
しかしこのものではボンディングフィンガー３を内層の
回路６に接続するためにキャリア基板１に多くの接続用
回路１５やスルーホールｌＯを設ける必要があり、半導
体の高密度化に伴うＩｌｏの増加に対して接続用回路１
５やスルーホールト０をキャリア基板１に設けるスペー
スを確保することができず、半導体の高密度化に対応す
ることが難しいという問題があった。またスルーホール
１０の箇所まで接続用回路１５を引き回して内層の回路
６に接続をおこなうことになるためにボンディングフィ
ンガー３から内層の回路６までの配線長が長くなり、半
導体の高速化に対応することが難しいという問題もあっ
た。
このために第５図に示すように、半導体搭載部２にメツ
キ層１６を設けてこのメツキ層１６を内層の回路６と導
通させ、メツキ層１６の上に実装される半導体チップ７
をメツキ層１６を介して内層回路６に接続させるように
することが検討されている。このものではスルーホール
１０や接続用回路１５の数を減らしたり不要にしたりす
ることが可能になる。しかしこのものでは半導体搭載部
２が内層回路６と同電位になるために、このような電位
では使用できない半導体チップ７の場合には採用するこ
とができないものであり、上記問題の有効な解決にはな
らない。
本発明は上記の点に鑑みて為されたものであり、半導体
の高密度及び高速化半導体に対応することが可能になる
半導体チップキャリアを提供することを目的とするもの
である。However, in this case, in order to connect the bonding finger 3 to the circuit 6 on the inner layer, it is necessary to provide many connection circuits 15 and through holes IO on the carrier substrate 1. Connection circuit 1
There was a problem in that it was not possible to secure space for providing the through holes 5 and 0 on the carrier substrate 1, and it was difficult to cope with the increase in the density of semiconductors. In addition, since the connection circuit 15 is routed to the through hole 10 and connected to the inner layer circuit 6, the wiring length from the bonding finger 3 to the inner layer circuit 6 becomes longer, which corresponds to higher speed semiconductors. There was also the problem that it was difficult to For this purpose, as shown in FIG. 5, a plating layer 16 is provided on the semiconductor mounting portion 2, and the plating layer 16 is electrically connected to the circuit 6 on the inner layer, and the semiconductor chip 7 is mounted on the plating layer 16.
It is being considered to connect the inner layer circuit 6 to the inner layer circuit 6 via the plating layer 16. With this structure, the number of through holes 10 and connection circuits 15 can be reduced or eliminated. However, in this case, since the semiconductor mounting portion 2 is at the same potential as the inner layer circuit 6, it cannot be adopted in the case of a semiconductor chip 7 that cannot be used at such a potential, and therefore it cannot be used as an effective solution to the above problem. Must not be. The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor chip carrier that can cope with high-density and high-speed semiconductors.
本発明は、キャリア基板１に形成される半導体搭載部２
の周縁に沿って多数本のボンディングフィンガー３，３
・・・を設けると共にキャリア基板１に取着した端子４
とボンディングフィンガー３とをキャリア基板１に形成
した外層の回路５あるいは内層の回路６を介して接続し
、半導体搭載部２に搭載された半導体チップ７と各ボン
ディングフィンガー３とを電気的に接続して形成される
半導体チップキャリアにおいて、半導体搭載部２の周縁
とボンディングフィンガー３との間においてキャリア基
板１の表面に形成されるスペース８に半導体搭載部２の
この周縁に沿う接続用回路９を設け、この接続用回路９
に複数本のボンディングフィンガー３を接続すると共に
内層の回路６と導通するようにキャリア基板１に設けた
スルーホール１０に接続用回路９を接続して成ることを
特徴とするものである。The present invention provides a semiconductor mounting portion 2 formed on a carrier substrate 1.
A large number of bonding fingers 3, 3 are placed along the periphery of the
... and attached to the carrier board 1.
and the bonding fingers 3 are connected via an outer layer circuit 5 or an inner layer circuit 6 formed on the carrier substrate 1, and the semiconductor chip 7 mounted on the semiconductor mounting section 2 and each bonding finger 3 are electrically connected. In the semiconductor chip carrier formed by the semiconductor chip carrier, a connection circuit 9 is provided along the periphery of the semiconductor mounting portion 2 in a space 8 formed on the surface of the carrier substrate 1 between the periphery of the semiconductor mounting portion 2 and the bonding finger 3. , this connection circuit 9
A plurality of bonding fingers 3 are connected to the carrier substrate 1, and a connecting circuit 9 is connected to a through hole 10 provided in the carrier substrate 1 so as to be electrically connected to the inner layer circuit 6.
本発明にあっては、半導体搭載部２の側縁とボンディン
グフィンガー３との間においてキャリア基板１の表面に
形成されるスペース８に半導体搭載部２のこの周縁に沿
う接続用回路９を設け、この接続用回路９に複数本のボ
ンディングフィンガー３を接続すると共に内層の回路６
と導通するようにキャリア基板ｌに設けたスルーホール
１ｏに接続用回路９を接続するようにしているために、
従来使用されない部分となっていた半導体搭載部２の周
縁とボンディングフィンガー３との間のスペース８を利
用して接続用回路９を形成することができ、しかも接続
用回路９には複数のボンディングフィンガー３が接続さ
れていてスル、−ホール１０の本数を少なくすることが
できる。またボンディングフィンガー３と接続用回路９
とは近接して配置されており、ボンディングフィンガー
３から内層の回路６への配線長が短くなる。In the present invention, a connection circuit 9 is provided along the periphery of the semiconductor mounting portion 2 in a space 8 formed on the surface of the carrier substrate 1 between the side edge of the semiconductor mounting portion 2 and the bonding finger 3, A plurality of bonding fingers 3 are connected to this connection circuit 9, and the inner layer circuit 6
Since the connection circuit 9 is connected to the through hole 1o provided in the carrier board l so as to be electrically conductive with the
The connection circuit 9 can be formed by using the space 8 between the periphery of the semiconductor mounting portion 2 and the bonding fingers 3, which was previously an unused portion. 3 are connected, and the number of holes 10 can be reduced. In addition, the bonding finger 3 and the connection circuit 9
The wiring length from the bonding finger 3 to the inner layer circuit 6 is shortened.
以下本発明を実施例によって詳述する。
第１図は本発明の一実施例を示すものであり、多層プリ
ント配線板で作成されるキャリア基板１の上面の中央部
には第１図（ａ）のように平面形状が四角形の半導体搭
載部２がキャビティとして凹設してあり、キャリア基板
１の下面にはビンで形成される多数の端子４，４・・・
が下方へ突出するように取着しである。またキャリア基
板１の表面には外層の回路５が、キャリア基板１の内部
には一層もしくは複数層の内層の回＃ｒ６がそれぞれ設
けである。これら回路５．６は端子４．４・・・に接続
されるように設けである。さらに半導体搭載部２の各端
辺に沿ってキャリア基板１の表面には多数本のボンディ
ングフィンガー３．３・・・が設けてあり、外層の各回
路５の一端はこのボンディングフィンガー３，３・・・
に接続しである。
また、半導体搭載部２の各端辺とボンディングフィンガ
ー３．３・・・を設けた部分との間は一般に何も設けら
れないスペース８くプルパックと通称される）となって
いるが、このスペース８を利用して半導体Ｍ−載部２の
各端縁と平行に沿うように接続用回路９，９・・・が設
けである。この接続用回路９には複数本のボンディング
フィンガー３．３・・・のうち、外層の回路５に接続さ
れていないボンディングフィンガー３ａが第１図（ｃ）
のように複数本づつ接続しである。さらに、半導体搭載
部２の周縁部分のうち半導体搭載部２角部に対応する部
分はボンディングフィンガー３．３・・・が形成されな
いスペース１７となっており、このスペース１７を利用
してキャリア基板１にスルーホール１０．１０・・・が
穿設してあり、この各スルーホール１０にそれぞれ接続
用回路９の一端を接続するようにしである。このスルー
ホール１０は内層の回路６に接続されるように設けられ
るものである。
スルーホール１０と接続用回路９や内層回路６との接続
は、スルーホール１０の内周にメツキ層を設けたり、第
１図（ｂ）のようにスルーホール１０内に導電性物質１
８を充填したりしておこなうことができる。
そして、半導体搭載部２にＩＣ等の半導体チップ７を搭
載し、半導体チップ７と各ボンディングフィンガー３．
３・・・どの間に金線などのワイヤー１４をボンディン
グすることによって、半導体チップ７を各ボンディング
フィンガー３．３・・・に接続するようにしである６従
って、半導体チップ７はボンディングフィンガー３から
外層回路５を介して端子４に接続されると共に、ボンデ
ィングフィンガー３ａから接続用回路９とスルーホール
ｌＯを介して内層用回路６を通じて端子４に電気的に接
続されることになる。この接続用回路９の表面には、ワ
イヤー１４との接触による短絡を防ぐために、絶縁物を
被覆しておくのが好ましい。
ここで、半導体チップ７において電源やアースの接続を
おこなう場合、半導体チップ７の電源用電極やアース用
電極は複数づつ設けられるが、キャリア基板１の上でこ
れら複数の電極を合流させる必要のあることが多い、半
導体チップ７のこのような複数の電源用電極やアース用
電極を接続用回路９に接続されたボンディングフィンガ
ー３ａ、３ａ・・・に接続するようにしているものであ
り、複数の電源用電極やアース用電極は複数のボンディ
ングフィンガー３ａ、３ａ・・・が−括して接続される
接続用回路９で合流され、内層の電源用の回路６やアー
ス用の回路６に接続することができることになる。この
ように半導体チップ７がら電源用やアース用の回路６に
接続するにあたって、接続用回路９はボンディングフィ
ンガー３ａの近傍に設けられているために、半導体チッ
プ７からボンディングフィンガー３ａ及び接続用回路９
を経た電源用やアース用の回路６までの配線長は短くな
り、半導体の高速化への対応に有利になるものである。
また、第２図に示すように、内層の回路６が複数層で形
成されている場合には、各層の回路６にスルーホール１
０によって接続用回路９を選択的に接続することができ
る。第２図の実施例ではスルーホール１０の内周にスル
ーホールメツキ１９を設けて、スルーホール１０と接続
用回路９や内層回路６との接続をおこなうようにしであ
る。
第３図は本発明の他の実施例を示すものであり、半導体
搭載部２の端辺とボンディングフィンガー３，３・・・
を設けた部分との間のスペース８に平行に配設した二本
（複数本）の接続用回路９を形成するようにしである。The present invention will be explained in detail below with reference to Examples. FIG. 1 shows an embodiment of the present invention, in which a semiconductor having a rectangular planar shape is mounted at the center of the upper surface of a carrier substrate 1 made of a multilayer printed wiring board, as shown in FIG. The portion 2 is recessed as a cavity, and the lower surface of the carrier substrate 1 has a large number of terminals 4, 4, .
It is attached so that it protrudes downward. Further, an outer layer circuit 5 is provided on the surface of the carrier substrate 1, and an inner layer circuit #r6 of one or more layers is provided inside the carrier substrate 1. These circuits 5.6 are provided to be connected to the terminals 4.4... Further, a large number of bonding fingers 3,3... are provided on the surface of the carrier substrate 1 along each edge of the semiconductor mounting portion 2, and one end of each circuit 5 on the outer layer is connected to the bonding fingers 3,3...・・・
It is connected to. Additionally, there is generally a space (commonly known as a pull pack) in which nothing is provided between each edge of the semiconductor mounting portion 2 and the portion where the bonding fingers 3, 3, etc. are provided. Connecting circuits 9, 9, . . . are provided along parallel to each edge of the semiconductor M-mounting portion 2 using the connecting circuits 8. Among the plurality of bonding fingers 3.3... in this connection circuit 9, the bonding finger 3a that is not connected to the outer layer circuit 5 is shown in FIG. 1(c).
Connect multiple wires at a time as shown in the figure below. Further, a portion of the peripheral edge portion of the semiconductor mounting portion 2 corresponding to the corner portion of the semiconductor mounting portion 2 is a space 17 in which the bonding fingers 3, 3, . . . Through holes 10, 10, . This through hole 10 is provided so as to be connected to the circuit 6 on the inner layer. The connection between the through hole 10 and the connection circuit 9 or the inner layer circuit 6 can be achieved by providing a plating layer on the inner periphery of the through hole 10 or by applying a conductive material 1 inside the through hole 10 as shown in FIG. 1(b).
8 can be filled. Then, a semiconductor chip 7 such as an IC is mounted on the semiconductor mounting portion 2, and the semiconductor chip 7 and each bonding finger 3.
3. The semiconductor chip 7 is connected to each bonding finger 3.3 by bonding a wire 14 such as a gold wire between the bonding fingers 3.6. Therefore, the semiconductor chip 7 is connected to each bonding finger 3. It is connected to the terminal 4 via the outer layer circuit 5, and is electrically connected to the terminal 4 from the bonding finger 3a through the inner layer circuit 6 via the connection circuit 9 and the through hole IO. The surface of the connection circuit 9 is preferably coated with an insulator to prevent short circuits due to contact with the wire 14. Here, when connecting the power supply and ground to the semiconductor chip 7, a plurality of power supply electrodes and a plurality of ground electrodes are provided for the semiconductor chip 7, but it is necessary to merge these plurality of electrodes on the carrier substrate 1. In many cases, a plurality of such power supply electrodes and ground electrodes of the semiconductor chip 7 are connected to the bonding fingers 3a, 3a, . . . connected to the connection circuit 9. The power supply electrode and the ground electrode are joined together at a connection circuit 9 to which a plurality of bonding fingers 3a, 3a, . . . are connected together, and connected to the power supply circuit 6 and the ground circuit 6 on the inner layer. You will be able to do that. In this way, when connecting the semiconductor chip 7 to the power supply or grounding circuit 6, since the connection circuit 9 is provided near the bonding finger 3a, the connection circuit 9 is connected from the semiconductor chip 7 to the bonding finger 3a and the connection circuit 9.
The length of the wiring from the circuit 6 to the power supply and ground circuit 6 is shortened, which is advantageous in responding to higher speeds of semiconductors. In addition, as shown in FIG. 2, when the inner layer circuit 6 is formed of multiple layers, a through hole 1 is provided in the circuit 6 of each layer.
0 allows the connection circuit 9 to be selectively connected. In the embodiment shown in FIG. 2, a through-hole plating 19 is provided on the inner periphery of the through-hole 10 to connect the through-hole 10 to the connection circuit 9 and the inner layer circuit 6. FIG. 3 shows another embodiment of the present invention, in which the edge of the semiconductor mounting portion 2 and bonding fingers 3, 3, . . .
Two (plural) connection circuits 9 are formed in parallel to each other in the space 8 between the connecting portion and the connecting portion.
上述のように本発明にあっては、半導体搭載部の周縁と
ボンディングフィンガーとの間においてキャリア基板の
表面に形成されるスペースに半導体搭載部のこの周縁に
沿う接続用回路を設け、この接続用回路に複数本のボン
ディングフィンガーを接続すると共に内層の回路と導通
するようにキャリア基板に設けたスルーホールに接続用
回路を接続するようにしたので、従来使用されない部分
となっていた半導体搭載部の周縁とボンディングフィン
ガーとの間のプルパックと称されるスペースを利用して
接続用回路を形成することができ、端子の数が増えても
接続用回路を形成するためのスペースを確保することが
できるものであり、しかも接続用回路には複数のボンデ
ィングフィンガーが接続されていてボンディングフィン
ガーを一括してスルーホールに接続することができ、ス
ルーホールの本数を少なくすることができるものあり、
この結果半導体の高密度化によるＩｌｏの増加に容易に
対応することができるようになったらのである。また接
続用回路はボンディングフィンガーと近接して配置させ
ることができるものであり、ボンディングフィンガーか
ら接続用回路を介して内層の回路に至る配線長を短くな
すことが可能になり、半導体の高速化に容易に対応する
ことが可能になるものである。As described above, in the present invention, a connection circuit is provided along the periphery of the semiconductor mounting part in the space formed on the surface of the carrier substrate between the periphery of the semiconductor mounting part and the bonding finger, and the connection circuit is provided along the periphery of the semiconductor mounting part and the bonding finger. In addition to connecting multiple bonding fingers to the circuit, the connection circuit is connected to a through hole provided in the carrier board so as to be electrically conductive with the inner layer circuit, so the semiconductor mounting area, which was previously an unused part, can be used. A connection circuit can be formed using the space called a pull pack between the periphery and the bonding finger, and even if the number of terminals increases, the space for forming a connection circuit can be secured. In addition, the connection circuit has multiple bonding fingers connected to it, and the bonding fingers can be connected to the through-holes all at once, reducing the number of through-holes.
As a result, it has become possible to easily cope with the increase in Ilo due to the increased density of semiconductors. In addition, the connection circuit can be placed close to the bonding finger, making it possible to shorten the wiring length from the bonding finger to the inner layer circuit via the connection circuit, which contributes to higher speed semiconductors. This makes it possible to respond easily.
第１図（ａ）（ｂ）（ｃ）は本発明の一実施例の平面図
と拡大した断面図と一部の拡大した平面図、第２図は同
上の他の実施例の断面図、第３図（ａ）（ｂ）は同上の
さらに他の実施例の平面図と断面図、第４図（ａ＞（ｂ
）は従来例の平面図と拡大した断面図、第５図（ａ）（
ｂ）は他の従来例の平面図と拡大した断面図である。
１はキャリア基板、２は半導体搭載部、３はボンディン
グフィンガー、４は端子、５は外層の回路、６は内層の
回路、７は半導体チップ、８はスペース、９は接続用回
路、１０はスルーホールである。1(a), (b), and (c) are a plan view, an enlarged sectional view, and a partially enlarged plan view of one embodiment of the present invention; FIG. 2 is a sectional view of another embodiment of the same; 3(a) and 3(b) are a plan view and a sectional view of still another embodiment of the same as above, and FIG. 4(a>(b)
) is a plan view and an enlarged sectional view of the conventional example, and Fig. 5(a) (
b) is a plan view and an enlarged sectional view of another conventional example. 1 is a carrier board, 2 is a semiconductor mounting part, 3 is a bonding finger, 4 is a terminal, 5 is an outer layer circuit, 6 is an inner layer circuit, 7 is a semiconductor chip, 8 is a space, 9 is a connection circuit, 10 is a through hole It is a hall.
Claims (1)
沿って多数本のボンディングフィンガーを設けると共に
キャリア基板に取着した端子とボンディングフィンガー
とをキャリア基板に形成した外層の回路あるいは内層の
回路を介して接続し半導体搭載部に搭載された半導体チ
ップと各ボンディングフィンガーとを電気的に接続して
形成される半導体チップキャリアにおいて、半導体搭載
部の周縁とボンディングフィンガーとの間においてキャ
リア基板の表面に形成されるスペースに半導体搭載部の
この周縁に沿う接続用回路を設け、この接続用回路に複
数本のボンディングフィンガーを接続すると共に内層の
回路と導通するようにキャリア基板に設けたスルーホー
ルに接続用回路を接続して成ることを特徴とする半導体
チップキャリア。(1) A large number of bonding fingers are provided along the periphery of the semiconductor mounting portion formed on the carrier substrate, and the terminals attached to the carrier substrate and the bonding fingers are connected to an outer layer circuit or an inner layer circuit formed on the carrier substrate. In a semiconductor chip carrier that is formed by electrically connecting a semiconductor chip mounted on a semiconductor mounting part and each bonding finger by connecting the semiconductor chip mounted on the semiconductor mounting part through the bonding finger, the surface of the carrier substrate is A connection circuit is provided along this periphery of the semiconductor mounting part in the space formed, and multiple bonding fingers are connected to this connection circuit and connected to through holes provided in the carrier board so as to be electrically connected to the inner layer circuit. A semiconductor chip carrier characterized in that it is formed by connecting a circuit for use.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2255848A JPH06103721B2 (en) | 1990-09-25 | 1990-09-25 | Semiconductor chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2255848A JPH06103721B2 (en) | 1990-09-25 | 1990-09-25 | Semiconductor chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04133341A true JPH04133341A (en) | 1992-05-07 |
| JPH06103721B2 JPH06103721B2 (en) | 1994-12-14 |
Family
ID=17284435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2255848A Expired - Lifetime JPH06103721B2 (en) | 1990-09-25 | 1990-09-25 | Semiconductor chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06103721B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002080268A1 (en) * | 2001-03-30 | 2002-10-10 | Infineon Technologies Ag | A substrate for mounting a semiconductor chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57107059A (en) * | 1980-12-25 | 1982-07-03 | Fujitsu Ltd | Semiconductor package |
| JPS596563A (en) * | 1982-07-05 | 1984-01-13 | Nec Corp | Integrated circuit device |
| JPS5972749A (en) * | 1982-10-19 | 1984-04-24 | Nec Corp | Semiconductor device |
| JPS6020524A (en) * | 1983-07-14 | 1985-02-01 | Toshiba Corp | Semiconductor integrated circuit device |
| JPH01111342A (en) * | 1987-10-26 | 1989-04-28 | Nec Corp | Package for integrated circuit |
| JPH0488664A (en) * | 1990-07-31 | 1992-03-23 | Ibiden Co Ltd | Lead frame provided with insulating base material |
| JPH04250641A (en) * | 1990-06-22 | 1992-09-07 | Digital Equip Corp <Dec> | Semiconductor package by metal and its manufacture |
-
1990
- 1990-09-25 JP JP2255848A patent/JPH06103721B2/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57107059A (en) * | 1980-12-25 | 1982-07-03 | Fujitsu Ltd | Semiconductor package |
| JPS596563A (en) * | 1982-07-05 | 1984-01-13 | Nec Corp | Integrated circuit device |
| JPS5972749A (en) * | 1982-10-19 | 1984-04-24 | Nec Corp | Semiconductor device |
| JPS6020524A (en) * | 1983-07-14 | 1985-02-01 | Toshiba Corp | Semiconductor integrated circuit device |
| JPH01111342A (en) * | 1987-10-26 | 1989-04-28 | Nec Corp | Package for integrated circuit |
| JPH04250641A (en) * | 1990-06-22 | 1992-09-07 | Digital Equip Corp <Dec> | Semiconductor package by metal and its manufacture |
| JPH0488664A (en) * | 1990-07-31 | 1992-03-23 | Ibiden Co Ltd | Lead frame provided with insulating base material |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002080268A1 (en) * | 2001-03-30 | 2002-10-10 | Infineon Technologies Ag | A substrate for mounting a semiconductor chip |
| US7294853B2 (en) | 2001-03-30 | 2007-11-13 | Infineon Technologies, A.G. | Substrate for mounting a semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06103721B2 (en) | 1994-12-14 |
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