JPH0799767B2 - Chip carrier IC device - Google Patents
Chip carrier IC deviceInfo
- Publication number
- JPH0799767B2 JPH0799767B2 JP61311020A JP31102086A JPH0799767B2 JP H0799767 B2 JPH0799767 B2 JP H0799767B2 JP 61311020 A JP61311020 A JP 61311020A JP 31102086 A JP31102086 A JP 31102086A JP H0799767 B2 JPH0799767 B2 JP H0799767B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- external connection
- circuit board
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、セラミックキャリアにICチップを装着すると
ともに、このセラミックキャリアに設けられた外部接続
電極にて回路基板に接続するように構成されたチップキ
ャリアIC装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier configured to mount an IC chip on a ceramic carrier and connect the IC chip to a circuit board by an external connection electrode provided on the ceramic carrier. It relates to IC devices.
従来の技術 従来のチップキャリアIC装置11は、第4図に示すように
方形平板状のセラミックキャリア12の中央部にICチップ
13が装着され、このICチップ13とセラミックキャリア12
に形成されたパッドとが金ワイヤ14にてワイヤボンディ
ングされて成り、前記セラミックキャリア12にはその四
周縁に前記パッドと配線(図示せず)にて接続された外
部接続電極15が配設されている。そして、このチップキ
ャリアIC装置11を回路基板16上に装着するとともに前記
外部接続電極15を回路基板16の配線17に接続するように
構成されている。2. Related Art As shown in FIG. 4, a conventional chip carrier IC device 11 has an IC chip in the center of a rectangular flat ceramic carrier 12.
13 is mounted, this IC chip 13 and ceramic carrier 12
Is formed by wire bonding with a gold wire 14 to the pad formed on the ceramic carrier 12, and the ceramic carrier 12 is provided with external connection electrodes 15 connected to the pad by wiring (not shown) on the four peripheral edges thereof. ing. The chip carrier IC device 11 is mounted on the circuit board 16 and the external connection electrodes 15 are connected to the wirings 17 of the circuit board 16.
発明が解決しようとする問題点 ところが、方形平板状のセラミックキャリア12の四周縁
に外部接続電極が配設されているので、外部接続電極の
数が多いと、セラミックキャリア12の一辺の長さが長く
なってその平面積が大きくなり、回路基板16に対する実
装密度が低くなり、又セラミックキャリア12と回路基板
16の熱膨張差の影響を受け易く、外部接続電極15と回路
基板16の配線17との接続部に接続不良を生ずる虞れがあ
るという問題があった。Problems to be Solved by the Invention However, since the external connection electrodes are arranged at the four peripheral edges of the rectangular flat ceramic carrier 12, if the number of external connection electrodes is large, the length of one side of the ceramic carrier 12 is reduced. The longer the flat area, the smaller the mounting density on the circuit board 16, and the ceramic carrier 12 and the circuit board.
There is a problem that it is easily affected by the difference in thermal expansion of 16 and a connection failure may occur in the connection portion between the external connection electrode 15 and the wiring 17 of the circuit board 16.
本発明は上記従来の問題点に鑑み、回路基板に対する実
装密度が向上するとともに熱膨張差の影響も受け難いチ
ップキャリアIC装置を提供することを目的とする。In view of the above conventional problems, it is an object of the present invention to provide a chip carrier IC device which is improved in mounting density on a circuit board and is less susceptible to a thermal expansion difference.
問題点を解決するための手段 本発明は上記目的を達成するため、各辺に複数の接続端
子を有するICチップと、このICチップを平面上に装着
し、ICチップの第一辺の複数の接続端子と各々導通可能
な外部接続電極を、積層方向の一方の側面に設けた第1
基板と、前記ICチップの第二辺の複数の接続端子と前記
第1の基板に形成されたスルーホールを介して導通可能
な外部接続電極を、積層方向の一方の側面に設けた第2
基板と、前記第1基板及び第2基板を複数積層し、積層
方向の一方の側面に配置された各基板の外部接続電極と
導通可能な回路基板とからなることを特徴とする 作用 本発明は上記構成を有しているので、多層基板の積層方
向に沿う1つの側面にICチップの接続端子に接続された
外部接続電極が配設されており、この多層基板の前記1
つの側面を回路基板に接合して各外部接続電極を回路基
板の配線に接続することによって、チップキャリアIC装
置を装着することができる。そして、多層基板の1つの
側面にすべての外部接続電極が形成されているので、チ
ップキャリアICの回路基板に対する接合面積は小さくて
済み、チップキャリアIC装置の実装密度が高くなる。
又、多層基板を構成する基板は、ICチップを装着できか
つ1グループの接続端子を各基板の一側端面の外部接続
電極に接続できるだけの高さを有するだけでよいので、
高さ方向のスペースが極端に大きくなるということもな
く、全体としてコンパクトに構成できる。又、回路基板
との接合面積が小さくなるので熱膨張差による影響も受
け難くなるのである。Means for Solving the Problems In order to achieve the above object, the present invention has an IC chip having a plurality of connection terminals on each side, and the IC chip is mounted on a plane, and a plurality of IC chips on the first side of the IC chip are mounted. The first external connection electrode, which is electrically connectable to the connection terminal, is provided on one side surface in the stacking direction.
A substrate, a plurality of connection terminals on the second side of the IC chip, and an external connection electrode capable of conducting through a through hole formed in the first substrate, provided on one side surface in the stacking direction.
The present invention is characterized by comprising a substrate and a plurality of the first substrate and the second substrate, and a circuit substrate which is electrically connected to the external connection electrode of each substrate arranged on one side surface in the laminating direction. Since it has the above-mentioned structure, the external connection electrode connected to the connection terminal of the IC chip is disposed on one side surface along the stacking direction of the multilayer board.
The chip carrier IC device can be mounted by joining one side surface to the circuit board and connecting each external connection electrode to the wiring of the circuit board. Further, since all the external connection electrodes are formed on one side surface of the multilayer substrate, the bonding area of the chip carrier IC with respect to the circuit substrate can be small, and the packaging density of the chip carrier IC device can be increased.
In addition, since the substrates constituting the multi-layer substrate only need to have a height to which an IC chip can be mounted and one group of connection terminals can be connected to an external connection electrode on one end face of each substrate,
The space in the height direction does not become extremely large, and the overall structure can be made compact. Further, since the bonding area with the circuit board becomes smaller, it is less likely to be affected by the difference in thermal expansion.
実施例 以下、本発明の一実施例を第1図〜第3図を参照しなが
ら説明する。Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
第1図において、1は、チップキャリアIC装置であっ
て、4枚の基板2a〜2dが積層された多層基板3において
1層目の基板2aの中央部にICチップ4が装着されてい
る。このICチップ4の4周に形成された多数の接続端子
はそれぞれ金ワイヤ5を用いたワイヤボンディングにて
前記基板2aに形成されたパッド(図示せず)に接続され
ている。これらパッドはICチップ4の四辺に対応してそ
の周囲に配設されており、その内のICチップ4の一辺に
対応するパッドはこの基板2aに形成された配線6を介し
てこの基板2aの一側端面に形成された外部接続電極7aに
接続されている。又、他の各辺に対応するパッドはそれ
ぞれ2層目〜4層目の基板2b〜2dに同様に形成された配
線(図示せず)に、各基板2a〜2cを貫通して形成された
スルーホールを介して接続され、かつ2層目〜4層目の
基板2b〜2dの配線はそれぞれの基板の一側端面に形成さ
れた外部接続電極7b〜7dに接続されている。前記各基板
2a〜2dの一側端面は多層基板3の積層方向の一側面3aを
構成するものであり、かつ前記外部接続電極7a〜7dは、
第2図に示すように、この一側面3a上で互いに短絡しな
いように千鳥状に配置されている。In FIG. 1, reference numeral 1 is a chip carrier IC device in which an IC chip 4 is mounted on the central portion of the first-layer substrate 2a in a multilayer substrate 3 in which four substrates 2a to 2d are stacked. A large number of connection terminals formed on the four circumferences of the IC chip 4 are connected to pads (not shown) formed on the substrate 2a by wire bonding using gold wires 5, respectively. These pads are arranged around the four sides of the IC chip 4, and the pads corresponding to one side of the IC chip 4 in the pads are provided on the substrate 2a via the wiring 6 formed on the substrate 2a. It is connected to the external connection electrode 7a formed on one end face. The pads corresponding to the other sides are formed by passing through the respective boards 2a to 2c to the wirings (not shown) similarly formed on the second to fourth layer boards 2b to 2d. The wirings of the second to fourth layers of the substrates 2b to 2d, which are connected through the through holes, are connected to the external connection electrodes 7b to 7d formed on one end surface of each substrate. Each substrate
One end surface of 2a to 2d constitutes one side surface 3a of the multilayer substrate 3 in the stacking direction, and the external connection electrodes 7a to 7d are
As shown in FIG. 2, the one side surfaces 3a are arranged in a staggered manner so as not to short-circuit with each other.
このように多層基板3にICチップ4が装着されかつこの
多層基板3の積層方向に沿う一側面3aに外部接続電極7a
〜7dが形成されたチップキャリアIC装置1は、第3図に
示すように、前記多層基板3の一側面3aを接合面として
回路基板8上に装着固定され、この一側面3aに形成され
た各外部接続電極7a〜7dが回路基板8の配線(図示せ
ず)と接続される。その際、多層基板3の積層方向に沿
う一側面3aにすべての外部接続電極7a〜7dが形成されて
いるので、チップキャリアIC装置1の回路基板8に対す
る接合面積は小さく、チップキャリアIC装置1の実装密
度を高くすることができるのである。又、各基板2a〜2d
は、ICチップ4を装着できかつその接続端子を各基板2a
〜2dの一側端面の外部接続電極7a〜7dに接続する配線を
形成できるだけの高さがあればよいので、高さ方向のス
ペースも極端に大きくなるということもなく、全体とし
てコンパクトに構成できる。又、回路基板8との接合面
積が小さくなるので熱膨張差による影響も受け難いので
ある。In this way, the IC chip 4 is mounted on the multilayer substrate 3 and the external connection electrode 7a is formed on one side surface 3a along the stacking direction of the multilayer substrate 3.
As shown in FIG. 3, the chip carrier IC device 1 on which ~ 7d is formed is mounted and fixed on the circuit board 8 with one side surface 3a of the multilayer substrate 3 as a joint surface, and is formed on this one side surface 3a. The external connection electrodes 7a to 7d are connected to the wiring (not shown) of the circuit board 8. At that time, since all the external connection electrodes 7a to 7d are formed on the one side surface 3a along the stacking direction of the multilayer substrate 3, the bonding area of the chip carrier IC device 1 to the circuit board 8 is small and the chip carrier IC device 1 is small. The packaging density of can be increased. In addition, each board 2a-2d
Can mount the IC chip 4 and connect its connection terminals to each board 2a.
Since it is sufficient that the wiring for connecting to the external connection electrodes 7a to 7d on one end face of ~ 2d is formed, the space in the height direction does not become extremely large, and the overall structure can be made compact. . Further, since the bonding area with the circuit board 8 is small, it is not easily affected by the difference in thermal expansion.
発明の効果 本発明のチップキャリアIC装置によれば、以上のように
多層基板の積層方向に沿う1つの側面にすべての外部接
続電極が形成されているので、チップキャリアIC装置の
回路基板に対する接合面積が小さくて済み、チップキャ
リアIC装置の実装密度が高くなる。また、多層基板を構
成する基板はICを装着できかつその接続端子と前記外部
接続電極を接続できるだけの高さがあればよいので、高
さ方向のスペースも比較的小さく、全体としてコンパク
トに構成できる。又、回路基板との接合面積が小さくな
るので熱膨張差による影響も受け難くなる等、大なる効
果が得られる。EFFECTS OF THE INVENTION According to the chip carrier IC device of the present invention, since all the external connection electrodes are formed on one side surface along the stacking direction of the multilayer substrate as described above, the chip carrier IC device is bonded to the circuit board. The area is small and the packaging density of the chip carrier IC device is high. In addition, since the substrate that constitutes the multilayer substrate only needs to have a height to which the IC can be mounted and the connection terminal and the external connection electrode can be connected, the space in the height direction is relatively small and the overall structure can be made compact. . Further, since the bonding area with the circuit board is reduced, it is less likely to be affected by the difference in thermal expansion, and other great effects can be obtained.
第1図〜第3図は本発明の一実施例を示し、第1図はチ
ップキャリアIC装置の斜視図、第2図は第1図の底面
図、第3図はチップキャリアIC装置を回路基板に装着し
た状態の概略斜視図、第4図は従来例の斜視図である。 1……チップキャリアIC装置 2a〜2d……基板 3……多層基板 4……ICチップ 7a〜7d……外部接続電極 8……回路基板。1 to 3 show an embodiment of the present invention. FIG. 1 is a perspective view of a chip carrier IC device, FIG. 2 is a bottom view of FIG. 1, and FIG. 3 is a circuit diagram of the chip carrier IC device. FIG. 4 is a schematic perspective view of a state where it is mounted on a substrate, and FIG. 4 is a perspective view of a conventional example. 1 ... Chip carrier IC device 2a-2d ... Substrate 3 ... Multilayer substrate 4 ... IC chips 7a-7d ... External connection electrode 8 ... Circuit board.
Claims (1)
と、このICチップを平面上に装着し、ICチップの第一辺
の複数の接続端子と各々導通可能な外部接続電極を、積
層方向の一方の側面に設けた第1基板と、前記ICチップ
の第二辺の複数の接続端子と前記第1基板に形成された
スルーホールを介して導通可能な外部接続電極を、積層
方向の一方の側面に設けた第2基板と、前記第1基板及
び第2基板を複数積層し、積層方向の一方の側面に配置
された各基板の外部接続電極と導通可能な回路基板とか
らなることを特徴とするチップキャリアIC装置。1. An IC chip having a plurality of connection terminals on each side, and an external connection electrode which is mounted on a flat surface and is electrically conductive with each of the plurality of connection terminals on the first side of the IC chip. A first substrate provided on one side surface in the stacking direction, a plurality of connection terminals on the second side of the IC chip, and an external connection electrode capable of conducting through a through hole formed in the first substrate, in the stacking direction. A second substrate provided on one side surface, and a circuit board formed by laminating a plurality of the first substrate and the second substrate and electrically connected to an external connection electrode of each substrate arranged on one side surface in the laminating direction. Chip carrier IC device characterized by.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61311020A JPH0799767B2 (en) | 1986-12-29 | 1986-12-29 | Chip carrier IC device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61311020A JPH0799767B2 (en) | 1986-12-29 | 1986-12-29 | Chip carrier IC device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63168040A JPS63168040A (en) | 1988-07-12 |
JPH0799767B2 true JPH0799767B2 (en) | 1995-10-25 |
Family
ID=18012150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61311020A Expired - Fee Related JPH0799767B2 (en) | 1986-12-29 | 1986-12-29 | Chip carrier IC device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0799767B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0485825U (en) * | 1990-11-28 | 1992-07-27 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS601848A (en) * | 1983-05-25 | 1985-01-08 | カボット・テクニカル・セラミックス・インコ−ポレ−テッド | Substrate for ic device package and method of producing same |
JPS63141352A (en) * | 1986-12-03 | 1988-06-13 | Nec Corp | Suface-packaged integrated circuit module |
-
1986
- 1986-12-29 JP JP61311020A patent/JPH0799767B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPS63168040A (en) | 1988-07-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |