JPH08316636A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08316636A
JPH08316636A JP11616695A JP11616695A JPH08316636A JP H08316636 A JPH08316636 A JP H08316636A JP 11616695 A JP11616695 A JP 11616695A JP 11616695 A JP11616695 A JP 11616695A JP H08316636 A JPH08316636 A JP H08316636A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor
semiconductor element
semiconductor device
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11616695A
Other languages
Japanese (ja)
Other versions
JP3838524B2 (en
Inventor
Yasuto Isozaki
康人 礒崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11616695A priority Critical patent/JP3838524B2/en
Publication of JPH08316636A publication Critical patent/JPH08316636A/en
Application granted granted Critical
Publication of JP3838524B2 publication Critical patent/JP3838524B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To provide a semiconductor device which can be mounted in a small mounting area on a mounting board without giving any damage to the semiconductor element. CONSTITUTION: A semiconductor carrier 3 is folded and a semiconductor element 1 is put between the two parts of the folded semiconductor carrier 3. A semiconductor electrode 2 of the semiconductor element 1 is directly junctioned to a connecting electrode 4 formed on a first major surface of the semiconductor carrier 3. An external electrode (a) 6 is formed on the surface, which is the second major surface of the semiconductor carrier 3, facing in the same direction of an electrode forming surface of the semiconductor 1. An external electrode (b) 7 is formed on the surface facing in the same direction of the rear of the electrode forming surface of the semiconductor 1. These external electrodes (a) 6 and (b) 7 are electrically connected with the connecting electrode 4 by conductive wire and via formed in the semiconductor carrier 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特
に、半導体素子の保護と,半導体素子と外部装置との電
気的接続を行う半導体素子保護用部材についての改良技
術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improved technique for a semiconductor element protecting member for protecting a semiconductor element and electrically connecting the semiconductor element and an external device.

【0002】[0002]

【従来の技術】従来、半導体素子は外部装置(半導体素
子,及び半導体素子以外のコンデンサ,抵抗,インダク
タ等の電子部品を含む。)との電気的接続を行うため
に、例えばQFPパッケージ,PGAパッケージのよう
なパッケージに収納して実装基板上に実装する、あるい
はフリップチップ方式のように半導体素子を直接実装基
板上に実装することが行われていた。
2. Description of the Related Art Conventionally, for example, a QFP package or a PGA package is used to electrically connect a semiconductor element to an external device (including a semiconductor element and electronic parts such as a capacitor, a resistor, an inductor other than the semiconductor element). It has been performed that the semiconductor device is mounted in such a package and mounted on a mounting substrate, or the semiconductor element is directly mounted on the mounting substrate like a flip chip method.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、半導体
素子をパッケージに収納して実装する場合、パッケージ
は半導体素子とパッケージとの電気的および機械的接続
を行うための接続部や、パッケージと外部装置との接続
を行うための接続端子(リード)を持つため、半導体素
子に比してその全体の大きさが大きくなり、その結果、
実装面積(すなわち、実装基板上でのパッケージが要す
る面積)が、非常に大きくなってしまうという問題点が
あった。また、パッケージは高価であり、コストがかさ
むという問題点もあった。一方、フリップチップ方式の
ように半導体素子を直接基板上に実装する方法では、半
導体素子の面積とほぼ同等な実装面積で基板に実装でき
るが、半導体素子を直接ハンドリングするため、実装作
業中に半導体素子に損傷を与えてしまうことがあるとい
う問題点があった。さらに、両者の方法とも半導体素子
に電気的に接続すべき外部装置の数が多くなると、実装
基板上の実装部品(半導体素子,外部装置)を平面的に
しか実装できないため、実装部品の数に応じて得られる
装置(混成回路装置)の占有面積が大きくなってしまう
という問題点があった。
However, when the semiconductor element is housed and mounted in the package, the package is provided with a connecting portion for electrically and mechanically connecting the semiconductor element and the package, and the package and the external device. Since it has connection terminals (leads) for making connections, its overall size is larger than that of semiconductor elements, and as a result,
There is a problem that the mounting area (that is, the area required for the package on the mounting board) becomes extremely large. In addition, the package is expensive and the cost is high. On the other hand, in the method of directly mounting the semiconductor element on the substrate such as the flip chip method, it is possible to mount the semiconductor element on the substrate with a mounting area almost equal to the area of the semiconductor element. There is a problem that the element may be damaged. Furthermore, in both methods, when the number of external devices to be electrically connected to the semiconductor element increases, the mounting components (semiconductor element, external device) on the mounting board can be mounted only in a planar manner, so that the number of mounting components is reduced. There is a problem that the occupied area of the device (mixed circuit device) obtained accordingly increases.

【0004】本発明は上記のような問題点を解消するた
めになされたものであり、半導体素子に損傷を与えるこ
となく、しかも小さい実装面積にて実装基板に実装でき
る半導体装置を提供することを目的とする。
The present invention has been made to solve the above problems, and it is an object of the present invention to provide a semiconductor device which can be mounted on a mounting board without damaging a semiconductor element and with a small mounting area. To aim.

【0005】[0005]

【課題を解決するための手段】本発明にかかる半導体装
置は、半導体素子と、折り曲げ可能な絶縁性基板材料の
第1の主面に第1の電極が形成され,第2の主面に前記
第1の電極に電気的に接続された第2の電極が形成され
てなる半導体素子保護用部材とを有し、前記絶縁性基板
材料をその前記第1の主面に前記半導体素子の電極形成
面に対向する第1の領域と,前記半導体素子の電極形成
面の裏側面に対向する第2の領域とが形成されるよう折
り曲げて、前記第1の電極を前記半導体素子の電極に直
接接続し、前記第2の電極を外部との電気的接続を行う
ための電極にしたものである。
In a semiconductor device according to the present invention, a semiconductor element and a first main surface of a bendable insulating substrate material are formed with a first electrode, and a second main surface is formed with the first electrode. A semiconductor element protection member formed by forming a second electrode electrically connected to the first electrode, and forming the electrode of the semiconductor element on the first main surface of the insulating substrate material. The first electrode is directly connected to the electrode of the semiconductor element by bending so as to form a first area facing the surface and a second area facing the back surface of the electrode formation surface of the semiconductor element. The second electrode is used as an electrode for electrical connection with the outside.

【0006】前記構成においては、前記第2の電極が、
前記第2の主面におけるその前記半導体素子の電極形成
面に対しての配置関係が異なる2つ以上の領域に設けら
れていることが好ましい。
In the above structure, the second electrode is
It is preferable that the second main surface is provided in two or more regions having different arrangement relations with respect to the electrode formation surface of the semiconductor element.

【0007】前記構成においては、前記第2の電極が、
前記第2の主面における前記半導体素子の電極形成面と
同一方向を向く第1の領域と、前記半導体素子の電極形
成面の裏側面と同一方向を向く第2の領域とにそれぞれ
設けられていることが好ましい。
In the above structure, the second electrode is
It is provided in each of a first region of the second main surface that faces the same direction as the electrode formation surface of the semiconductor element and a second region that faces the same direction as the back side surface of the electrode formation surface of the semiconductor device. Is preferred.

【0008】前記構成においては、前記折り曲げ可能な
絶縁性基板材料がフレキシブル樹脂基板であることが好
ましい。前記フレキシブル樹脂基板としては例えばポリ
イミド樹脂基板を用いる。
In the above structure, it is preferable that the foldable insulating substrate material is a flexible resin substrate. A polyimide resin substrate, for example, is used as the flexible resin substrate.

【0009】前記構成においては、前記折り曲げ可能な
絶縁性基板材料が樹脂含浸有機質不織布材からなる基板
であり、前記半導体素子保護用部材がこの樹脂含浸有機
質不織布材からなる基板を用いて構成された両面または
多層プリント配線板であることが好ましい。前記樹脂含
浸有機質不織布材からなる基板としては例えばエポキシ
樹脂またはポリイミド樹脂含浸のアラミド繊維からなる
シート基板,フェノール樹脂含浸の紙からなるシート基
板等を用いることができる。
In the above structure, the foldable insulating substrate material is a substrate made of a resin-impregnated organic nonwoven fabric material, and the semiconductor element protecting member is made of a substrate made of the resin-impregnated organic nonwoven fabric material. It is preferably a double-sided or multilayer printed wiring board. As the substrate made of the resin-impregnated organic nonwoven fabric material, for example, a sheet substrate made of aramid fiber impregnated with epoxy resin or polyimide resin, a sheet substrate made of paper impregnated with phenol resin, or the like can be used.

【0010】前記構成においては、前記半導体素子と前
記半導体素子保護用部材との間の空間および前記半導体
素子の周辺の空間に絶縁物が充填されていることが好ま
しい。前記絶縁物としては例えばエポキシ樹脂,ポリブ
タジエン樹脂,フェノール樹脂,及びポリイミド樹脂等
の熱硬化性樹脂を用いることができる。
In the above structure, it is preferable that the space between the semiconductor element and the semiconductor element protection member and the space around the semiconductor element are filled with an insulator. As the insulator, for example, thermosetting resin such as epoxy resin, polybutadiene resin, phenol resin, and polyimide resin can be used.

【0011】前記構成においては、前記絶縁物中に高熱
伝導性を有するフィラーが添加されていることが好まし
い。前記高熱伝導性を有するフィラーとしては例えばア
ルミニウム等の金属やアルミナ,窒化アルミニウム等の
金属酸化物または窒化物の微粒子を用いることができ
る。
In the above structure, it is preferable that a filler having high thermal conductivity is added to the insulator. As the filler having high thermal conductivity, fine particles of a metal such as aluminum, a metal oxide such as alumina or aluminum nitride, or a nitride can be used.

【0012】前記構成においては、前記半導体素子と前
記半導体素子保護用部材との間に放熱用部材が挟まれて
いることがことが好ましい。前記放熱用部材としては例
えばアルミナ,窒化アルミニウム等の高熱伝導性を有す
る金属酸化物または窒化物により製作された板状または
フィン状の部材を用いることができる。
In the above structure, it is preferable that a heat radiation member is sandwiched between the semiconductor element and the semiconductor element protection member. As the heat dissipation member, for example, a plate-shaped or fin-shaped member made of a metal oxide or nitride having a high thermal conductivity such as alumina or aluminum nitride can be used.

【0013】前記構成においては、前記半導体素子保護
用部材の第2の主面に半導体素子とは異なる他の電子部
品が実装されていることが好ましい。更に、本発明にか
かる半導体装置は、前記半導体装置が複数積み重ねら
れ、上下に位置する半導体装置が互いの前記第2の電極
により電気的に接続されてなるものである。
In the above structure, it is preferable that another electronic component different from the semiconductor element is mounted on the second main surface of the semiconductor element protecting member. Further, in the semiconductor device according to the present invention, a plurality of the semiconductor devices are stacked and the upper and lower semiconductor devices are electrically connected to each other by the second electrodes.

【0014】[0014]

【作用】前記した本発明にかかる半導体装置の構成によ
れば、半導体素子と、折り曲げ可能な絶縁性基板材料の
第1の主面に第1の電極が形成され,第2の主面に前記
第1の電極に電気的に接続された第2の電極が形成され
てなる半導体素子保護用部材とを有し、前記絶縁性基板
材料をその前記第1の主面に前記半導体素子の電極形成
面に対向する第1の領域と,前記半導体素子の電極形成
面の裏側面に対向する第2の領域とが形成されるよう折
り曲げて、前記第1の電極を前記半導体素子の電極に直
接接続し、前記第2の電極を外部装置との電気的接続を
行うための電極にしたことにより、半導体素子に損傷を
与えることなく、実装作業を行えるとともに、実装基板
上における実装面積が半導体素子の面積より若干大きい
程度ですみ、高密度実装が可能になる。
According to the above-mentioned structure of the semiconductor device of the present invention, the semiconductor element and the first main surface of the foldable insulating substrate material are provided with the first electrode, and the second main surface is provided with the first electrode. A semiconductor element protection member formed by forming a second electrode electrically connected to the first electrode, and forming the electrode of the semiconductor element on the first main surface of the insulating substrate material. The first electrode is directly connected to the electrode of the semiconductor element by bending so as to form a first area facing the surface and a second area facing the back surface of the electrode formation surface of the semiconductor element. Since the second electrode is used as an electrode for electrical connection with an external device, the mounting work can be performed without damaging the semiconductor element, and the mounting area on the mounting board is smaller than that of the semiconductor element. Only slightly larger than the area, high density Implementation is possible.

【0015】前記構成の好ましい例として、前記第2の
電極が、前記第2の主面におけるその前記半導体素子の
電極形成面に対する位置関係が互いに異なる2つ以上の
領域に設けられていることにより、複数の半導体装置を
実装基板上で連結して実装することができ、高密度化の
面から実用性に優れたものとなる。
As a preferred example of the above structure, the second electrode is provided in two or more regions having different positional relations with respect to the electrode formation surface of the semiconductor element on the second main surface. Since a plurality of semiconductor devices can be connected and mounted on a mounting board, the device is highly practical in terms of high density.

【0016】前記構成の好ましい例として、前記第2の
電極が、前記第2の主面における前記半導体素子の電極
形成面と同一方向を向く第1の領域と、前記半導体素子
の電極形成面の裏側面と同一方向を向く第2の領域とに
それぞれ設けられていることにより、複数の半導体装置
を用いてこれを実装基板上で基板面に対して垂直方向,
あるいは水平方向に積み上げて実装することができ、全
体装置の実装面積を極めて小さくすることができる。
As a preferred example of the above structure, the second electrode has a first region in the second main surface which faces the same direction as the electrode forming surface of the semiconductor element, and an electrode forming surface of the semiconductor element. Since the semiconductor device is provided in each of the back surface and the second region that faces the same direction, a plurality of semiconductor devices are used to mount the semiconductor device on the mounting substrate in a direction perpendicular to the substrate surface.
Alternatively, they can be stacked and mounted in the horizontal direction, and the mounting area of the entire device can be made extremely small.

【0017】前記構成の好ましい例として、前記折り曲
げ可能な絶縁性板材がフレキシブル樹脂基板であると、
折り曲げが容易で実装作業の作業性が向上するととも
に、コスト面から実用的なものとなる。
As a preferred example of the above structure, when the foldable insulating plate member is a flexible resin substrate,
It is easy to fold and improves the workability of mounting work, and it is practical in terms of cost.

【0018】前記構成の好ましい例として、前記折り曲
げ可能な絶縁性板材が樹脂含浸有機質不織布材からなる
基板であり、前記半導体素子保護用部材がこの樹脂含浸
有機質不織布材からなる基板を用いて構成された多層プ
リント配線板であると、半導体素子保護用部材に多くの
配線層,電源層を作り込むことができ、熱放散性に優
れ、しかも高密度化の面から実用的なものとなる。
As a preferred example of the above construction, the foldable insulating plate material is a substrate made of a resin-impregnated organic nonwoven fabric material, and the semiconductor element protecting member is made of a substrate made of the resin-impregnated organic nonwoven fabric material. The multi-layer printed wiring board has many wiring layers and power supply layers formed in the semiconductor element protection member, is excellent in heat dissipation and is practical in terms of high density.

【0019】前記構成の好ましい例として、前記半導体
素子と前記半導体素子保護用部材との間の空間および前
記半導体素子の周辺の空間に絶縁物が充填されている
と、機械的的強度に優れたものとなる。
As a preferred example of the above structure, when a space between the semiconductor element and the semiconductor element protecting member and a space around the semiconductor element are filled with an insulator, mechanical strength is excellent. Will be things.

【0020】前記構成の好ましい例として、前記絶縁物
中に高熱伝導性を有するフィラーが添加されていると、
機械的的強度に加え熱放散性に優れたものとなる。前記
構成の好ましい例として、前記半導体素子と前記半導体
素子保護用部材との間に放熱用部材が挟まれていると、
熱放散性に優れたものとなる。、前記構成の好ましい例
として、前記半導体素子保護用部材の第2の主面に半導
体素子とは異なる他の電子部品が実装されていると、混
成回路装置として有効に使用することができる。
As a preferred example of the above constitution, when a filler having high thermal conductivity is added to the insulator,
It has excellent heat dissipation in addition to mechanical strength. As a preferred example of the configuration, when a heat dissipation member is sandwiched between the semiconductor element and the semiconductor element protection member,
It has excellent heat dissipation. As a preferred example of the above configuration, when another electronic component different from the semiconductor element is mounted on the second main surface of the semiconductor element protection member, it can be effectively used as a hybrid circuit device.

【0021】更に前記した本発明にかかる半導体装置の
構成によれば、前記半導体装置が複数積み重ねられ、上
下に位置する半導体装置が互いの前記第2の電極により
電気的に接続されてなるものであることにより、複数の
半導体素子が実装基板上に1個の半導体素子の実装面積
に等しい実装面積で実装された半導体装置を得ることが
できる。
Further, according to the above-mentioned structure of the semiconductor device of the present invention, a plurality of the semiconductor devices are stacked, and the semiconductor devices located above and below are electrically connected to each other by the second electrodes. Due to this, it is possible to obtain a semiconductor device in which a plurality of semiconductor elements are mounted on a mounting substrate in a mounting area equal to the mounting area of one semiconductor element.

【0022】[0022]

【実施例】以下、本発明の実施例を図に基づいて説明す
る。 (実施例1)図1は本発明の実施例1による半導体装置
の構成を示す断面図であり、図において、半導体素子1
の第1の主面に半導体電極2が形成され、半導体電極2
が半導体キャリア3の第1の主面に形成された接続電極
4に導電性接着剤5により直接接続(接合)されてい
る。半導体キャリア3の第2の主面には外部電極(a)
6,外部電極(b) 7が形成され、これらは接続電極4と
電気的に接続されている。また、半導体素子1と半導体
キャリア3との間の空間および半導体素子1の周辺の空
間には例えばエポキシ樹脂からなる絶縁物8が充填され
ている。ここで、半導体キャリア3は例えばポリイミド
樹脂からなるフレキシブル樹脂基板を本体にしてこれを
折り曲げ、接続電極4,外部電極(a)6,および外部電
極(b)7を形成したものであり、接続電極4と、外部電
極(a)6および外部電極(b)7との電気的接続は、半導体
キャリア(フレキシブル樹脂基板)3の表面あるいは内
部に形成された配線(図示せず。)とビア(図示せ
ず。)によりなされている。また、外部電極(a)6と外
部電極(b)7とは半導体素子1を挟んで、半導体キャリ
ア3の第2の主面(外側面)上の同一投影位置に配置さ
れている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a sectional view showing the structure of a semiconductor device according to Embodiment 1 of the present invention.
The semiconductor electrode 2 is formed on the first main surface of the
Are directly connected (joined) to the connection electrode 4 formed on the first main surface of the semiconductor carrier 3 by the conductive adhesive 5. An external electrode (a) is provided on the second main surface of the semiconductor carrier 3.
6, external electrodes (b) 7 are formed, and these are electrically connected to the connection electrodes 4. The space between the semiconductor element 1 and the semiconductor carrier 3 and the space around the semiconductor element 1 are filled with an insulator 8 made of, for example, an epoxy resin. Here, the semiconductor carrier 3 is formed by bending a flexible resin substrate made of, for example, a polyimide resin as a main body to form the connection electrode 4, the external electrode (a) 6, and the external electrode (b) 7. 4 is electrically connected to the external electrode (a) 6 and the external electrode (b) 7 by wiring (not shown) formed on the surface or inside of the semiconductor carrier (flexible resin substrate) 3 and via (FIG. Not shown). The external electrode (a) 6 and the external electrode (b) 7 are arranged at the same projection position on the second main surface (outer surface) of the semiconductor carrier 3 with the semiconductor element 1 interposed therebetween.

【0023】このような本実施例の半導体装置では、半
導体素子1の電極2を半導体キャリア3の接続電極4に
直接接続することから、半導体キャリア3を従来のパッ
ケージに比して小さい面積にでき、その結果、実装基板
上における実装面積が半導体素子の面積より若干大きい
程度ですみ、高密度実装が可能になる。しかも、フリッ
プチップ方式のように、半導体素子を直接ハンドリング
することなく、実装基板上に実装できるので、半導体素
子に損傷を与えることもない。また、パッケージに比し
て半導体キャリア(フレキシブル樹脂基板)3が安価で
あり、装置コストを削減できる。また、例えば、メモリ
ー素子のように、複数のメモリー素子を共通の端子によ
り電気的に接続する必要が有る半導体素子の場合に、複
数の半導体装置を実装基板(回路基板)上に積み重ね、
上下に位置する半導体装置の外部電極(a)6と外部電極
(b)7を直接接続することにより、複数の半導体素子を
配線を用いることなく電気的に接続でき、複数の半導体
素子を1つの半導体素子の実装面積に実装することがで
きる。
In such a semiconductor device of this embodiment, since the electrode 2 of the semiconductor element 1 is directly connected to the connection electrode 4 of the semiconductor carrier 3, the semiconductor carrier 3 can have a smaller area than that of the conventional package. As a result, the mounting area on the mounting board is slightly larger than the area of the semiconductor element, and high-density mounting becomes possible. Moreover, unlike the flip-chip method, the semiconductor element can be mounted on the mounting substrate without directly handling it, so that the semiconductor element is not damaged. Further, the semiconductor carrier (flexible resin substrate) 3 is cheaper than the package, and the device cost can be reduced. Further, for example, in the case of a semiconductor element such as a memory element that needs to electrically connect a plurality of memory elements through a common terminal, a plurality of semiconductor devices are stacked on a mounting board (circuit board),
The external electrodes (a) 6 and the external electrodes of the semiconductor device located above and below
(b) By connecting 7 directly, a plurality of semiconductor elements can be electrically connected without using wiring, and a plurality of semiconductor elements can be mounted in the mounting area of one semiconductor element.

【0024】(実施例2)図2は本発明の実施例2によ
る半導体装置の構成を示す断面図であり、図において、
図1と同一符号は同一または相当する部分を示してい
る。前記実施例1の装置は、外部電極(b) 7が半導体キ
ャリア3の第2の主面(外側面)における半導体素子1
の電極形成面の裏側面と同一方向を向く面、すなわち、
装置の上面に設けられたものであるが、本実施例の装置
は外部電極(b) 7が半導体キャリア3の第2の主面(外
側面)における半導体素子1の側面と同一方向を向く
面、すなわち、装置の側面に設けられたものである。
(Embodiment 2) FIG. 2 is a sectional view showing the structure of a semiconductor device according to Embodiment 2 of the present invention.
The same reference numerals as those in FIG. 1 indicate the same or corresponding portions. In the device of Example 1, the external electrode (b) 7 is the semiconductor element 1 on the second main surface (outer surface) of the semiconductor carrier 3.
A surface facing the same direction as the back surface of the electrode formation surface of, that is,
Although provided on the upper surface of the device, in the device of this embodiment, the external electrode (b) 7 is a surface facing the same direction as the side surface of the semiconductor element 1 on the second main surface (outer surface) of the semiconductor carrier 3. That is, it is provided on the side surface of the device.

【0025】このような本実施例の半導体装置では、実
装基板(回路基板)に実装された複数の装置を、各装置
の側面の外部電極(b) 7同士を接続することにより連結
できるので、実装基板(回路基板)における装置間の電
気的接続のための配線層を削減でき、高密度な実装を行
うことができる。
In such a semiconductor device of this embodiment, since a plurality of devices mounted on the mounting substrate (circuit board) can be connected by connecting the external electrodes (b) 7 on the side surfaces of each device, Wiring layers for electrical connection between devices on the mounting board (circuit board) can be reduced, and high-density mounting can be performed.

【0026】(実施例3)図3は本発明の実施例2によ
る半導体装置の構成を示す断面図であり、図において、
図1と同一符号は同一または相当する部分を示してい
る。本実施例の半導体装置は、前記実施例1,2の装置
の構成を複合した構成のものであり、実装基板上で複数
の半導体装置を垂直方向と横方向に連結できるので、前
記実施例1,2の装置に比してより高密度な実装が可能
になる。
(Embodiment 3) FIG. 3 is a sectional view showing the structure of a semiconductor device according to Embodiment 2 of the present invention.
The same reference numerals as those in FIG. 1 indicate the same or corresponding portions. The semiconductor device according to the present embodiment has a configuration obtained by combining the configurations of the devices according to the first and second embodiments, and a plurality of semiconductor devices can be connected in the vertical direction and the horizontal direction on the mounting substrate. , 2 can be mounted at a higher density than that of the device.

【0027】(実施例4)図4は本発明の実施例4によ
る半導体装置の構成を示す断面図であり、図において、
図1と同一符号は同一または相当する部分を示してい
る。前記実施例1〜3の半導体装置は、半導体キャリア
3が半導体素子1の1つの側面を介して半導体素子1を
挟む構造に折り曲げられて構成されたものであるが、本
実施例装置は、半導体キャリア3が半導体素子1の2つ
の側面を介して半導体素子1を挟む構造に折り曲げら
れ、前記実施例1の装置と同様に、半導体キャリア3の
第2の主面(外側面)における半導体素子1の電極形成
面の裏側面と同一方向を向く面、すなわち、装置の上面
に外部電極(b) 7が設けられたものである。
(Embodiment 4) FIG. 4 is a sectional view showing the structure of a semiconductor device according to Embodiment 4 of the present invention.
The same reference numerals as those in FIG. 1 indicate the same or corresponding portions. The semiconductor devices of Examples 1 to 3 are configured by bending the semiconductor carrier 3 into a structure that sandwiches the semiconductor element 1 with one side surface of the semiconductor element 1 interposed therebetween. The carrier 3 is bent into a structure sandwiching the semiconductor element 1 via the two side surfaces of the semiconductor element 1, and the semiconductor element 1 on the second main surface (outer surface) of the semiconductor carrier 3 is the same as the device of the first embodiment. The external electrode (b) 7 is provided on the surface facing the same direction as the back side of the electrode forming surface, that is, the upper surface of the device.

【0028】このような本実施例の装置では、前記実施
例1の装置と同様の効果が得られるとともに、接続電極
4と,外部電極(a)6 および外部電極(b)7 とを配線や
ビアを用いて電気的に接続させるための作業が容易にな
る。
In the device of this embodiment as described above, the same effect as that of the device of the first embodiment can be obtained, and the connection electrode 4, the external electrode (a) 6 and the external electrode (b) 7 are connected by wiring or wiring. The work for electrically connecting vias is facilitated.

【0029】(実施例5)図5は本発明の実施例5によ
る半導体装置の構成を示す断面図であり、図において、
図1と同一符号は同一または相当する部分を示してい
る。本実施例の半導体装置は、前記実施例4の装置と同
様に、半導体キャリア3が半導体素子1の2つ側面を介
して半導体素子1を挟む構造に折り曲げられ、半導体キ
ャリア3の第2の主面(外側面)における半導体素子1
の2つの側面と同一方向を向くそれぞれの面、すなわ
ち、装置の2つの側面に外部電極(b) 7が設けられたも
のである。
(Embodiment 5) FIG. 5 is a sectional view showing the structure of a semiconductor device according to Embodiment 5 of the present invention.
The same reference numerals as those in FIG. 1 indicate the same or corresponding portions. In the semiconductor device of the present embodiment, the semiconductor carrier 3 is bent into a structure in which the semiconductor element 1 is sandwiched via the two side surfaces of the semiconductor element 1 in the same manner as the device of the fourth embodiment. Semiconductor element 1 on the surface (outer surface)
The external electrodes (b) 7 are provided on the respective surfaces facing the same direction as the two side surfaces of the device, that is, on the two side surfaces of the device.

【0030】このような本実施例の半導体装置では、装
置の2つの側面に外部電極(b) 7がそれぞれを設けられ
ているので、前記実施例2の装置に比して、実装基板上
で互いの外部電極(b) 7を直接接続することにより連結
して実装することのできる装置数を増やすことができ
る。
In such a semiconductor device of this embodiment, since the external electrodes (b) 7 are provided on the two side surfaces of the device, the external electrodes (b) 7 are provided on the mounting substrate as compared with the device of the second embodiment. By directly connecting the external electrodes (b) 7 to each other, the number of devices that can be connected and mounted can be increased.

【0031】(実施例6)図6は本発明の実施例6によ
る半導体装置の構成を示す断面図であり、図において、
図1と同一符号は同一または相当する部分を示してい
る。本実施例の半導体装置は、前記実施例4,5の装置
の構成を複合した構成のものであり、実装基板上で複数
の半導体装置を垂直方向と横方向に連結できるので、前
記実施例4,5の装置に比してより高密度な実装を行う
ことができる。
(Embodiment 6) FIG. 6 is a sectional view showing the structure of a semiconductor device according to Embodiment 6 of the present invention.
The same reference numerals as those in FIG. 1 indicate the same or corresponding portions. The semiconductor device of the present embodiment has a configuration obtained by combining the configurations of the devices of the fourth and fifth embodiments, and since a plurality of semiconductor devices can be connected vertically and laterally on the mounting substrate, the semiconductor device of the fourth embodiment is described. , 5 can be mounted at a higher density than that of the devices of FIGS.

【0032】なお、前記実施例1〜6では、半導体キャ
リアを半導体素子の1つまたは2つの側面を介して半導
体素子を挟むように折り曲げ、その外側面における半導
体素子の1つまたは2つの側面とそれぞれ同一方向を向
く1つまたは2つの面に外部電極を設けが、本発明で
は、半導体キャリアを半導体素子の3つ以上の側面を介
して半導体素子を挟むように折り曲げ、その外側面にお
ける半導体素子の3つ以上の側面とそれぞれ同一方向を
向く3つ以上の面に外部電極を設けることも可能であ
り、この場合は、接続電極と外部電極を配線やビアによ
り電気的に接続させるための作業がより一層容易にな
る。
In the first to sixth embodiments, the semiconductor carrier is bent so as to sandwich the semiconductor element via one or two side surfaces of the semiconductor element, and one or two side surfaces of the semiconductor element are formed on the outer side surfaces thereof. The external electrodes are provided on one or two surfaces respectively facing the same direction. In the present invention, the semiconductor carrier is bent so as to sandwich the semiconductor element via three or more side surfaces of the semiconductor element, and the semiconductor element on the outer surface thereof is bent. It is also possible to provide external electrodes on three or more surfaces that face the same direction as the three or more side surfaces, respectively. In this case, work for electrically connecting the connection electrode and the external electrode by wiring or vias. Will be even easier.

【0033】また、前記実施例1〜6では、半導体キャ
リアの本体基板としてフレキシブル樹脂基板を用いた
が、本発明では、半導体キャリアの本体基板として折り
曲げ可能で半導体素子を挟むことができる他の絶縁性基
板を用いることも可能であり、例えば、エポキシ樹脂ま
たはポリイミド樹脂含浸のアラミド繊維からなるシート
基板,フェノール樹脂含浸の紙からなるシート基板等を
用いることができる。そして、これら樹脂を含浸させた
有機質不織布からなるシート基板を用いて多層配線板を
構成した場合には、基板に複数の配線層をもたせること
ができるので、接続できる電極(接続電極,外部電極)
の数を増加させることができ、また、基板に複数の電源
層をもたせることができるので、電気的雑音に強くなる
とともに、熱放散性が向上する。
Further, in the first to sixth embodiments, the flexible resin substrate is used as the main body substrate of the semiconductor carrier. However, in the present invention, other insulating materials that can be folded and sandwich the semiconductor element as the main body substrate of the semiconductor carrier are used. It is also possible to use a flexible substrate, for example, a sheet substrate made of aramid fiber impregnated with epoxy resin or polyimide resin, a sheet substrate made of paper impregnated with phenol resin, or the like. When a multilayer wiring board is formed using a sheet substrate made of an organic non-woven fabric impregnated with these resins, the substrate can have a plurality of wiring layers, and therefore electrodes that can be connected (connection electrodes, external electrodes)
Can be increased, and since the substrate can be provided with a plurality of power supply layers, the resistance to electrical noise is improved and the heat dissipation is improved.

【0034】また、前記実施例1〜6では、半導体電極
と接続電極を導電性接着剤を用いて直接接合したが、本
発明ではこれら半導体電極と接続電極を半田や他の導電
性の接合材料を用いて直接接合することも可能である。
In the first to sixth embodiments, the semiconductor electrode and the connection electrode are directly joined by using a conductive adhesive, but in the present invention, the semiconductor electrode and the connection electrode are soldered or another conductive joining material. It is also possible to directly bond by using.

【0035】また、前記実施例1〜6では、半導体電極
と接続電極を直接接合したが、本発明ではこれら半導体
電極と接続電極をワイヤボンドやTAB(tape automate
d bonding)によって接続することも可能である。ただ
し、この場合は半導体電極と接続電極を直接接合する構
造に比較して、若干装置が大きくなる。
In the first to sixth embodiments, the semiconductor electrode and the connection electrode are directly joined, but in the present invention, the semiconductor electrode and the connection electrode are wire-bonded or TAB (tape automate).
It is also possible to connect by d bonding). However, in this case, the device is slightly larger than the structure in which the semiconductor electrode and the connection electrode are directly joined.

【0036】また、前記実施例1〜6では、半導体素子
と半導体キャリアとの間の空間および半導体素子の周辺
の空間にエポキシ樹脂を絶縁物として充填して、装置強
度を高めたものにしているが、本発明では必ずしもこの
ような絶縁物の充填を行う必要はない。なお、絶縁物を
充填する際、絶縁物中にアルミニウム等の金属やアルミ
ナ,窒化アルミニウム等の高熱伝導性を有する金属酸化
物または窒化物の微粒子を添加すると、装置強度を高め
ることができると同時に、熱放散性が向上する。
Further, in the first to sixth embodiments, the space between the semiconductor element and the semiconductor carrier and the space around the semiconductor element are filled with epoxy resin as an insulator to enhance the strength of the device. However, in the present invention, it is not always necessary to fill such an insulating material. When the insulating material is filled with metal particles such as aluminum or metal oxides or nitride particles having high thermal conductivity such as alumina or aluminum nitride, which are added to the insulating material, the strength of the device can be increased. , Heat dissipation is improved.

【0037】また、本発明では、半導体素子と半導体キ
ャリアとの間にアルミナ,窒化アルミニウム等の高熱伝
導性を有する金属酸化物または窒化物により製作された
板状またはフィン状の部材を挟み、熱放散性を更に向上
させることができる。
Further, according to the present invention, a plate-shaped or fin-shaped member made of a metal oxide or a nitride having a high thermal conductivity such as alumina or aluminum nitride is sandwiched between the semiconductor element and the semiconductor carrier, and heat is applied. The radiation property can be further improved.

【0038】また、前記実施例1〜6では、半導体キャ
リアに1つの半導体素子のみが挟まれているが、本発明
では2以上の半導体素子や半導体素子と他の電子部品を
挟むことも可能であり、マルチチップモデュール等も構
成することができる。
Further, in the first to sixth embodiments, only one semiconductor element is sandwiched by the semiconductor carrier, but in the present invention, it is also possible to sandwich two or more semiconductor elements or semiconductor elements and other electronic parts. Yes, a multi-chip module or the like can be configured.

【0039】また、本発明では、半導体キャリアの外側
面に半導体素子や半導体素子とは異なる他の電子部品、
例えば、コンデンサ,抵抗,インダクタ等を設けること
ができ、この場合、小型の混成回路装置をとして有効に
使用できる。
Further, according to the present invention, a semiconductor element or another electronic component different from the semiconductor element is provided on the outer surface of the semiconductor carrier,
For example, a capacitor, a resistor, an inductor, etc. can be provided, and in this case, a small hybrid circuit device can be effectively used.

【0040】[0040]

【発明の効果】本発明にかかる半導体装置によれば、半
導体素子と、折り曲げ可能な絶縁性基板材料の第1の主
面に第1の電極が形成され,第2の主面に前記第1の電
極に電気的に接続される第2の電極が形成されてなる半
導体素子保護用部材とを有し、前記絶縁性基板材料をそ
の前記第1の主面に前記半導体素子の電極形成面に対向
する第1の領域と,前記半導体素子の電極形成面の裏側
面に対向する第2の領域とが形成されるよう折り曲げ
て、前記第1の電極を前記半導体素子の電極に直接接続
し、前記第2の電極を外部装置との電気的接続を行うた
めの電極にしたことにより、半導体素子に損傷を与える
ことなく、実装作業を行えるとともに、実装基板上にお
ける実装面積が半導体素子の面積より若干大きい程度で
すみ、高密度実装が可能になる。
According to the semiconductor device of the present invention, the first electrode is formed on the semiconductor element and the first main surface of the bendable insulating substrate material, and the first electrode is formed on the second main surface. A member for protecting a semiconductor element, in which a second electrode electrically connected to the electrode is formed, and the insulating substrate material is provided on the first main surface thereof on the electrode forming surface of the semiconductor element. Bending so as to form a first region facing each other and a second region facing the back surface of the electrode formation surface of the semiconductor element, and directly connecting the first electrode to the electrode of the semiconductor element, By using the second electrode as an electrode for electrically connecting to an external device, the mounting work can be performed without damaging the semiconductor element, and the mounting area on the mounting substrate is smaller than the area of the semiconductor element. Only slightly larger size, high density mounting It becomes ability.

【0041】更に、本発明の半導体装置によれば、前記
半導体装置が複数積み重ねられ、上下に位置する半導体
装置が互いの前記第2の電極により電気的に接続されて
なるものであることにより、複数の半導体素子が実装基
板上に1個の半導体素子の実装面積に等しい実装面積で
実装された半導体装置を得ることができる。
Further, according to the semiconductor device of the present invention, a plurality of the semiconductor devices are stacked, and the semiconductor devices located above and below are electrically connected to each other by the second electrodes. It is possible to obtain a semiconductor device in which a plurality of semiconductor elements are mounted on a mounting substrate in a mounting area equal to the mounting area of one semiconductor element.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1による半導体装置の構成を示
す断面図。
FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の実施例2による半導体装置の構成を示
す断面図。
FIG. 2 is a sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

【図3】本発明の実施例3による半導体装置の構成を示
す断面図。
FIG. 3 is a sectional view showing the configuration of a semiconductor device according to a third embodiment of the present invention.

【図4】本発明の実施例4による半導体装置の構成を示
す断面図。
FIG. 4 is a sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.

【図5】本発明の実施例5による半導体装置の構成を示
す断面図。
FIG. 5 is a sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

【図6】本発明の実施例6による半導体装置の構成を示
す断面図。
FIG. 6 is a sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 半導体電極 3 半導体キャリア 4 接続電極 5 導電性接着剤 6 外部電極a 7 外部電極b 8 絶縁物 1 Semiconductor Element 2 Semiconductor Electrode 3 Semiconductor Carrier 4 Connection Electrode 5 Conductive Adhesive 6 External Electrode a 7 External Electrode b 8 Insulator

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子と、折り曲げ可能な絶縁性基
板材料の第1の主面に第1の電極が形成され,第2の主
面に前記第1の電極に電気的に接続された第2の電極が
形成されてなる半導体素子保護用部材とを有し、 前記絶縁性基板材料をその前記第1の主面に前記半導体
素子の電極形成面に対向する第1の領域と,前記半導体
素子の電極形成面の裏側面に対向する第2の領域とが形
成されるよう折り曲げて、前記第1の電極を前記半導体
素子の電極に直接接続し、前記第2の電極を外部との電
気的接続を行うための電極にした半導体装置。
1. A semiconductor element, a first electrode formed on a first main surface of a bendable insulating substrate material, and a first electrode electrically connected to the first electrode on a second main surface. A semiconductor element protection member having two electrodes formed thereon, the insulating substrate material having a first region facing the electrode forming surface of the semiconductor element on the first main surface thereof; The device is bent to form a second region facing the back surface of the electrode formation surface of the device, the first electrode is directly connected to the electrode of the semiconductor device, and the second electrode is electrically connected to the outside. Device used as an electrode for electrical connection.
【請求項2】 前記第2の電極が、前記第2の主面にお
けるその前記半導体素子の電極形成面に対しての配置関
係が異なる2つ以上の領域に設けられている請求項1に
記載の半導体装置。
2. The second electrode is provided in two or more regions of the second main surface, which have different positional relationships with respect to the electrode formation surface of the semiconductor element. Semiconductor device.
【請求項3】 前記第2の電極が、前記第2の主面にお
ける前記半導体素子の電極形成面と同一方向を向く第1
の領域と、前記半導体素子の電極形成面の裏側面と同一
方向を向く第2の領域とにそれぞれ設けられている請求
項1に記載の半導体装置。
3. A first electrode in which the second electrode faces the same direction as an electrode formation surface of the semiconductor element in the second main surface.
2. The semiconductor device according to claim 1, wherein the semiconductor device is provided in each of the region and the second region facing the same direction as the back surface of the electrode formation surface of the semiconductor element.
【請求項4】 前記折り曲げ可能な絶縁性基板材料がフ
レキシブル樹脂基板である請求項1に記載の半導体装
置。
4. The semiconductor device according to claim 1, wherein the bendable insulating substrate material is a flexible resin substrate.
【請求項5】 前記折り曲げ可能な絶縁性基板材料が樹
脂含浸有機質不織布材からなる基板であり、前記半導体
素子保護用部材がこの樹脂含浸有機質不織布材からなる
基板を用いて構成された両面または多層プリント配線板
である請求項1に記載の半導体装置。
5. A double-sided or multi-layer structure in which the foldable insulating substrate material is a substrate made of a resin-impregnated organic nonwoven fabric material, and the semiconductor element protecting member is made of a substrate made of the resin-impregnated organic nonwoven fabric material. The semiconductor device according to claim 1, which is a printed wiring board.
【請求項6】 前記半導体素子と前記半導体素子保護用
部材との間の空間および前記半導体素子の周辺の空間に
絶縁物が充填されている請求項1に記載の半導体装置。
6. The semiconductor device according to claim 1, wherein a space between the semiconductor element and the semiconductor element protection member and a space around the semiconductor element are filled with an insulating material.
【請求項7】 前記絶縁物中に高熱伝導性を有するフィ
ラーが添加されている請求項6に記載の半導体装置。
7. The semiconductor device according to claim 6, wherein a filler having a high thermal conductivity is added to the insulator.
【請求項8】 前記半導体素子と前記半導体素子保護用
部材との間に放熱用部材が挟まれた請求項1に記載の半
導体装置。
8. The semiconductor device according to claim 1, wherein a heat dissipation member is sandwiched between the semiconductor element and the semiconductor element protection member.
【請求項9】 前記半導体素子保護用部材の第2の主面
に半導体素子とは異なる他の電子部品が実装されている
請求項1に記載の半導体装置。
9. The semiconductor device according to claim 1, wherein another electronic component different from the semiconductor element is mounted on the second main surface of the semiconductor element protection member.
【請求項10】 請求項3に記載の半導体装置が複数積
み重ねられ、上下に位置する半導体装置が互いの前記第
2の電極により電気的に接続されてなる半導体装置。
10. A semiconductor device in which a plurality of the semiconductor devices according to claim 3 are stacked, and the semiconductor devices located above and below are electrically connected to each other by the second electrodes.
JP11616695A 1995-05-15 1995-05-15 Semiconductor device Expired - Fee Related JP3838524B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11616695A JP3838524B2 (en) 1995-05-15 1995-05-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11616695A JP3838524B2 (en) 1995-05-15 1995-05-15 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH08316636A true JPH08316636A (en) 1996-11-29
JP3838524B2 JP3838524B2 (en) 2006-10-25

Family

ID=14680427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11616695A Expired - Fee Related JP3838524B2 (en) 1995-05-15 1995-05-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3838524B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010276621A (en) * 2010-09-14 2010-12-09 Fujitsu Semiconductor Ltd Test device and test method for semiconductor device
JP2016152234A (en) * 2015-02-16 2016-08-22 古河電気工業株式会社 Electronic module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010276621A (en) * 2010-09-14 2010-12-09 Fujitsu Semiconductor Ltd Test device and test method for semiconductor device
JP2016152234A (en) * 2015-02-16 2016-08-22 古河電気工業株式会社 Electronic module

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