JPS6038841A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6038841A
JPS6038841A JP58146321A JP14632183A JPS6038841A JP S6038841 A JPS6038841 A JP S6038841A JP 58146321 A JP58146321 A JP 58146321A JP 14632183 A JP14632183 A JP 14632183A JP S6038841 A JPS6038841 A JP S6038841A
Authority
JP
Japan
Prior art keywords
conductor layer
base
conductive layers
power source
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58146321A
Other languages
Japanese (ja)
Other versions
JPH0481330B2 (en
Inventor
Takashi Miwa
孝志 三輪
Atsushi Honda
厚 本多
Koji Nakamura
功治 中村
Kanji Otsuka
寛治 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58146321A priority Critical patent/JPS6038841A/en
Publication of JPS6038841A publication Critical patent/JPS6038841A/en
Publication of JPH0481330B2 publication Critical patent/JPH0481330B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To improve the interchangeability of a semiconductor device with a package consisting of a laminated ceramic substrate in a double-layer wiring structure as well as to contrive to upgrade the moisture resistance of a package consisting of a substrate made of resin by a method wherein internal conductive layers are formed on one surface of the base of the package consisting of the substrate made of resin and such internal conductive layers as a ground conductive layer, a power source conductive layer, etc., are formed on the other surface. CONSTITUTION:A signal to the active circuit, etc., of a pellet 4 is in putted and outputted to each electrode pad through pins 7, internal conductive layers 5 and bonding wires 6, while grounding and power source supply to the pellet 4 are secured through pins 13a and 13b for grounding and power source, ground conductive layers 8, a power source conductive layer 9, through hole conductive layers 12a and 12b, the prescribed internal conductive layers 5a and 5b, the bonding wires 6 and the prescribed electrode pads. The pellet 4 and the wires 6, etc., are hermetically sealed with a soft resin 16. As the lower surface of the base 2 of a substrate 1 made of glass epoxy, whose resistance to moisture is weak, is totally coated with the ground conductive layers 8 and the power source conductive layer 9, each consisting of a metal film, etc., intrusion of moisture can be prevented.

Description

【発明の詳細な説明】 ［技術分野］ 本発明は、半導体装置、特に、パッケージのベースに樹
脂製基板を用いる技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique of using a resin substrate as a base of a package.

［背景技術］ 半導体装置において、製造原価低減のために、ガラスエ
ポキシ基板を使用することが考えられ、この場合、ガラ
スエポキシ基板の表面に１層の外部引き出し用の導体層
を形成することが通常に考えられる。[Background Art] Glass epoxy substrates may be used in semiconductor devices to reduce manufacturing costs, and in this case, it is common to form one conductor layer for external extraction on the surface of the glass epoxy substrate. It can be considered.

しかし、かかる技術においては、２屓配線のセラミック
基板が使用された半導体装置とビン配置が異なるため、
２Ｎ配線のセラしツク基板を有する半導体装置との互換
性がとれず、また、ガラスエポキシ基板は組織が緻密で
ないため、耐湿性が低下するという問題点があることが
、本発明者によって明らかにされた。However, in this technology, the bin arrangement is different from that of a semiconductor device using a ceramic substrate with two-layer wiring.
The inventor has clarified that there is a problem that it is not compatible with a semiconductor device having a ceramic substrate with 2N wiring, and that the structure of the glass epoxy substrate is not dense, resulting in a decrease in moisture resistance. It was done.

［発明の目的］ 本発明の目的は、２層配線のセラミ・／り基板を有する
半導体装置との互換性を持つガラスエポキシ基板からな
る半導体装置の技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a technology for a semiconductor device made of a glass epoxy substrate that is compatible with a semiconductor device having a ceramic/resistance substrate with two-layer wiring.

本発明のその他の目的は、耐湿性の向上を容易に可能な
半導体技術を提供することにある。Another object of the present invention is to provide a semiconductor technology that can easily improve moisture resistance.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

［発明の概要コ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、パンケージのベースを樹脂製基板により形成
し、ベースの一面に内部導体層を形成するとともに、ベ
ースの他面にグランド導体層、電源導体層等の外部導体
層を形成することにより、二層配線構造とし、２層配線
を有するセラミック基鈑の半導体装置との互換性を備え
ることができ、かつ、外部導体層とでベースの全面を被
覆できるようにすることにより、耐湿性が向上できるよ
うにしたものである。In other words, the base of the pancage is formed from a resin substrate, an internal conductor layer is formed on one side of the base, and external conductor layers such as a ground conductor layer and a power conductor layer are formed on the other side of the base. The wiring structure enables compatibility with ceramic substrate semiconductor devices having two-layer wiring, and the ability to cover the entire surface of the base with the external conductor layer improves moisture resistance. This is what I did.

［実施例コ 第１図は本発明の一実施例である半導体装置を示す縦断
面図、第２図はその上部を除いた一部省略平面図、第３
図はその一部省略底面図である。[Example 1] Fig. 1 is a vertical cross-sectional view showing a semiconductor device which is an embodiment of the present invention, Fig. 2 is a partially omitted plan view excluding the upper part, and Fig. 3 is a partially omitted plan view of the semiconductor device.
The figure is a partially omitted bottom view.

本実施例において、この半導体装置はパッケージ１を備
えており、このパッケージｌのベース２は、樹脂製基板
と都でのガラスエポキシ基板により形成されている。こ
のガラスエポキシ基板はエポキシ樹脂内にガラス短繊維
を混入させてなり、剛性、絶縁性等を備えている。ベー
ス２の上面の中央部にはキャビティ３が形成され、キャ
ビティ３の底面上にはペレット４がボンディングされて
いる。ベース２上面の周辺部には、複数条の内部導体層
５が互いに絶縁状態に放射状に形成されており、各導体
層５はベレン］−４の電極バンドにボンディングワイヤ
６により電気的にそれぞれ接続されている。In this embodiment, this semiconductor device includes a package 1, and a base 2 of this package 1 is formed of a resin substrate and a glass epoxy substrate. This glass epoxy substrate is made by mixing short glass fibers into an epoxy resin, and has rigidity, insulation properties, etc. A cavity 3 is formed in the center of the upper surface of the base 2, and a pellet 4 is bonded onto the bottom surface of the cavity 3. A plurality of internal conductor layers 5 are formed in a radial manner on the upper surface of the base 2 in a mutually insulated state, and each conductor layer 5 is electrically connected to the electrode band of the belen-4 by a bonding wire 6. has been done.

ベース２の周辺部には複数本のピン７が大小正方形の外
形線上に配列されて面に直角にグリッドされており、こ
れらピン７は各内部導体Ｍ５に電気的にそれぞれ接続さ
れている。A plurality of pins 7 are arranged on the outline of large and small squares on the periphery of the base 2 in a grid perpendicular to the surface, and these pins 7 are electrically connected to each internal conductor M5, respectively.

第３図に斜線で詳示されるように、ベース２の下面には
、外部導体層としてのグランド導体層８および電源導体
層９が、絶縁ギャップとしての境界線１０で適当に画成
させることにより互いに絶縁されて形成され、両導体層
８．９によってベース２の下面はほぼ全体的に被覆され
ている。両導体■８．９におけるピン７が突き出た各位
置には、絶縁ギャップとしての逃げ孔１１がそれぞれ形
成され、したがって、両導体層８．９はピン７に対し絶
縁されている。As shown in detail with diagonal lines in FIG. 3, a ground conductor layer 8 as an external conductor layer and a power conductor layer 9 are formed on the lower surface of the base 2 by appropriately defining a boundary line 10 as an insulating gap. The conductor layers 8.9 are formed so as to be insulated from each other, and the lower surface of the base 2 is substantially entirely covered by both conductor layers 8.9. Evacuation holes 11 are formed as insulating gaps at the positions of both conductors 8.9 where pins 7 protrude, and therefore both conductor layers 8.9 are insulated from pins 7.

ベース２のグランド導体層８に対応する少なくとも１箇
所にはスルーボール導体ＪｉＪ　１２　ａが上下面を接
続するように形成され、このスルーホール導体によりグ
ランド導体層８はベース２下面の少なくとも１条の内部
導体Ｊｆｉ５ａに電気的に接続されている。A through-ball conductor JiJ 12a is formed in at least one location corresponding to the ground conductor layer 8 of the base 2 so as to connect the upper and lower surfaces, and this through-hole conductor allows the ground conductor layer 8 to connect to at least one strip on the bottom surface of the base 2. It is electrically connected to the internal conductor Jfi5a.

同様に、ベース２の電源導体層９に対応する少なくとも
１箇所にはスルーホール導体１２ｂが形成され、このス
ルーボール導体により電源導体層９はベース２の」二面
の少なくとも１条の内部導体層５ｂに電気的に接続され
ている。Similarly, a through-hole conductor 12b is formed at at least one location corresponding to the power conductor layer 9 of the base 2, and this through-ball conductor allows the power conductor layer 9 to form at least one inner conductor layer on two sides of the base 2. 5b.

ベース２下面のグランド導体層８に対応する少なくとも
１箇所にはグランド用ビン１３ａが他のピン７に揃えら
れて突設され、このピン１３ａはグランド導体層８に電
気的に接続されるが、ベース２下面の内部導体層とは絶
縁されている。同様に、ベース２下面の電源導体層９に
対応する少なくとも１箇所には電源用ピン１３ｂが突設
され、このピン１３ｂは電源導体Ｎ９に電気的に接続さ
れるが、ベース２上面の内部導体層とは絶縁されている
。A grounding pin 13a is protruded from at least one location corresponding to the ground conductor layer 8 on the lower surface of the base 2, aligned with the other pins 7, and this pin 13a is electrically connected to the ground conductor layer 8. It is insulated from the internal conductor layer on the lower surface of the base 2. Similarly, a power supply pin 13b is protruded from at least one location corresponding to the power supply conductor layer 9 on the lower surface of the base 2, and this pin 13b is electrically connected to the power supply conductor N9. It is insulated from the other layers.

なお、内部導体層５、グランド導体層８および電源導体
層９は、たとえば、ガラスエポキシ基板の表裏面に貼着
された銅（Ｃｕ）箔をリソグラフィー処理によってエツ
チングすることにより所望のパターンに形成される。Note that the internal conductor layer 5, the ground conductor layer 8, and the power conductor layer 9 are formed into a desired pattern by, for example, etching copper (Cu) foils stuck to the front and back surfaces of a glass epoxy board by lithography processing. Ru.

ベース２上面の周辺部には、枠形状のガラスエポキシ基
板等からなるダム】４が接着剤１５等を介して固着され
、このダム１４により囲まれたキャビティ３を含む凹所
内には、非気密月止祠として、たとえばシリコーン系軟
質レジン１６がゲル状態でボッティング等の適当な手段
により注入されている。これにより、ペレット４、ワイ
ヤ３および内部導体Ｎ５の一部等は非気密封止されてい
る。A dam 4 made of a frame-shaped glass epoxy substrate or the like is fixed to the periphery of the upper surface of the base 2 via an adhesive 15 or the like. For example, a silicone-based soft resin 16 is injected in a gel state as a moon stopper by an appropriate means such as botting. Thereby, the pellet 4, the wire 3, a part of the internal conductor N5, etc. are non-hermetically sealed.

ダム１４上には、ガラスエポキシ基板等からなるキャン
プ１７が軟質レジン１６の上方を覆うように接着材１５
等を介して固着されている。An adhesive material 15 is placed on the dam 14 so that a camp 17 made of a glass epoxy substrate or the like covers the upper part of the soft resin 16.
It is fixed via etc.

次に作用を説明する。Next, the action will be explained.

前記構成にかかる半導体装置において、ペレット４の動
作回路等に対する信号はピン７、内部導体層５、ボンデ
ィングワイヤ６を通じて各電極パッドへ入出力される。In the semiconductor device having the above configuration, signals for the operating circuit of the pellet 4 and the like are inputted and outputted to each electrode pad through the pin 7, the internal conductor layer 5, and the bonding wire 6.

また、ペレット４に対するグランドおよび電源供給は、
グランド用および電源用ピン１３ａ、１３ｂ、グランド
導体層８および電源導体層９、スルーホール導体１２ａ
、１２ｂ１所定の内部導体層５ａ、５ｂ、ボンディング
ワイヤ６および所定の電極バンドを通してそれぞれ確保
される。In addition, the ground and power supply to the pellet 4 are as follows.
Ground and power supply pins 13a, 13b, ground conductor layer 8 and power supply conductor layer 9, through-hole conductor 12a
, 12b1 are secured through predetermined inner conductor layers 5a, 5b, bonding wires 6, and predetermined electrode bands, respectively.

ペレット４やワイヤ６等は軟質レジン１６により非気密
封止されるが、このレジン１６は軟質であるため、接着
性（密着性）が良好であり、かつ、発熱による熱膨張に
追従して変形しこれを吸収する。The pellet 4, wire 6, etc. are non-hermetically sealed with a soft resin 16, but since this resin 16 is soft, it has good adhesion (adhesion) and deforms following thermal expansion due to heat generation. Absorb this.

ガラスエポキシ製基板は組織的に緻密でないため、ベー
ス２下面からキャビティ３内に湿気が侵入する危険があ
るが、ベース２の下面は金属膜等からなるグランド導体
層８および電源導体層９により第３図に示す如く全体的
に被覆されているため、この被覆膜により湿気は侵入を
阻止される。Since the glass epoxy substrate is not structurally dense, there is a risk that moisture will enter the cavity 3 from the bottom surface of the base 2. As shown in FIG. 3, since the entire surface is coated, this coating film prevents moisture from entering.

すなわち、ガラスエポキシ製基板をベース２に使用しな
がらも、このパンケージＩは高い耐湿性を具備すること
になる。That is, even though a glass epoxy substrate is used for the base 2, the pancage I has high moisture resistance.

また、グランド導体層８および電ａ導体層９はきわめて
大きい放熱面を作り出すことになるため、パンケージｌ
のベース２は熱抵抗を効果的に低減される。In addition, since the ground conductor layer 8 and the a-conductor layer 9 create an extremely large heat dissipation surface, the pan case l
The base 2 can effectively reduce thermal resistance.

［効果コ （す、樹脂製基板からなるパンケージのベースの一面に
内部導体を、その他面にグランド導体層、電源導体層等
の外部導体層をそれぞれ形成することにより、二層配線
構造とすることができるため、二層配線構造の積層セラ
ミック基板からなるパンケージと互換性をとることがで
きる。[Effect: A two-layer wiring structure is created by forming an internal conductor on one side of the base of the pan cage made of a resin board, and forming external conductor layers such as a ground conductor layer and a power conductor layer on the other side. This makes it compatible with a pancage made of a multilayer ceramic substrate with a two-layer wiring structure.

（２）、ベースの外面をグランド導体層、電源導体層等
の外部導体層によって被覆することにより、ベースにち
密な被覆を形成できるため、パンケージの耐湿性が向上
できる。(2) By covering the outer surface of the base with an external conductor layer such as a ground conductor layer or a power supply conductor layer, a dense coating can be formed on the base, thereby improving the moisture resistance of the pancage.

（３）、ベースの外面全体にグランド導体層、電源導体
層等の外部導体層を形成することにより、この導体層が
放熱フィン的作用を果たすため、パンケージの熱抵抗が
小さくできる。(3) By forming external conductor layers such as a ground conductor layer and a power supply conductor layer on the entire outer surface of the base, the conductor layers function like heat radiation fins, so that the thermal resistance of the pancage can be reduced.

（４）、樹脂性基板を使用することにより、材料費、加
工費等の低減から、製造原価が低減できる。(4) By using a resin substrate, manufacturing costs can be reduced due to reductions in material costs, processing costs, etc.

（５）、ベース上のペレット、ボンディングワイヤ等を
軟質レジンによって非気密封止することにより、直い封
止性が得られるとともに、気密性試験等が省略化でき、
かつ、熱膨張差が吸収できる。(5) By non-hermetically sealing the pellets, bonding wires, etc. on the base with a soft resin, straight sealing performance can be obtained, and airtightness tests etc. can be omitted.
Moreover, the difference in thermal expansion can be absorbed.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、ベースの樹脂材料としては、ガラスエポキシ
に限らず、ポリイミド等が使用できる。For example, the base resin material is not limited to glass epoxy, but polyimide and the like can be used.

グランド導体層、電源導体層等の外部導体層によりベー
スの外面を被覆することが望ましいが、これに限定され
るものではない。Although it is desirable to cover the outer surface of the base with an external conductor layer such as a ground conductor layer or a power supply conductor layer, the present invention is not limited thereto.

外部導体層は、グランド導体層および電源導体層に限定
されるものではなく、信号人出用導体層として形成して
もよい。The external conductor layer is not limited to the ground conductor layer and the power supply conductor layer, but may be formed as a signal conductor layer.

［利用分野］ 以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるピングリソドアレイ
パソケージ型半導体装置に適用した場合について説明し
たが、それに限定されるものではなく、たとえば、デツ
プキャリア（リードレス、リーデフドを含む。）パンケ
ージ型半導体装置等にも通用できる。[Field of Application] In the above description, the invention made by the present inventor was mainly applied to a pinion grid array pathocage type semiconductor device, which is the field of application behind the invention, but the present invention is not limited thereto. For example, it can also be used in deep carriers (including leadless and lead-defed), pan-cage type semiconductor devices, and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示ず縦断面図、第２図は第
１図の如き断面をＡ−Ａ線に沿って有する半導体装置の
一部省略平面図、 第３図は第１図の如き断面をＡ−Ａ線に沿って有する半
導体装置の一部省略底面図である。 １・−・パッケージ、２・・・ベース、３・・・キャビ
ティ、４・・・ペレット、５・・・内部導体、６・・・
ワイヤ、７・・・ビン、８・・・グランド導体層（外部
導体Ｍ）、９・・・電源導体Ｎ（外部導体ｉｉ）、１０
・・・境界線、１１・・・逃げ孔、１２ａ、１２ｂ・・
・スルーポール導体層、１３ａ・・・グランド用ビン、
１３ｂ・・・電源用ビン、１４・・・ダム、１５・・・
接着材、１６・・・軟質レジン、１７・・・キャンプ。 第　１　図 第　２　図 ／ 第　３　図 ／ん ７ ７　／FIG. 1 is a longitudinal cross-sectional view of an embodiment of the present invention, FIG. 2 is a partially omitted plan view of a semiconductor device having a cross section as shown in FIG. 1 along line A-A, and FIG. 1 is a partially omitted bottom view of a semiconductor device having a cross section as shown in FIG. 1 taken along line A-A. 1... Package, 2... Base, 3... Cavity, 4... Pellet, 5... Internal conductor, 6...
Wire, 7... Bin, 8... Ground conductor layer (outer conductor M), 9... Power supply conductor N (outer conductor ii), 10
...Boundary line, 11...Escape hole, 12a, 12b...
・Through pole conductor layer, 13a... ground bin,
13b...power bottle, 14...dam, 15...
Adhesive material, 16... Soft resin, 17... Camp. Figure 1 Figure 2/ Figure 3/7 7/

Claims (1)

【特許請求の範囲】 ■、パッケージのベースが樹脂製基板により成り、ベー
スの一面に複数の内部導体層が存在するとともに、ベー
スの他面に少なくとも１部に外部導体層を有し、さらに
、外部導体層がスルーホール導体層により内部導体層の
少なくとも一部に接続されてなる半導体装置。 ２、樹脂製基板が、ガラスエポキシ材料から成ることを
特徴とする特許請求の範囲第１項記載の半導体装置。 ３、外部導体層が、ベースのほぼ全面を被覆したことを
特徴とする特許請求の範囲第１項記載の半導体装置。 ４、外部導体層の一部が、グランド導体層であり、他の
一部が電源導体層であることを特徴とする特許請求の範
囲第１項記載の半導体装置。[Claims] (1) The base of the package is made of a resin substrate, and has a plurality of internal conductor layers on one side of the base, and an external conductor layer on at least a portion of the other side of the base, and A semiconductor device in which an outer conductor layer is connected to at least a portion of an inner conductor layer by a through-hole conductor layer. 2. The semiconductor device according to claim 1, wherein the resin substrate is made of a glass epoxy material. 3. The semiconductor device according to claim 1, wherein the external conductor layer covers almost the entire surface of the base. 4. The semiconductor device according to claim 1, wherein a part of the external conductor layer is a ground conductor layer and another part is a power supply conductor layer.
JP58146321A 1983-08-12 1983-08-12 Semiconductor device Granted JPS6038841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58146321A JPS6038841A (en) 1983-08-12 1983-08-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58146321A JPS6038841A (en) 1983-08-12 1983-08-12 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6038841A true JPS6038841A (en) 1985-02-28
JPH0481330B2 JPH0481330B2 (en) 1992-12-22

Family

ID=15405022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58146321A Granted JPS6038841A (en) 1983-08-12 1983-08-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6038841A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0634255U (en) * 1992-10-09 1994-05-06 日本航空電子工業株式会社 Pin stand package for high speed operation
US7309917B2 (en) 2002-08-29 2007-12-18 Fujitsu Limited Multilayer board and a semiconductor device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938153A (en) * 1972-08-18 1974-04-09
JPS53121165A (en) * 1977-03-30 1978-10-23 Tokyo Shibaura Electric Co Printed circuit board
JPS5449475A (en) * 1977-09-28 1979-04-18 Aisin Seiki Co Ltd Saffty circuit for multi-channel brake fluid control system
JPS5542508A (en) * 1978-09-18 1980-03-25 Mitsui Concrete Kogyo Kk Fish bank block
JPS5646599A (en) * 1979-09-25 1981-04-27 Nippon Electric Co Producing wiring board
JPS57107059A (en) * 1980-12-25 1982-07-03 Fujitsu Ltd Semiconductor package
JPS5833857A (en) * 1981-08-21 1983-02-28 Nec Corp Semiconductor device
JPS58134450A (en) * 1982-02-05 1983-08-10 Hitachi Ltd Semiconductor device and manufacture thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938153A (en) * 1972-08-18 1974-04-09
JPS53121165A (en) * 1977-03-30 1978-10-23 Tokyo Shibaura Electric Co Printed circuit board
JPS5449475A (en) * 1977-09-28 1979-04-18 Aisin Seiki Co Ltd Saffty circuit for multi-channel brake fluid control system
JPS5542508A (en) * 1978-09-18 1980-03-25 Mitsui Concrete Kogyo Kk Fish bank block
JPS5646599A (en) * 1979-09-25 1981-04-27 Nippon Electric Co Producing wiring board
JPS57107059A (en) * 1980-12-25 1982-07-03 Fujitsu Ltd Semiconductor package
JPS5833857A (en) * 1981-08-21 1983-02-28 Nec Corp Semiconductor device
JPS58134450A (en) * 1982-02-05 1983-08-10 Hitachi Ltd Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0634255U (en) * 1992-10-09 1994-05-06 日本航空電子工業株式会社 Pin stand package for high speed operation
US7309917B2 (en) 2002-08-29 2007-12-18 Fujitsu Limited Multilayer board and a semiconductor device

Also Published As

Publication number Publication date
JPH0481330B2 (en) 1992-12-22

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