JP4263211B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a surface mount type semiconductor device.

  An example of a conventional semiconductor device having a ball grid array (Ball Grid Array is abbreviated as “BGA” hereinafter) structure using a tape carrier is shown in FIG.

  As shown in FIG. 5, the semiconductor device 100 is patterned in a plurality of lands 17 (electrodes) that are provided in an array along the four sides on the substrate surface side and on which the solder balls 20 (external connection terminals) are mounted. A base substrate 12 (polyimide film) in which a copper foil 16 is bonded to the lower surface by an insulating adhesive 14, and a sheet having adhesive force bonded to the exposed portion of the lower surface of the insulating adhesive 14 and the land 17. An elastomer 26 (elastic body), a semiconductor element 28 bonded to a plurality of electrode pads 30 having an inner lead 18 that is substantially fixed to the lower surface of the elastomer 26 and extends from the land 17 at the periphery of the upper surface, and an inner lead 18 and an insulating resin 32 that protects the bonding portion.

  Here, the base substrate 12, the insulating adhesive 14, the copper foil 16, the land 17, and the inner lead 18 are collectively referred to as a tape carrier 25.

  By the way, in recent years when electronic devices have been reduced in size, further reduction in the size of semiconductor devices has been demanded. However, the above-described semiconductor device having the BGA structure has a configuration in which one semiconductor element is arranged in one package. In other words, in a device using this semiconductor device, for example, when a semiconductor element having a different function is required or a plurality of semiconductor elements are required even if the same type of semiconductor element is used, it is a matter of course. Therefore, it is necessary to secure the space occupied by the packages and connection terminal portions of each semiconductor device. Therefore, it has been desired to improve the mounting density of the semiconductor device by reducing such a space.

  In view of the above fact, an object of the present invention is to provide a semiconductor device in which the mounting density at the time of mounting is improved as compared with the conventional structure.

  The semiconductor device according to claim 1 has a first semiconductor element having a surface provided with a plurality of first electrode pads, and a surface provided with a plurality of second electrode pads. A second semiconductor element disposed adjacent to the semiconductor element, a base substrate having a plurality of holes disposed on the first semiconductor element and the second semiconductor element, and a plurality of the holes. A plurality of electrode portions provided so as to be closed; a plurality of external connection terminals provided on the plurality of electrode portions; one end connected to the electrode portion disposed on the first semiconductor element; A first inner lead having an end connected to the first electrode pad, a first end connected to the electrode portion disposed on the second semiconductor element, and a second end connected to the second electrode pad Second inner lead and one end of the first inner lead A third inner lead connected to the electrode pad and having the other end separated in the middle connected to the second electrode pad and the electrode portion disposed on the first semiconductor element; Inner lead, the second inner lead, the third inner lead, a connection point between the first inner lead and the first electrode pad, the second inner lead and the second electrode Insulating resin for sealing the connection point with the pad, the connection point between the third inner lead and the first electrode pad, and the connection point between the third inner lead and the second electrode pad It is characterized by having.

  In the semiconductor device according to claim 1, since the semiconductor elements are arranged in the same plane, the semiconductor device can be made thinner than in the case where the semiconductor elements are arranged in a stack, and the semiconductor devices are mounted side by side on a plane such as a substrate. Compared to the conventional arrangement, the mounting area is reduced. Therefore, for example, when applied to a thin device or the like, the mounting density is improved as compared with a semiconductor device having a conventional structure.

  Further, when arranged in parallel as described above, they can be accommodated in one package regardless of the size of each semiconductor element.

  Since the semiconductor device of the present invention has the above configuration, the mounting density at the time of mounting can be improved as compared with the conventional structure.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Reference Invention ]
FIG. 1 shows a semiconductor device 50 having a BGA structure using a tape carrier according to the first reference invention .

  The semiconductor device 50 includes a base substrate 12 (polyimide film) having a plurality of ball mounting holes 12 a, and an insulating adhesive 14 is formed in layers on the lower surface of the base substrate 12. With this insulating adhesive 14, the patterned copper foil 16 and lands 17 (electrode portions) arranged so as to close the lower openings of the ball mounting holes 12 a are attached to the lower surface of the base substrate 12. Has been.

  Further, from each land 17, inner leads 18, 58, 60 whose surfaces are plated with gold extend obliquely downward in a predetermined direction (left and right in FIG. 1B and four directions in the front and depth directions). . Solder balls 20 projecting toward the upper surface side of the base substrate 12 are mounted on the upper surfaces of the lands 17. When the semiconductor device 50 is surface-mounted by reflow or the like on a circuit board, a mother board or the like, the solder balls 20 are welded to electrode lands formed on the board, thereby mechanically connecting the semiconductor device 50 and the board. It serves as a junction and an electrical connection.

  Further, on the lower surface side of the base substrate 12, solder resists 22 (step removal members) are formed on the side surfaces and the lower surfaces of the lands 17 and the lower surface exposed portions of the insulating adhesive 14. The solder resist 22 is obtained by, for example, applying a polyimide resin having insulating properties and heat resistance in a liquid state and applying heat treatment or the like to solidify. Therefore, the side surface and the lower surface of the land 17 and the exposed lower surface portion of the insulating adhesive 14 are covered with the solder resist 22 formed in a substantially film shape, and at the same time, the land 17 is protected.

  As a result, the solder resist 22 enters and adheres to the stepped portion or uneven portion formed by the land 17 without any gap, and the shape thereof is maintained. Here, the base substrate 12, the adhesive layer 14, the copper foil 16, the land 17, the inner leads 18, 58 and 60, and the solder resist 22 are collectively referred to as a tape carrier 24.

  Further, the lower surface of the solder resist 22 is a smooth surface, and the semiconductor element 28 is substantially fixed to the lower surface of the tape carrier 24 by an elastic elastomer 26 having an adhesive force attached to the lower surface. A direction (vertical direction in FIG. 1B) is arranged substantially at the center.

  A plurality of electrode pads 30 are provided on the peripheral portion on the upper surface side of the semiconductor element 28, and predetermined inner leads 18 and 60 corresponding to the electrode pads 30 are bonded to the electrode pad 30.

  Further, a semiconductor element 54 whose outer dimension is slightly larger than that of the semiconductor element 28 is fixed to the lower surface of the semiconductor element 28 via an adhesive 52. Similarly to the semiconductor element 28, an electrode pad 56 is provided on the peripheral edge of the upper surface of the semiconductor element 54.

  For the connection between the electrode pad 56 and the land 17 of the semiconductor element 54, the inner lead 58 (which is bent once in the thickness direction) directly connecting the land 17 and the electrode pad 56, and the land 17 through the electrode pad 30. Then, an inner lead 60 (bending in the thickness direction multiple times) connected to the electrode pad 56 is used.

  As a result, the semiconductor elements 28 and 54 are electrically connected to an electric circuit of the substrate via the solder balls 20 as external connection terminals between the semiconductor device 28 and the substrate when the semiconductor device 50 is mounted. A predetermined peripheral portion of the tape carrier 24 is sealed with an insulating resin 32 that protects the inner leads 18, 58, 60 and the bonding portion.

  Next, an outline of a method for manufacturing the semiconductor device 50 having the above-described configuration will be described.

  First, a hole required by a mold or etching is opened in the base substrate 12 having a cover tape attached to the lower surface of the insulating adhesive 14. The holes are a ball mounting hole 12a for mounting the solder ball 20, a bonding hole for connecting the inner lead 18 and the electrode pad 30, and a perforation hole used for positioning and transporting the base substrate 12. .

  Next, the cover tape is peeled off, and the copper foil 16 is attached to the insulating adhesive 14. Subsequently, a photosensitive resist is applied to the lower surface of the copper foil 16, and a back coat material is applied to the upper surface of the copper foil 16.

  Here, when the photosensitive resist is exposed and developed through a mask on which a circuit pattern is baked, a predetermined portion of the photosensitive resist is dissolved by a developer, and a pattern (concave portion) is formed. Further, the exposed portion of the copper foil 16 is processed by etching, and when the photosensitive resist and the back coat material are peeled off, the land 17 and the inner leads 18, 58, 60 are formed.

  Further, a solder resist 22 (insulating layer) is applied to a part of the land 17 and the inner leads 18, 58 and 60. As a method for applying the solder resist 22, for example, screen printing can be used. Thus, the tape carrier 24 is completed.

  In manufacturing a BGA-structured semiconductor device using the tape carrier 24 and the semiconductor elements 28 and 54, first, a sheet-like elastomer 26 processed into a predetermined shape is attached to the solder resist 22 with heat and load. The semiconductor element 28 is aligned and joined to the elastomer 26 by heat and load. Furthermore, after a sheet-like adhesive 52 processed into a predetermined shape is attached to the lower surface of the semiconductor element 28, the semiconductor element 54 is aligned and bonded to the semiconductor element 28 via the adhesive 52.

  Next, according to the “single point bonding method using both ultrasonic, heat and load”, heat, load and ultrasonic waves are applied to perform inner bonding in the bonding hole portion, and the inner leads 18, 58 and 60 are connected to the electrode pads 30 and 56. To be joined. Here, in the case of the inner lead 60 that is joined at two locations, the upper electrode pad 30 is joined after the lower electrode pad 56 is joined first. Therefore, the semiconductor element 28 and the semiconductor element 54 are electrically connected within the semiconductor device 50 by the inner lead 60.

  Subsequently, the inner bonding portion is sealed with the resin 32, the solder ball 20 is mounted on the upper surface of the land 17, and heat is applied to join the contact portions. Finally, the product portion is punched from the tape carrier, and the semiconductor device 50 having the BGA structure is completed.

As described above, in the semiconductor device 50 of the present invention , a plurality of semiconductor elements (semiconductor elements 28 and 54) are provided in the semiconductor device, and each semiconductor element is electrically connected. That is, the semiconductor element 28 and the semiconductor element 54 are arranged in the same package and share the package and the land 17. Further, since the semiconductor element 28 and the semiconductor element 54 are arranged in a stacked manner, that is, both the semiconductor elements are overlapped in the thickness direction, the semiconductor device 50 is compared with the case where the semiconductor elements are arranged in a plane. The external dimensions in the mounting surface direction are reduced.

  As a result, the mounting space is reduced and the mounting density is improved as compared with the case where a plurality of semiconductor devices having a conventional structure in which one semiconductor element is housed in one package are mounted in a predetermined range.

  Also, compared to the conventional case where each semiconductor device is electrically connected through an external path such as a substrate pattern, the connection path between the semiconductor elements is shortened, which is advantageous for delay in signal transmission time. is there.

  Here, the semiconductor elements can be combined with semiconductor elements having different functions. That is, the upper semiconductor element 28 can be a logic semiconductor element and the lower semiconductor element 54 can be a memory semiconductor element. Of course, the combination is not limited to this, and the functions of the semiconductor device can be increased by various combinations such as logic or memory semiconductor elements.

Further, in the semiconductor device 50 of the present invention, the solder resist 22 that eliminates the step between the base substrate 12 and the land 17 is provided between the base substrate 12 and the sheet-like elastomer 26, so that the base A step due to the land 17 provided on the lower surface of the substrate 12 is removed. Further, since the solder resist 22 is a coating agent, the solder resist 22 is surely filled in the gap on the lower surface portion of the base substrate 12, and no gap remains.

  Therefore, a partial peeling force does not occur on the smoothed lower surface portion of the base substrate 12, that is, the adhesive surface of the elastomer 26 bonded to the lower surface of the solder resist 22. Therefore, a space due to partial peeling does not occur on the bonding surface, and the package is not deformed or cracked even if a thermal history is applied by mounting.

  Needless to say, since the solder resist 22 has an insulating property, there is no short circuit in the land 17 through which a current flows.

Furthermore, in this reference invention , the solder resist 22 is a polyimide resin, and is the same material as the base substrate 12 that is a polyimide film. Therefore, since the thermal expansion coefficients are almost equal, it is hardly affected by thermal stress or the like, and even if a thermal history is applied, the solder resist 22 is not peeled off from the base substrate 12 or a gap is not generated.

  In addition, various materials can be applied to the solder resist 22 in addition to the polyimide resin. For example, when an epoxy resin is used, it is less expensive than a polyimide resin, and thus there is an advantage that manufacturing costs can be reduced.

[Second Reference Invention ]
Next, the second reference invention will be described. In the second reference invention, since it is almost the same as the configuration described in the first reference invention , the same components are denoted by the same reference numerals, and the description of the configuration is omitted. The feature of the second reference invention relates to the connection structure of the semiconductor elements in the first reference invention .

FIG. 2 shows a semiconductor device 70 according to the second reference invention . The semiconductor device 70 has a structure in which a semiconductor element 28 and a semiconductor element 54 are connected by an inner lead 18 and an inner lead 58 provided on the same land 17. That is, each semiconductor element is electrically connected directly to the land 17 without using the inner lead 60 joined at two places as in the first reference invention.

  This eliminates the need for a complicated connection structure and method that spans between the semiconductor element 28 and the semiconductor element 54, and simplifies the bonding method.

[ Embodiment ]
Next, an embodiment of the present invention will be described. In this embodiment , the same components as those described in the first reference invention are given the same reference numerals, and the description of the configurations is omitted. The feature of this embodiment relates to a semiconductor element arrangement structure different from the first and second reference inventions .

3 and 4 show a semiconductor device 80 according to an embodiment of the present invention. In the semiconductor device 80, two tape carriers are arranged side by side on the same plane, and each tape carrier is provided with a semiconductor element having substantially the same external dimensions and thickness. Here, the semiconductor element 28L is substantially fixed to the left tape carrier 24L, and the semiconductor element 28R is substantially fixed to the right tape carrier 24R by an elastomer 26, respectively. Further, the semiconductor elements 28L and 28R are joined to the lands 17 provided on the tape carriers 24L and 28R by the electrode pads 30 by the inner leads 18.

  Further, a part of the land 17 located adjacent to the tape carriers 24L and 28R is divided into an inner lead 82 joined to the adjacent semiconductor element and a fork in the middle, and each tip is connected to the semiconductor elements 28L and 28R. An inner lead 84 is provided. Therefore, the semiconductor elements 28L and 28R are electrically connected by the inner lead 84.

  As described above, in the semiconductor device 80 according to the present embodiment, the semiconductor elements are arranged side by side in the same plane, so that the semiconductor device can be made thinner than the case where the semiconductor elements are arranged in a stack, and each semiconductor device can be placed on a plane such as a substrate. The mounting area is also reduced compared to a conventional array that is mounted side by side. Therefore, for example, when applied to a thin device or the like, the mounting density is improved as compared with a semiconductor device having a conventional structure.

  Further, when arranged in parallel as described above, they can be accommodated in one package regardless of the size of each semiconductor element.

In the first and second reference inventions and the present embodiment , the number of semiconductor elements in the semiconductor device is two. However, the number of arrangements is not limited to this, and even when there are three or more semiconductor elements. Applicable.

In the first and second reference inventions and the present embodiment , the present invention is applied to a semiconductor device having a BGA structure in which an inner lead used for wiring between a land and an electrode pad of a semiconductor element is a gold wire (wire) or the like. Can also

1A and 1B show a semiconductor device having a BGA structure according to a first reference invention, in which FIG. 1A is a top view and FIG. 1B is a schematic cross-sectional view taken along line 1-1 of FIG. FIG. 4A is a top view of a semiconductor device having a BGA structure according to a second reference invention , and FIG. 4B is a schematic cross-sectional view taken along line 2-2 of FIG. It is a top view which shows the semiconductor device of the BGA structure which concerns on embodiment of this invention. FIG. 4A is a schematic cross-sectional view taken along line 4a-4a in FIG. 3 and FIG. 4B is a schematic cross-sectional view taken along line 4b-4b in FIG. 3 showing a semiconductor device having a BGA structure according to the embodiment of the present invention. FIG. It is a schematic sectional drawing which shows the semiconductor device of the conventional BGA structure.

Explanation of symbols

12 Base material 17 Land (electrode part)
28 Semiconductor Element 28L Semiconductor Element 28R Semiconductor Element 50 Semiconductor Device 54 Semiconductor Element 70 Semiconductor Device 80 Semiconductor Device

Claims (1)

A first semiconductor element having a surface provided with a plurality of first electrode pads;
A second semiconductor element having a surface provided with a plurality of second electrode pads, the second semiconductor element being disposed adjacent to the first semiconductor element;
A base substrate having a plurality of holes disposed on the first semiconductor element and the second semiconductor element;
A plurality of electrode portions provided to close the plurality of holes;
A plurality of external connection terminals provided on the plurality of electrode portions;
A first inner lead having one end connected to the electrode portion disposed on the first semiconductor element and the other end connected to the first electrode pad;
A second inner lead having one end connected to the electrode portion disposed on the second semiconductor element and the other end connected to the second electrode pad;
One end is connected to the first electrode pad, and the other end divided in the middle is connected to the second electrode pad and the electrode portion disposed on the first semiconductor element. Lead and
The first inner lead, the second inner lead, and the third inner lead, a connection point between the first inner lead and the first electrode pad, the second inner lead and the second inner lead 2, a connection point between the third inner lead and the first electrode pad, and a connection point between the third inner lead and the second electrode pad are sealed. An insulating resin;
A semiconductor device comprising:

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