JPH0536853A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0536853A JPH0536853A JP3193357A JP19335791A JPH0536853A JP H0536853 A JPH0536853 A JP H0536853A JP 3193357 A JP3193357 A JP 3193357A JP 19335791 A JP19335791 A JP 19335791A JP H0536853 A JPH0536853 A JP H0536853A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- active
- integrated circuit
- circuit device
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、混成集積回路装置に関
し、特に配線基板上に能動素子，受動素子等を搭載した
混成集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which active elements, passive elements, etc. are mounted on a wiring board.
【０００２】[0002]
【従来の技術】従来この種の混成集積回路装置は、図５
および図６に示すように、配線基板１に配線パターン６
と基板端面にスルホール電極２を設け、さらに能動素
子，受動素子８等を導電性または絶縁性の接着剤７で搭
載した後、加熱硬化することにより機械的に固定させ
る。2. Description of the Related Art Conventionally, a hybrid integrated circuit device of this type is shown in FIG.
As shown in FIG. 6 and FIG.
The through-hole electrode 2 is provided on the end face of the substrate, and then the active element, the passive element 8 and the like are mounted with the conductive or insulating adhesive 7, and then thermally cured to mechanically fix the element.
【０００３】次に金属細線９を用いワイヤボンディング
法で、能動素子，受動素子８の電極と配線基板１の配線
パターン６を電気的に接続し、最後に能動素子，受動素
子８等を電気的かつ機械的に保護するための外装樹脂５
で覆う構造となっている。Next, the electrodes of the active elements and passive elements 8 are electrically connected to the wiring pattern 6 of the wiring board 1 by the wire bonding method using the fine metal wires 9, and finally the active elements and the passive elements 8 are electrically connected. And the exterior resin 5 for mechanical protection
The structure is covered with.
【０００４】[0004]
【発明が解決しようとする課題】この従来の混成集積回
路装置では、配線基板１の材質がガラスエポキシ等有機
材料を用いている理由で、熱伝導率が約０．０００４ｃ
ａｌ／ｓｅｃ・ｃｍ・℃と悪くなり消費電力の大きな、
能動素子，受動素子８等が、熱伝導率の制約上使用でき
ない欠点があった。In this conventional hybrid integrated circuit device, the thermal conductivity is about 0.0004c because the wiring substrate 1 is made of an organic material such as glass epoxy.
Al / sec · cm · ° C, which is worse and consumes more power.
There is a drawback that the active element, the passive element 8 and the like cannot be used due to the restriction of thermal conductivity.
【０００５】さらに熱膨張係数が約１５〜２０×１０-6
１／℃の配線基板１に能動素子，受動素子８等を搭載
後、電気的かつ機械的に保護する目的で、熱膨張係数が
約２５〜３０×１０-6の外装樹脂５を用いるため、熱膨
張係数差および外装樹脂５を硬化するときの収縮力等に
より機械歪が生じ配線基板１が反るため表面実装ができ
なくなる欠点がある。Further, the coefficient of thermal expansion is about 15 to 20 × 10 -6.
Since the exterior resin 5 having a thermal expansion coefficient of about 25 to 30 × 10 −6 is used for the purpose of electrically and mechanically protecting after mounting the active element, the passive element 8 and the like on the wiring board 1 of 1 / ° C., There is a disadvantage that surface mounting cannot be performed because mechanical strain occurs due to a difference in thermal expansion coefficient and a contracting force when the exterior resin 5 is cured, and the wiring substrate 1 warps.
【０００６】また配線基板１の寸法が大きくなると、こ
の反りはさらに拡大される。その上、能動素子，受動素
子８等は外装樹脂５で電気的かつ機械的に保護されてい
るだけで電気的な外乱ノイズの多い環境で使用する場
合、金属性のシールド板４でノイズ対策をしなければい
けない問題点があった。When the size of the wiring board 1 is increased, the warp is further magnified. In addition, the active element, the passive element 8 and the like are only electrically and mechanically protected by the exterior resin 5, and when used in an environment with a lot of electrical disturbance noise, the metallic shield plate 4 provides a noise countermeasure. There was a problem I had to do.
【０００７】[0007]
【課題を解決するための手段】本発明の混成集積回路装
置は、１個以上の能動素子，受動素子８等を搭載する配
線基板１に於いて、前記配線基板１のダイパッド部分に
金属板１０まで達する凹部を用いて固定する構造と金属
板１０と一体となる吊りピン３の延長部に金属性シール
ド板４を能動素子，受動素子８側の外装樹脂５面に設け
る構造を備えている。According to the hybrid integrated circuit device of the present invention, in a wiring board 1 on which one or more active elements, passive elements 8 and the like are mounted, a metal plate 10 is provided on the die pad portion of the wiring board 1. It is provided with a structure in which it is fixed using a recess reaching up to and a structure in which a metallic shield plate 4 is provided on the surface of the exterior resin 5 on the active element and passive element 8 side at the extension of the hanging pin 3 integrated with the metal plate 10.
【０００８】[0008]
【実施例】次に本発明について図面を参照して説明す
る。図１，図２および図３は本発明の一実施例の混成集
積回路装置の平面および断面図である。配線基板１に例
えば、４２合金Ｃｕ合金等の熱伝導率が約０．０４〜
０．４ｃａｌ／ｓｅｃ・ｃｍ・℃の金属板１０を多層プ
リント板製造技術で、内層に設け、さらにスルホール電
極２および配線パターン６をプリント基板の電気メッキ
法を用いて約３０〜３５μｍ（Ｃｕ箔地下を含む）のＣ
ｕメッキを施し、さらに金属細線の接合部には約５〜８
μｍのＮｉメッキおよび約０．３〜０．５μｍのＡｕメ
ッキを施す。The present invention will be described below with reference to the drawings. 1, 2, and 3 are plan and cross-sectional views of a hybrid integrated circuit device according to an embodiment of the present invention. The wiring board 1 has a thermal conductivity of, for example, 42 alloy Cu alloy of about 0.04 to
A metal plate 10 of 0.4 cal / sec · cm · ° C is provided on the inner layer by the multilayer printed board manufacturing technique, and the through-hole electrode 2 and the wiring pattern 6 are further applied to the printed board by electroplating to a thickness of about 30 to 35 μm (Cu foil). C (including underground)
u plating is applied, and about 5-8 at the joint part of the metal thin wire.
μm Ni plating and about 0.3 to 0.5 μm Au plating are applied.
【０００９】次に、能動素子，受動素子８等の搭載部に
凹部を設けることで、金属板１０を露出させると共に、
能動素子，受動素子８等を接着剤７を用いて搭載し、約
１５０〜２００℃で加熱硬化させ接合する。Next, a recess is provided in the mounting portion of the active element, the passive element 8 and the like to expose the metal plate 10 and
An active element, a passive element 8 and the like are mounted by using an adhesive agent 7, and heat-cured at about 150 to 200 ° C. to bond them.
【００１０】次に、能動素子受動素子８等と配線パター
ン６とを約φ２５〜３０μｍの金属細線９でワイヤボン
ディング法により電気的に接合した後、ポッディングま
たは、トランスファーモールド法等により外装樹脂５を
施し、金属板１０と一体となる吊りピン３の延長部に金
属性シールド板４で能動素子，受動素子８等の外装樹脂
５面を覆うことで電気的な外乱ノイズを約１０〜５０％
程度遮蔽することができると共に、能動素子，受動素子
８等から不要輻射ノイズで周囲の電子回路，機器に影響
をしないように出来る。よって混成集積回路装置のノイ
ズマージンを著しく向上させることができる。Next, the active element passive element 8 and the like and the wiring pattern 6 are electrically joined by a wire bonding method with a fine metal wire 9 having a diameter of about 25 to 30 μm, and then the exterior resin 5 is applied by padding or transfer molding. By covering the exterior resin 5 surface of the active element, the passive element 8 and the like with the metallic shield plate 4 on the extension portion of the hanging pin 3 which is integrated with the metal plate 10, about 10 to 50% of the electric disturbance noise is generated.
In addition to being shielded to some extent, it is possible to prevent the surrounding electronic circuits and devices from being affected by unnecessary radiation noise from the active element, the passive element 8 and the like. Therefore, the noise margin of the hybrid integrated circuit device can be significantly improved.
【００１１】図４は第２の実施例を示す断面図である。
本発明は、金属シールド板４に放熱フィン１１を接合
し、放熱効果をさらに良くし、消費電力の大きな、能動
素子，受動素子８等の搭載可能とした。FIG. 4 is a sectional view showing the second embodiment.
In the present invention, the radiation fin 11 is joined to the metal shield plate 4 to further improve the radiation effect, and the active element, the passive element 8 and the like having large power consumption can be mounted.
【００１２】[0012]
【発明の効果】以上説明したように本発明は、能動素
子，受動素子８等を金属板３に直接接合する構造を有し
ているので、熱伝導率を従来の約０．０００４から約
０．０４〜０．４１／℃と、大巾に小さくすることがで
きるので消費電力の大きな能動素子，受動素子８等を搭
載できるという効果がある。As described above, the present invention has a structure in which the active element, the passive element 8 and the like are directly bonded to the metal plate 3, and therefore the thermal conductivity is about 0.0004 to about 0. Since it can be greatly reduced to 0.04 to 0.41 / ° C., there is an effect that an active element, a passive element 8 and the like with large power consumption can be mounted.
【００１３】さらに配線基板１の外装樹脂５等の熱膨張
係数差による熱収縮力に耐える為、配線基板１の反りを
大巾に低減できる。また配線基板１と能動素子，受動素
子８等を金属シールド板４で含うことにより、電気的な
ノイズマージンを著しく向上させることができると共
に、放熱効果も著しく良くなる。Further, since it withstands the thermal contraction force due to the difference in thermal expansion coefficient of the exterior resin 5 of the wiring board 1, the warpage of the wiring board 1 can be greatly reduced. Further, by including the wiring board 1 and the active element, the passive element 8 and the like in the metal shield plate 4, the electrical noise margin can be remarkably improved and the heat dissipation effect can be remarkably improved.
【００１４】さらに、赤外線リフロー等による半田実装
に於いて、外装樹脂５の表面に金属シールド板４を設け
ることにより、赤外線が反射し、外装樹脂５の内部に直
接熱が伝わらないため、熱ショックを大巾に低減でき
る。よって配線基板１および外装樹脂５のクラック等を
防止することができる。Further, in solder mounting by infrared reflow or the like, by providing the metal shield plate 4 on the surface of the exterior resin 5, infrared rays are reflected and heat is not directly transmitted to the interior of the exterior resin 5, so a heat shock is generated. Can be greatly reduced. Therefore, it is possible to prevent the wiring board 1 and the exterior resin 5 from being cracked.
【図１】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.
【図２】図１のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.
【図３】図１のＢ−Ｂ線断面図である。FIG. 3 is a sectional view taken along line BB of FIG.
【図４】本発明の他の実施例を示す断面図である。FIG. 4 is a sectional view showing another embodiment of the present invention.
【図５】従来例を示す平面図である。FIG. 5 is a plan view showing a conventional example.
【図６】図５のＣ−Ｃ線断面図である。FIG. 6 is a sectional view taken along line CC of FIG.
１ 配線基板 ２ スルーホール電極 ３ 吊りピン ４ 金属性シールド板 ５ 外装樹脂 ６ 配線パターン ７ 接着剤 ８ 能動素子，受動素子 ９ 金属細線 １０ 金属板 1 Wiring board 2 Through-hole electrode 3 Hanging pin 4 Metallic shield plate 5 Exterior resin 6 Wiring pattern 7 Adhesive 8 Active element, Passive element 9 Metal thin wire 10 Metal plate
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/28 Ｅ 8617−4Ｍ 25/04 25/18 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/28 E 8617-4M 25/04 25/18
Claims (1)
配線基板のダイパットに設けられた凹部と、前記素子を
直接搭載する金属板と、前記金属板と一体となる吊りピ
ンの延長部に設けられた金属性シールド板とを有するこ
とを特徴とする混成集積回路装置。Claim: What is claimed is: 1. A wiring board on which a plurality of elements are mounted, a recess provided in a die pad of the wiring board, a metal plate on which the elements are directly mounted, and the metal plate integrated with each other. A hybrid integrated circuit device, comprising: a metallic shield plate provided on an extension of a hanging pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3193357A JP2932772B2 (en) | 1991-08-02 | 1991-08-02 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3193357A JP2932772B2 (en) | 1991-08-02 | 1991-08-02 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0536853A true JPH0536853A (en) | 1993-02-12 |
| JP2932772B2 JP2932772B2 (en) | 1999-08-09 |
Family
ID=16306569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3193357A Expired - Fee Related JP2932772B2 (en) | 1991-08-02 | 1991-08-02 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2932772B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6933604B2 (en) * | 2000-10-05 | 2005-08-23 | Sanyo Electric Co., Ltd. | Semiconductor device, semiconductor module and hard disk |
| CN102820286A (en) * | 2012-07-16 | 2012-12-12 | 昆山华太电子技术有限公司 | Structure for improving performance of passive device of power integrated circuit |
| WO2017221730A1 (en) * | 2016-06-24 | 2017-12-28 | 三菱電機株式会社 | Power semiconductor device and method for manufacturing power semiconductor device |
-
1991
- 1991-08-02 JP JP3193357A patent/JP2932772B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6933604B2 (en) * | 2000-10-05 | 2005-08-23 | Sanyo Electric Co., Ltd. | Semiconductor device, semiconductor module and hard disk |
| CN102820286A (en) * | 2012-07-16 | 2012-12-12 | 昆山华太电子技术有限公司 | Structure for improving performance of passive device of power integrated circuit |
| WO2017221730A1 (en) * | 2016-06-24 | 2017-12-28 | 三菱電機株式会社 | Power semiconductor device and method for manufacturing power semiconductor device |
| JPWO2017221730A1 (en) * | 2016-06-24 | 2018-10-11 | 三菱電機株式会社 | Power semiconductor device and method for manufacturing power semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2932772B2 (en) | 1999-08-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990427 |
|
| LAPS | Cancellation because of no payment of annual fees |