JP2932772B2 - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JP2932772B2
JP2932772B2 JP3193357A JP19335791A JP2932772B2 JP 2932772 B2 JP2932772 B2 JP 2932772B2 JP 3193357 A JP3193357 A JP 3193357A JP 19335791 A JP19335791 A JP 19335791A JP 2932772 B2 JP2932772 B2 JP 2932772B2
Authority
JP
Japan
Prior art keywords
integrated circuit
wiring board
circuit device
hybrid integrated
active element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3193357A
Other languages
Japanese (ja)
Other versions
JPH0536853A (en
Inventor
小室哲雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3193357A priority Critical patent/JP2932772B2/en
Publication of JPH0536853A publication Critical patent/JPH0536853A/en
Application granted granted Critical
Publication of JP2932772B2 publication Critical patent/JP2932772B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、混成集積回路装置に関
し、特に配線基板上に能動素子,受動素子等を搭載した
混成集積回路装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device having an active element, a passive element and the like mounted on a wiring board.

【0002】[0002]

【従来の技術】従来この種の混成集積回路装置は、図5
および図6に示すように、配線基板1に配線パターン6
と基板端面にスルホール電極2を設け、さらに能動素
子,受動素子8等を導電性または絶縁性の接着剤7で搭
載した後、加熱硬化することにより機械的に固定させ
る。
2. Description of the Related Art Conventionally, a hybrid integrated circuit device of this kind is shown in FIG.
As shown in FIG. 6 and FIG.
Then, the through-hole electrode 2 is provided on the end face of the substrate, and the active element, the passive element 8 and the like are mounted with a conductive or insulating adhesive 7 and then mechanically fixed by heating and curing.

【0003】次に金属細線9を用いワイヤボンディング
法で、能動素子,受動素子8の電極と配線基板1の配線
パターン6を電気的に接続し、最後に能動素子,受動素
子8等を電気的かつ機械的に保護するための外装樹脂5
で覆う構造となっている。
Next, the electrodes of the active element and the passive element 8 are electrically connected to the wiring pattern 6 of the wiring board 1 by wire bonding using a thin metal wire 9, and finally the active element and the passive element 8 are electrically connected. And exterior resin 5 for mechanical protection
It is structured to cover with.

【0004】[0004]

【発明が解決しようとする課題】この従来の混成集積回
路装置では、配線基板1の材質がガラスエポキシ等有機
材料を用いている理由で、熱伝導率が約0.0004c
al/sec・cm・℃と悪くなり消費電力の大きな、
能動素子,受動素子8等が、熱伝導率の制約上使用でき
ない欠点があった。
In this conventional hybrid integrated circuit device, the thermal conductivity is about 0.0004 c because the wiring board 1 is made of an organic material such as glass epoxy.
al / sec · cm · ° C
There was a disadvantage that the active element, the passive element 8 and the like could not be used due to the restriction of thermal conductivity.

【0005】さらに熱膨張係数が約15〜20×10-6
1/℃の配線基板1に能動素子,受動素子8等を搭載
後、電気的かつ機械的に保護する目的で、熱膨張係数が
約25〜30×10-6の外装樹脂5を用いるため、熱膨
張係数差および外装樹脂5を硬化するときの収縮力等に
より機械歪が生じ配線基板1が反るため表面実装ができ
なくなる欠点がある。
Further, the thermal expansion coefficient is about 15-20 × 10 -6.
After mounting the active element, the passive element 8 and the like on the 1 / ° C. wiring board 1, the exterior resin 5 having a coefficient of thermal expansion of about 25 to 30 × 10 −6 is used for the purpose of electrical and mechanical protection. There is a drawback that mechanical distortion occurs due to a difference in thermal expansion coefficient and a contraction force when the exterior resin 5 is cured, and the wiring substrate 1 warps, so that surface mounting cannot be performed.

【0006】また配線基板1の寸法が大きくなると、こ
の反りはさらに拡大される。その上、能動素子,受動素
子8等は外装樹脂5で電気的かつ機械的に保護されてい
るだけで電気的な外乱ノイズの多い環境で使用する場
合、金属性のシールド板4でノイズ対策をしなければい
けない問題点があった。
When the size of the wiring board 1 is increased, the warpage is further increased. In addition, when the active element and the passive element 8 are used in an environment where there is a lot of electric disturbance noise only by being protected electrically and mechanically by the exterior resin 5, a noise countermeasure is provided by the metallic shield plate 4. There was a problem that had to be done.

【0007】[0007]

【課題を解決するための手段】本発明の混成集積回路装
置は、1個以上の能動素子,受動素子8等を搭載する配
線基板1に於いて、前記配線基板1のダイパッド部分に
金属板10まで達する凹部を用いて固定する構造と金属
板10と一体となる吊りピン3の延長部に金属性シール
ド板4を能動素子,受動素子8側の外装樹脂5面に設け
る構造を備えている。
According to the hybrid integrated circuit device of the present invention, a metal plate 10 is mounted on a die pad portion of the wiring board 1 on which one or more active elements, passive elements 8 and the like are mounted. The structure includes a structure in which the metal shield plate 4 is fixed using a concave portion that reaches to the metal plate 10 and a structure in which a metallic shield plate 4 is provided on the surface of the exterior resin 5 on the active element and passive element 8 side in the extension of the suspension pin 3 integrated with the metal plate 10.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。図1,図2および図3は本発明の一実施例の混成集
積回路装置の平面および断面図である。配線基板1に例
えば、42合金Cu合金等の熱伝導率が約0.04〜
0.4cal/sec・cm・℃の金属板10を多層プ
リント板製造技術で、内層に設け、さらにスルホール電
極2および配線パターン6をプリント基板の電気メッキ
法を用いて約30〜35μm(Cu箔地下を含む)のC
uメッキを施し、さらに金属細線の接合部には約5〜8
μmのNiメッキおよび約0.3〜0.5μmのAuメ
ッキを施す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1, 2 and 3 are a plan view and a sectional view of a hybrid integrated circuit device according to one embodiment of the present invention. For example, the thermal conductivity of the 42 alloy Cu alloy or the like is about 0.04 to
A metal plate 10 of 0.4 cal / sec · cm · ° C. is provided on the inner layer by a multilayer printed board manufacturing technique, and the through-hole electrode 2 and the wiring pattern 6 are formed to a thickness of about 30 to 35 μm (Cu foil) using an electroplating method of a printed board. C (including underground)
u plating, and about 5 to 8
Ni plating of about μm and Au plating of about 0.3 to 0.5 μm are applied.

【0009】次に、能動素子,受動素子8等の搭載部に
凹部を設けることで、金属板10を露出させると共に、
能動素子,受動素子8等を接着剤7を用いて搭載し、約
150〜200℃で加熱硬化させ接合する。
Next, a concave portion is provided in a mounting portion of the active element, the passive element 8 and the like, so that the metal plate 10 is exposed and
The active element, the passive element 8 and the like are mounted using the adhesive 7, and are heated and cured at about 150 to 200 ° C. and joined.

【0010】次に、能動素子受動素子8等と配線パター
ン6とを約φ25〜30μmの金属細線9でワイヤボン
ディング法により電気的に接合した後、ポッディングま
たは、トランスファーモールド法等により外装樹脂5を
施し、金属板10と一体となる吊りピン3の延長部に金
属性シールド板4で能動素子,受動素子8等の外装樹脂
5面を覆うことで電気的な外乱ノイズを約10〜50%
程度遮蔽することができると共に、能動素子,受動素子
8等から不要輻射ノイズで周囲の電子回路,機器に影響
をしないように出来る。よって混成集積回路装置のノイ
ズマージンを著しく向上させることができる。
Next, after the active element passive element 8 and the like and the wiring pattern 6 are electrically connected by a wire bonding method with a thin metal wire 9 having a diameter of about 25 to 30 μm, the exterior resin 5 is formed by a podding or transfer molding method. The external disturbance noise is reduced by about 10 to 50% by covering the surface of the exterior resin 5 such as the active element and the passive element 8 with the metallic shield plate 4 on the extension of the suspension pin 3 integrated with the metal plate 10.
In addition to being able to shield to a certain extent, unnecessary radiation noise from the active element, the passive element 8 and the like does not affect the surrounding electronic circuits and devices. Therefore, the noise margin of the hybrid integrated circuit device can be significantly improved.

【0011】図4は第2の実施例を示す断面図である。
本発明は、金属シールド板4に放熱フィン11を接合
し、放熱効果をさらに良くし、消費電力の大きな、能動
素子,受動素子8等の搭載可能とした。
FIG. 4 is a sectional view showing a second embodiment.
According to the present invention, the heat radiation fins 11 are joined to the metal shield plate 4 to further improve the heat radiation effect, and the active element, the passive element 8 and the like which consume large power can be mounted.

【0012】[0012]

【発明の効果】以上説明したように本発明は、能動素
子,受動素子8等を金属板3に直接接合する構造を有し
ているので、熱伝導率を従来の約0.0004から約
0.04〜0.41/℃と、大巾に小さくすることがで
きるので消費電力の大きな能動素子,受動素子8等を搭
載できるという効果がある。
As described above, the present invention has a structure in which the active element, the passive element 8 and the like are directly joined to the metal plate 3, so that the thermal conductivity is reduced from the conventional value of about 0.0004 to about 0. Since the power consumption can be greatly reduced to 0.04 to 0.41 / ° C., there is an effect that an active element and a passive element 8 having large power consumption can be mounted.

【0013】さらに配線基板1の外装樹脂5等の熱膨張
係数差による熱収縮力に耐える為、配線基板1の反りを
大巾に低減できる。また配線基板1と能動素子,受動素
子8等を金属シールド板4で含うことにより、電気的な
ノイズマージンを著しく向上させることができると共
に、放熱効果も著しく良くなる。
Further, since the wiring board 1 withstands a heat shrinkage force due to a difference in thermal expansion coefficient of the exterior resin 5 and the like, the warpage of the wiring board 1 can be greatly reduced. Further, by including the wiring board 1, the active element, the passive element 8 and the like in the metal shield plate 4, the electric noise margin can be remarkably improved and the heat radiation effect can be remarkably improved.

【0014】さらに、赤外線リフロー等による半田実装
に於いて、外装樹脂5の表面に金属シールド板4を設け
ることにより、赤外線が反射し、外装樹脂5の内部に直
接熱が伝わらないため、熱ショックを大巾に低減でき
る。よって配線基板1および外装樹脂5のクラック等を
防止することができる。
Further, in solder mounting by infrared reflow or the like, by providing the metal shield plate 4 on the surface of the exterior resin 5, infrared rays are reflected and heat is not transmitted directly to the interior of the exterior resin 5. Can be greatly reduced. Therefore, cracks and the like of the wiring board 1 and the exterior resin 5 can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.

【図2】図1のA−A線断面図である。FIG. 2 is a sectional view taken along line AA of FIG.

【図3】図1のB−B線断面図である。FIG. 3 is a sectional view taken along line BB of FIG. 1;

【図4】本発明の他の実施例を示す断面図である。FIG. 4 is a sectional view showing another embodiment of the present invention.

【図5】従来例を示す平面図である。FIG. 5 is a plan view showing a conventional example.

【図6】図5のC−C線断面図である。FIG. 6 is a sectional view taken along line CC of FIG. 5;

【符号の説明】[Explanation of symbols]

1 配線基板 2 スルーホール電極 3 吊りピン 4 金属性シールド板 5 外装樹脂 6 配線パターン 7 接着剤 8 能動素子,受動素子 9 金属細線 10 金属板 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Through-hole electrode 3 Hanging pin 4 Metallic shield plate 5 Outer resin 6 Wiring pattern 7 Adhesive 8 Active element, passive element 9 Fine metal wire 10 Metal plate

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H01L 25/18 ──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. 6 Identification code FI H01L 25/18

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 金属板を有する配線基板と、前記金属板
を露出させる前記配線基板中に設けられた凹部と、前記
金属板上に設けられた能動素子及び受動素子と、前記凹
部を埋める樹脂と、前記樹脂上に設けられた金属シール
ド板と、前記金属板に接続した吊りピンとを有し、前記
吊りピンの延長部が前記配線基板の側面から上面に沿っ
て設けられ前記金属シールド板に接続していることを特
徴とする混成集積回路装置。
1. A wiring board having a metal plate, a recess provided in the wiring board exposing the metal plate, an active element and a passive element provided on the metal plate, and a resin filling the recess. And a metal shield plate provided on the resin, and a suspension pin connected to the metal plate, wherein an extension of the suspension pin is provided along a top surface from a side surface of the wiring board and is provided on the metal shield plate. A hybrid integrated circuit device which is connected.
JP3193357A 1991-08-02 1991-08-02 Hybrid integrated circuit device Expired - Fee Related JP2932772B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3193357A JP2932772B2 (en) 1991-08-02 1991-08-02 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3193357A JP2932772B2 (en) 1991-08-02 1991-08-02 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0536853A JPH0536853A (en) 1993-02-12
JP2932772B2 true JP2932772B2 (en) 1999-08-09

Family

ID=16306569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3193357A Expired - Fee Related JP2932772B2 (en) 1991-08-02 1991-08-02 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JP2932772B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3634735B2 (en) * 2000-10-05 2005-03-30 三洋電機株式会社 Semiconductor device and semiconductor module
CN102820286A (en) * 2012-07-16 2012-12-12 昆山华太电子技术有限公司 Structure for improving performance of passive device of power integrated circuit
WO2017221730A1 (en) * 2016-06-24 2017-12-28 三菱電機株式会社 Power semiconductor device and method for manufacturing power semiconductor device

Also Published As

Publication number Publication date
JPH0536853A (en) 1993-02-12

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