JPH0536299Y2 - - Google Patents
Info
- Publication number
- JPH0536299Y2 JPH0536299Y2 JP10891188U JP10891188U JPH0536299Y2 JP H0536299 Y2 JPH0536299 Y2 JP H0536299Y2 JP 10891188 U JP10891188 U JP 10891188U JP 10891188 U JP10891188 U JP 10891188U JP H0536299 Y2 JPH0536299 Y2 JP H0536299Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip electronic
- electronic component
- printed
- resin
- large chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920005989 resin Polymers 0.000 claims description 20
- 239000011347 resin Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 15
- 230000008646 thermal stress Effects 0.000 description 8
- 239000004020 conductor Substances 0.000 description 3
- 238000007598 dipping method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は絶縁基板上に実装されている各種電子
部品等を樹脂で被覆保護した樹脂封止型混成集積
回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a resin-sealed hybrid integrated circuit in which various electronic components mounted on an insulating substrate are coated and protected with resin.
従来、この種の樹脂封止型混成集積回路は、セ
ラミツク基板等の絶縁基板上に導体配線、および
導体配線電極端、抵抗素子等を印刷成形後、各種
電子部品を搭載してその電極端と前記導体配線電
極端とを、ハンダ付け，ワイヤボンデイング等を
用いて電気的に接続し、しかる後基板全体をフエ
ノール樹脂等の樹脂材料によつて被覆保護してい
る。基板上に搭載される電子部品としては、チツ
プ電子部品の各種開発により、従来のデイスクリ
ート部品が大型チツプ電子部品となり、混成集積
回路にも組込まれつつある。
Conventionally, this type of resin-sealed hybrid integrated circuit has been made by printing conductor wiring, conductor wiring electrode ends, resistive elements, etc. on an insulating substrate such as a ceramic substrate, and then mounting various electronic components on the electrode ends. The ends of the conductor wiring electrodes are electrically connected using soldering, wire bonding, etc., and then the entire board is covered and protected with a resin material such as phenolic resin. With the development of various types of chip electronic components, conventional discrete components have become large-sized chip electronic components and are being incorporated into hybrid integrated circuits as electronic components mounted on substrates.
第２図はこのような大型チツプ電子部品１を絶
縁基板２上に搭載してダイボンデイングペースト
で固着し、外装樹脂３によつて大型チツプ電子部
品１と共に絶縁基板２全体を被覆保護した従来例
を示すもので、この場合抵抗素子４が印刷形成さ
れていると、外装樹脂３の硬化収縮による影響を
防ぐため、大型チツプ電子部品１と印刷抵抗素子
３との距離Ｌを該大型チツプ電子部品１の実装寸
法Ｈの２倍以上はなす必要があつた。 FIG. 2 shows a conventional example in which such a large chip electronic component 1 is mounted on an insulating substrate 2 and fixed with die bonding paste, and the entire insulating substrate 2 together with the large chip electronic component 1 is covered and protected with an exterior resin 3. In this case, if the resistive element 4 is printed, the distance L between the large chip electronic component 1 and the printed resistive element 3 is set to It was necessary to make it more than twice the mounting dimension H of 1.
すなわち、大型チツプ電子部品１はその実装寸
法Ｈが大であるため、外装樹脂３を絶縁基板２の
表面に流動浸漬法または浸漬法により塗布して加
熱乾燥し、大型チツプ電子部品１，印刷抵抗素子
４等を封止する際、外装樹脂３の硬化収縮による
熱ストレスにより印刷抵抗素子４が大型チツプ電
子部品１側に引張られるため、あまり近接しすぎ
ていると大きな熱ストレスを受け絶縁基板２から
剥離したり、クラツクが発生するためである。 That is, since the large chip electronic component 1 has a large mounting dimension H, the exterior resin 3 is coated on the surface of the insulating substrate 2 by a fluidized dipping method or a dipping method, and then heated and dried. When sealing the element 4, etc., the printed resistor element 4 is pulled toward the large chip electronic component 1 side due to thermal stress caused by curing and shrinkage of the exterior resin 3. This is because it may peel off or cause cracks.
然るに、このような従来の樹脂封止型混成集積
回路においては、距離Ｌを大きくとると、実装密
度が低下し、大きな絶縁基板２を必要とするため
不経済で、集積回路自体を小型化できないという
問題があつた。
However, in such conventional resin-sealed hybrid integrated circuits, if the distance L is large, the mounting density decreases, a large insulating substrate 2 is required, which is uneconomical, and the integrated circuit itself cannot be miniaturized. There was a problem.
そこで、外装樹脂３の硬化収縮による熱ストレ
スを吸収する方法として、例えば第３図に示すよ
うにあらかじめ弾性に富んだバツフアコート樹脂
５を大型チツプ電子部品１の周囲に施し、前記距
離Ｌを2H以下にするようにしている。しかし、
この場合はバツフアコート樹脂５の塗布工程が増
えるため、工数がかかりコストアツプになるとい
う欠点があつた。 Therefore, as a method of absorbing the thermal stress caused by curing and shrinkage of the exterior resin 3, for example, as shown in FIG. I try to do that. but,
In this case, the number of steps for applying the buffer coat resin 5 increases, which increases the number of man-hours and increases costs.
したがつて、本考案は上述したような問題点を
解決し、簡単な構成でバツフアコート樹脂で処理
することなく大型チツプ電子部品を印刷抵抗素子
に近接して実装し得るようにした樹脂封止型混成
集積回路を提供することを目的とするものであ
る。 Therefore, the present invention solves the above-mentioned problems and provides a resin-sealed type that allows large chip electronic components to be mounted close to printed resistor elements with a simple structure and without processing with buffer coat resin. The object is to provide a hybrid integrated circuit.
本考案は上記目的を達成するために、絶縁基板
上に印刷抵抗素子を形成すると共にこの印刷抵抗
素子の近傍部に大型チツプ電子部品を実装し、こ
の大型チツプ電子部品と前記印刷抵抗素子との距
離を該大型チツプ電子部品の実装寸法の２倍以下
に設定し、実装寸法が前記大型チツプ電子部品よ
り小さい他のチツプ電子部品を前記大型チツプ電
子部品と前記印刷抵抗素子との間に実装し、かつ
前記絶縁基板，前記両チツプ電子部品および印刷
抵抗素子を外装樹脂によつて被覆保護するように
したものである。
In order to achieve the above object, the present invention forms a printed resistance element on an insulating substrate, mounts a large chip electronic component in the vicinity of the printed resistance element, and connects the large chip electronic component and the printed resistance element. The distance is set to twice or less the mounting dimension of the large chip electronic component, and another chip electronic component whose mounting dimension is smaller than the large chip electronic component is mounted between the large chip electronic component and the printed resistance element. , and the insulating substrate, both chip electronic components, and the printed resistance element are covered and protected with an exterior resin.
本考案において、大型チツプ電子部品と印刷抵
抗素子との間に実装された実装寸法の小さい他の
チツプ電子部品は、外装樹脂の硬化収縮による熱
ストレスを受け、印刷抵抗素子が受ける熱ストレ
スを減少させる。
In the present invention, other small-sized chip electronic components mounted between the large chip electronic component and the printed resistance element are subjected to heat stress due to curing and shrinkage of the exterior resin, reducing the thermal stress that the printed resistance element receives. let
以下、本考案を図面に示す実施例に基づいて詳
細に説明する。
Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.
第１図は本考案に係る樹脂封止型混成集積回路
の一実施例を示す要部断面図である。同図におい
て、本実施例は大型チツプ電子部品１と印刷抵抗
素子４との間に、実装寸法H0が大型チツプ電子
部品１（例えばIC）の実装寸法Ｈより小さい
（H0＜Ｈ）他のチツプ電子部品６（例えばタンタ
ルコンデンサ）を実装し、大型チツプ電子部品１
と印刷抵抗素子４との距離Ｌを2H以下に設定し
たものである。大型チツプ電子部品１の実装寸法
Ｈは５〜６mm程度、他のチツプ電子部品６の実装
寸法H0は１mm以下、印刷抵抗素子４の厚みは数
十μとされる。 FIG. 1 is a sectional view of essential parts showing an embodiment of a resin-sealed hybrid integrated circuit according to the present invention. In the figure, this embodiment has a mounting dimension H 0 smaller than the mounting dimension H of the large chip electronic component 1 (for example, an IC) (H 0 <H) between the large chip electronic component 1 and the printed resistance element 4. A chip electronic component 6 (for example, a tantalum capacitor) is mounted, and a large chip electronic component 1 is mounted.
The distance L between the resistive element 4 and the printed resistive element 4 is set to 2H or less. The mounting dimension H of the large chip electronic component 1 is approximately 5 to 6 mm, the mounting dimension H 0 of the other chip electronic component 6 is 1 mm or less, and the thickness of the printed resistive element 4 is several tens of microns.
かくしてこのような構成からなる樹脂封止型混
成集積回路によれば、大型チツプ電子部品１と他
のチツプ電子部品６との間における外装樹脂３の
硬化収縮による熱ストレスを該他のチツプ電子部
品６が受けるため、印刷抵抗素子４には殆んど作
用しないか、作用しても僅かで、また他のチツプ
電子部品６と印刷抵抗素子４との間における外装
樹脂３の硬化収縮による熱ストレスを該印刷抵抗
素子４が受けるが、この熱ストレスは他のチツプ
電子部品６の実装寸法H0が小さいため僅かであ
る。したがつて、印刷抵抗素子４と大型チツプ電
子部品１との距離Ｌを2H以下に設定しても外装
樹脂３の硬化収縮による熱ストレスにより印刷抵
抗素子４が絶縁基板２から剥離したり、クラツク
が発生したりするのを確実に防止し得る。 Thus, according to the resin-sealed hybrid integrated circuit having such a configuration, thermal stress caused by curing shrinkage of the exterior resin 3 between the large-sized chip electronic component 1 and the other chip electronic component 6 is absorbed by the other chip electronic component. 6, the printed resistance element 4 is hardly affected, or even if it is affected, it is only a small amount, and thermal stress due to curing shrinkage of the exterior resin 3 between the other chip electronic components 6 and the printed resistance element 4 is However, this thermal stress is slight because the mounting dimension H 0 of the other chip electronic components 6 is small. Therefore, even if the distance L between the printed resistive element 4 and the large chip electronic component 1 is set to 2H or less, the printed resistive element 4 may peel off from the insulating substrate 2 or crack due to thermal stress caused by curing and shrinkage of the exterior resin 3. can be reliably prevented from occurring.
以上説明したように本考案に係る樹脂封止型混
成集積回路によれば、絶縁基板上に近接して設け
られる印刷抵抗素子と大型チツプ電子部品との間
に、この大型チツプ電子部品より実装寸法が小さ
い他のチツプ電子部品を実装し、基板全体を外装
樹脂によつて封止するように構成したので、印刷
抵抗素子に作用する外装樹脂の硬化収縮による熱
ストレスを減少させることができ、したがつて印
刷抵抗素子の剥離、クラツク等の発生が少なく、
歩留が良好で品質の安定した混成集積回路を提供
でき、しかもバツフアコート樹脂で処理する必要
がないためコスト低減を実現できる上、大型チツ
プ電子部品と印刷抵抗素子との距離を短縮し得、
回路の小型化を可能にするなど、その実用上の効
果は非常に大である。
As explained above, according to the resin-sealed hybrid integrated circuit according to the present invention, there is a mounting dimension between the printed resistor element and the large chip electronic component, which are provided close to each other on the insulating substrate. Since other chip electronic components with a small chip size are mounted and the entire board is sealed with an exterior resin, it is possible to reduce the thermal stress caused by curing shrinkage of the exterior resin that acts on the printed resistance element. This reduces the occurrence of peeling of printed resistance elements, cracks, etc.
It is possible to provide hybrid integrated circuits with good yields and stable quality, and since there is no need to process with buffer coat resin, it is possible to reduce costs, and the distance between large chip electronic components and printed resistive elements can be shortened.
Its practical effects are extremely large, such as making it possible to miniaturize circuits.
第１図は本考案の一実施例を示す要部断面図、
第２図は従来の樹脂封止型混成集積回路の要部断
面図、第３図はバツフアコート樹脂で処理した樹
脂封止型混成集積回路の従来例を示す要部断面図
である。
１……大型チツプ電子部品、２……絶縁基板、
３……外装樹脂、４……印刷抵抗素子、５……バ
ツフアコート樹脂、６……他のチツプ電子部品。
FIG. 1 is a cross-sectional view of essential parts showing an embodiment of the present invention;
FIG. 2 is a sectional view of a main part of a conventional resin-sealed hybrid integrated circuit, and FIG. 3 is a sectional view of a main part of a conventional example of a resin-sealed hybrid integrated circuit treated with a buffer coat resin. 1...Large chip electronic components, 2...Insulating substrate,
3...Exterior resin, 4...Printed resistance element, 5...Buffer coat resin, 6...Other chip electronic components.
Claims (1)
の印刷抵抗素子の近傍部に大型チツプ電子部品を
実装し、この大型チツプ電子部品と前記印刷抵抗
素子との距離を該大型チツプ電子部品の実装寸法
の２倍以下に設定し、実装寸法が前記大型チツプ
電子部品より小さい他のチツプ電子部品を前記大
型チツプ電子部品と前記印刷抵抗素子との間に実
装し、かつ前記絶縁基板、前記両チツプ電子部品
および印刷抵抗素子を外装樹脂によつて被覆保護
するようにしたことを特徴とする樹脂封止型混成
集積回路。 A printed resistive element is formed on an insulating substrate, and a large chip electronic component is mounted near the printed resistive element, and the distance between this large chip electronic component and the printed resistive element is determined by the mounting dimensions of the large chip electronic component. 2 times or less, and another chip electronic component whose mounting dimensions are smaller than the large chip electronic component is mounted between the large chip electronic component and the printed resistance element, and the insulating substrate and both chip electronic components and a resin-sealed hybrid integrated circuit, characterized in that the printed resistance element is covered and protected by an exterior resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10891188U JPH0536299Y2 (en) | 1988-08-19 | 1988-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10891188U JPH0536299Y2 (en) | 1988-08-19 | 1988-08-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0231176U JPH0231176U (en) | 1990-02-27 |
| JPH0536299Y2 true JPH0536299Y2 (en) | 1993-09-14 |
Family
ID=31344686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10891188U Expired - Lifetime JPH0536299Y2 (en) | 1988-08-19 | 1988-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0536299Y2 (en) |
-
1988
- 1988-08-19 JP JP10891188U patent/JPH0536299Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0231176U (en) | 1990-02-27 |
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