JP2593524Y2 - Hybrid IC - Google Patents
Hybrid ICInfo
- Publication number
- JP2593524Y2 JP2593524Y2 JP1993009122U JP912293U JP2593524Y2 JP 2593524 Y2 JP2593524 Y2 JP 2593524Y2 JP 1993009122 U JP1993009122 U JP 1993009122U JP 912293 U JP912293 U JP 912293U JP 2593524 Y2 JP2593524 Y2 JP 2593524Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductive wiring
- wiring body
- solder
- protective film
- glass protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【0001】[0001]
【産業上の利用分野】この考案はハイブリッドICの温
度サイクル耐量向上を目的とする改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement for improving the temperature cycling capability of a hybrid IC.
【0002】[0002]
【従来の技術】図3に従来のハイブリッドICの特に部
品実装部分の構造を示す。図中1は例えばアルミナのよ
うな材質で構成される絶縁基板を示す。絶縁基板1の上
面に導電配線体2が被着形成される。導電配線体2を形
成した後で絶縁基板1及び導電配線体2の面に湿気等の
侵入を妨ぐために、ガラス保護膜3が形成される。ガラ
ス保護膜3を形成する際に導電配線体2には部品4を接
続するための部品接続面2Aが露出して形成される。部
品接続面2Aに電気部品4のリード4Aが半田5によっ
て接続され、電気部品4が実装される。2. Description of the Related Art FIG. 3 shows a structure of a conventional hybrid IC, particularly a component mounting portion. In FIG. 1, reference numeral 1 denotes an insulating substrate made of a material such as alumina. The conductive wiring body 2 is formed on the upper surface of the insulating substrate 1. After the conductive wiring body 2 is formed, a glass protective film 3 is formed on the surfaces of the insulating substrate 1 and the conductive wiring body 2 in order to prevent moisture or the like from entering. When the glass protective film 3 is formed, a component connection surface 2A for connecting the component 4 is formed on the conductive wiring body 2 so as to be exposed. The lead 4A of the electric component 4 is connected to the component connection surface 2A by the solder 5, and the electric component 4 is mounted.
【0003】[0003]
【考案が解決しようとする課題】電気部品4は通電中は
自己発熱によりリード4Aの相互間に外側に拡がる力を
発生し、また電力の供給を断つとリード4Aの相互間に
内向に向う力を発生する。従って電源のオン、オフの繰
返しに伴なって導電配線体2は電気部品4から応力を受
ける。特に図4に拡大して示すようにガラス保護膜3と
半田5との境界部分で応力集中が起り、この部分にクラ
ック6が発生し、クラック6の発生後導体破断にいたる
事故が起きることが多い。The electric component 4 generates a force that spreads outward between the leads 4A due to self-heating during energization, and an inward force between the leads 4A when power supply is cut off. Occurs. Therefore, the conductive wiring 2 receives stress from the electric component 4 as the power supply is repeatedly turned on and off. In particular, as shown in an enlarged manner in FIG. 4, stress concentration occurs at a boundary portion between the glass protective film 3 and the solder 5, a crack 6 is generated in this portion, and an accident leading to conductor breakage after the crack 6 occurs may occur. Many.
【0004】クラック発生のメカニズムは以下のように
考えられる。つまり、ガラスは一般によく知られている
ように硬度が高くかたい。このため電気部品4のリード
4Aから応力が与えられると、ガラス保護膜3はかたく
変形しないから、ガラスで覆われた部分の縁の部分に応
力が集中し、このためにガラス保護膜3の縁の直下にク
ラック6が形成されるものと考えられる。The mechanism of crack generation is considered as follows. In other words, glass has a high hardness as generally known. For this reason, when a stress is applied from the lead 4A of the electric component 4, the glass protective film 3 does not hardly deform, so that the stress concentrates on the edge of the portion covered with the glass. It is considered that a crack 6 is formed immediately below the.
【0005】更に加えて、半田5で覆われた部分の導電
配線体2に半田5の成分が拡散する。また導電配線体2
の成分も半田5に拡散し、相互に合金が生じる。半田5
を構成するスズが例えばAgPd或はAgPt等によっ
て形成された導電配線体2に拡散すると、導電配線体2
の体積が膨張し、材質がもろい性能に変質する現象が見
られ、この現象によってもクラック6が発生し易くなる
ものと考えられる。[0005] In addition, the components of the solder 5 diffuse into the portion of the conductive wiring body 2 covered with the solder 5. In addition, the conductive wiring body 2
Is also diffused into the solder 5 to form an alloy with each other. Solder 5
Is diffused into the conductive wiring body 2 formed of, for example, AgPd or AgPt, the conductive wiring body 2
A phenomenon is seen in which the volume expands and the quality of the material changes to fragile performance, and it is considered that the crack 6 is also likely to occur due to this phenomenon.
【0006】この考案の目的はクラック6の発生を抑制
し、耐久性の高いハイブリッドICを提供しようとする
ものである。An object of the present invention is to suppress the occurrence of cracks 6 and provide a highly durable hybrid IC.
【0007】[0007]
【課題を解決するための手段】この考案では導電配線体
のガラス保護膜3で覆われる部分と、半田で覆われる部
分との間に緩衝帯を設け、この緩衝帯によって導電配線
体の半田で覆われる部分と、ガラス保護膜で覆われる部
分との境界部分に応力が集中して掛ることを抑制するこ
とができる構造としたものである。According to the present invention, a buffer band is provided between a portion of the conductive wiring body covered with the glass protective film 3 and a part of the conductive wiring body covered with the solder. The structure is such that stress can be prevented from being concentrated and applied to the boundary between the portion to be covered and the portion to be covered by the glass protective film.
【0008】この考案によれば導電配線体の部品接続面
とガラス保護膜との間の境界部分に緩衝帯を設けた構造
としたから、部品の膨張、収縮による応力が与えられて
も緩衝帯によって応力が分散されて導電配線体に与えら
れる。よって導電配線体にクラックが発生することがな
い。よって破断事故が起きるおそれがなく、信頼性の高
いハイブリッドICを提供することができる。According to the present invention, a buffer band is provided at the boundary between the component connecting surface of the conductive wiring body and the glass protective film. Therefore, even when a stress due to expansion and contraction of the component is applied, the buffer band is provided. The stress is dispersed and applied to the conductive wiring body. Therefore, no crack occurs in the conductive wiring body. Therefore, there is no possibility that a breakage accident occurs, and a highly reliable hybrid IC can be provided.
【0009】[0009]
【実施例】図1にこの考案の一実施例を示す。この考案
では部品接続部2Aを残して導電配線体2上にガラス保
護膜3を被着して構成されるハイブリッドICにおい
て、導電配線体2の半田5で覆われる部分とガラス保護
膜3で覆われる部分との間に緩衝帯7を設けた構造を特
徴とするものである。FIG. 1 shows an embodiment of the present invention. In the present invention, in a hybrid IC in which a glass protective film 3 is applied on the conductive wiring body 2 while leaving the component connection portion 2A, a portion of the conductive wiring body 2 covered with the solder 5 and a portion covered with the glass protective film 3 are provided. It is characterized by a structure in which a buffer band 7 is provided between a portion to be covered.
【0010】緩衝帯7の形成方法はガラス保護膜3の上
に例えばエポキシ系の耐熱性樹脂層8を印刷により形成
する。この印刷の際に樹脂層8の一部を部品接続面2A
に延長して形成し、導電配線体2の上に樹脂層8を被着
する。導電配線体2の上に被着した樹脂層2によって緩
衝帯7が形成される。つまり樹脂層8を形成した後に部
品4のリード4Aを半田付する。緩衝帯7の寸法として
は、導電配線体2の厚みが例えば12μm程度の場合、
緩衝帯7の寸法Lを導電配線体2の厚みより充分長い2
00〜300μm程度に採ればよい。つまり樹脂層8の
延長量を200〜300μm程度に採ればよいことにな
る。The method of forming the buffer zone 7 is to form, for example, an epoxy-based heat-resistant resin layer 8 on the glass protective film 3 by printing. At the time of this printing, a part of the resin layer 8 is replaced with the component connection surface 2A.
And a resin layer 8 is adhered on the conductive wiring body 2. A buffer band 7 is formed by the resin layer 2 applied on the conductive wiring body 2. That is, after forming the resin layer 8, the leads 4A of the component 4 are soldered. When the thickness of the conductive wiring body 2 is, for example, about 12 μm,
Make the dimension L of the buffer band 7 sufficiently longer than the thickness of the conductive wiring body 2.
The thickness may be about 100 to 300 μm. That is, the extension amount of the resin layer 8 may be set to about 200 to 300 μm.
【0011】[0011]
【考案の効果】このように樹脂層8を導電配線体2に直
接被せて形成した緩衝帯7を設けたことにより、導電配
線体2の半田5を被着させた部分と、樹脂層8を被せた
部分との間に応力が集中して掛ることがない。つまり樹
脂はガラスと比較して硬度が低い、このため外力に対し
てガラスより変形し易い性質を有する。この結果、電気
部品4が熱膨張すると、半田5に接する樹脂層8も応力
に追従して成る程度変形するから、応力が導電配線体2
の延長方向に分散され導電配線体2に局部的に応力が集
中することがない。特に、樹脂層8によって形成される
緩衝帯7を導電配線体2の厚みより充分長い200〜3
00μm程度に採るから、ガラス保護膜3の被着部分に
応力が伝達されることはない。この結果、導電配線体2
にクラックが発生することを防止することができる。As described above, by providing the buffer band 7 formed by directly covering the conductive layer 2 with the resin layer 8, the portion of the conductive layer 2 where the solder 5 is deposited and the resin layer 8 are formed. Stress is not concentrated between the portion and the portion to be covered. That is, the resin has a lower hardness than glass, and therefore has a property of being more easily deformed than glass by external force. As a result, when the electric component 4 thermally expands, the resin layer 8 in contact with the solder 5 also deforms to the extent that it follows the stress.
And the stress is not locally concentrated on the conductive wiring body 2. In particular, formed by the resin layer 8
Make the buffer band 7 200 to 3 sufficiently longer than the thickness of the conductive wiring body 2.
Since it is about 00 μm,
No stress is transmitted. As a result, the conductive wiring body 2
Cracks can be prevented.
【0012】更に、実用中に半田5から導電配線体2に
成分の一部例えばスズが拡散することにより、導電配線
体2の体積が膨張する現象が見られる。この現象により
樹脂層8は図2に拡大して示すように、半田5との接触
部側が持ち上げられ、半田5と樹脂層8との間の機械的
な結合が益々密になるから、電気部品4のリード4Aか
ら与えられる応力によって樹脂層8は、益々容易に変形
し易い状態となる。よってリード4Aから受ける力が導
電配線体2に集中して掛ることがなく、クラックの発生
が抑えられ、温度サイクル耐量の大きいハイブリッドI
Cを提供することができる。Further, a phenomenon is observed in which the volume of the conductive wiring body 2 expands due to the diffusion of a part of the component, for example, tin from the solder 5 to the conductive wiring body 2 during practical use. As a result of this phenomenon, as shown in the enlarged view of FIG. 2, the contact portion of the resin layer 8 with the solder 5 is lifted, and the mechanical connection between the solder 5 and the resin layer 8 is further increased. The resin layer 8 is more easily deformed by the stress applied from the lead 4A of the fourth member 4. Therefore, the force received from the lead 4A is not concentrated on the conductive wiring body 2, so that the generation of cracks is suppressed and the hybrid I having a large temperature cycle resistance is provided.
C can be provided.
【図1】この考案の一実施例を説明するための拡大断面
図。FIG. 1 is an enlarged sectional view for explaining an embodiment of the present invention.
【図2】この考案によるハイブリッドICの実用中に生
じる樹脂層と半田部分の変形状況を説明するための拡大
断面図。FIG. 2 is an enlarged cross-sectional view for explaining a deformation state of a resin layer and a solder portion occurring during practical use of the hybrid IC according to the present invention.
【図3】従来の技術を説明するための断面図。FIG. 3 is a cross-sectional view for explaining a conventional technique.
【図4】従来の技術の問題点を説明するための拡大断面
図。FIG. 4 is an enlarged cross-sectional view for explaining a problem of the related art.
1 絶縁基板 2 導電配線体 3 ガラス保護膜 4 電気部品 4A リード 5 半田 6 クラック 7 緩衝帯 8 樹脂層 DESCRIPTION OF SYMBOLS 1 Insulating board 2 Conductive wiring body 3 Glass protective film 4 Electric component 4A Lead 5 Solder 6 Crack 7 Buffer band 8 Resin layer
Claims (1)
形成され、この導電配線体の上面に部品接続面を残して
ガラス保護膜を被着し、露出された導電配線体に半田に
よって部品の端子を電気的機械的に接続した構造のハイ
ブリッドICにおいて、 上記ガラス保護膜の縁と上記半田との間を上記導電配線
体の厚みより充分長い200〜300μm程度にわたっ
て離して配置し、上記ガラス保護膜と上記半田との被着
部分の間に、上記導電配線体を露出させることなく樹脂
層を被着して構成した緩衝帯を設けた構造とした ことを
特徴とするハイブリッドIC。1. A conductive wiring body is formed in a predetermined shape on an insulating substrate, a glass protective film is applied on the upper surface of the conductive wiring body while leaving a component connection surface, and the exposed conductive wiring body is soldered to the exposed conductive wiring body.
Therefore, the structure of connecting the terminals of the parts electrically and mechanically
In the brid IC, the conductive wiring is provided between the edge of the glass protective film and the solder.
200-300 μm, which is much longer than the thickness of the body
To separate the glass protective film and the solder.
Resin without exposing the conductive wiring body between the parts
A hybrid IC having a structure in which a buffer band formed by applying a layer is provided .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1993009122U JP2593524Y2 (en) | 1993-03-05 | 1993-03-05 | Hybrid IC |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1993009122U JP2593524Y2 (en) | 1993-03-05 | 1993-03-05 | Hybrid IC |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0670279U JPH0670279U (en) | 1994-09-30 |
JP2593524Y2 true JP2593524Y2 (en) | 1999-04-12 |
Family
ID=18528901
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1993009122U Expired - Fee Related JP2593524Y2 (en) | 1993-03-05 | 1993-03-05 | Hybrid IC |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2593524Y2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4682437B2 (en) * | 2001-04-17 | 2011-05-11 | パナソニック株式会社 | Board device |
JP2012221983A (en) * | 2011-04-04 | 2012-11-12 | Murata Mfg Co Ltd | Ceramic substrate |
KR102281457B1 (en) * | 2015-01-13 | 2021-07-27 | 삼성전기주식회사 | Printed circuit board and method of manufacturing the same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2789356B2 (en) * | 1989-09-08 | 1998-08-20 | 北陸電気工業株式会社 | Electronic components |
JPH03116797A (en) * | 1989-09-28 | 1991-05-17 | Matsushita Electric Ind Co Ltd | Thick film surface package circuit |
-
1993
- 1993-03-05 JP JP1993009122U patent/JP2593524Y2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0670279U (en) | 1994-09-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19981124 |
|
LAPS | Cancellation because of no payment of annual fees |