JPH02207559A - Two row parallel multi-terminal terminal hybrid integrated circuit device - Google Patents
Two row parallel multi-terminal terminal hybrid integrated circuit deviceInfo
- Publication number
- JPH02207559A JPH02207559A JP1028136A JP2813689A JPH02207559A JP H02207559 A JPH02207559 A JP H02207559A JP 1028136 A JP1028136 A JP 1028136A JP 2813689 A JP2813689 A JP 2813689A JP H02207559 A JPH02207559 A JP H02207559A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- terminal
- substrate
- silicone resin
- coated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920002050 silicone resin Polymers 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000005011 phenolic resin Substances 0.000 claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 16
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 claims description 8
- 229920001568 phenolic resin Polymers 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 5
- 239000000919 ceramic Substances 0.000 abstract description 4
- 239000003365 glass fiber Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000001771 impaired effect Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920001971 elastomer Polymers 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Landscapes
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は二列並行多端子型混成集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a two-row parallel multi-terminal hybrid integrated circuit device.
この種の混成集積回路装置は耐湿性のために基板の上下
面を樹脂により被覆された構成となっている。しかし、
更に優れた耐湿性が要求されており、例えば端子に応力
が作用した後においても良好な耐湿性を維持することが
必要とされる。This type of hybrid integrated circuit device has a structure in which the upper and lower surfaces of the substrate are coated with resin for moisture resistance. but,
Even better moisture resistance is required, and for example, it is necessary to maintain good moisture resistance even after stress is applied to the terminal.
第５図は従来の二列並行多端子型混成集積回路装置１を
示す。FIG. 5 shows a conventional two-row parallel multi-terminal hybrid integrated circuit device 1. As shown in FIG.
２はセラミック製の基板、３．４はこの上下面に実装さ
れたチップ部品、５．６は基板２の両側に固定された端
子である。2 is a ceramic substrate, 3.4 is a chip component mounted on the upper and lower surfaces of this substrate, and 5.6 is a terminal fixed to both sides of the substrate 2.
７は表面の樹脂層、８は裏面の樹脂層であり、共にフェ
ノール樹脂である。7 is a resin layer on the front surface, and 8 is a resin layer on the back surface, both of which are made of phenol resin.
上記の装置１は、端子５．６を半田付は固定されてプリ
ント基板９上に実装される。The above device 1 is mounted on a printed circuit board 9 with the terminals 5 and 6 fixed by soldering.
プリント基板９が熱等によって反ることがある。 The printed circuit board 9 may warp due to heat or the like.
この場合には、端子５（６）が第６図（Ａ）から（Ｂ）
に示すように引っ張られる。In this case, terminal 5 (6) is
It is pulled as shown.
下面の樹脂はフェノール樹脂であり硬質のものであるた
め、端子５（６）が引っ張られたときに、第６図（Ｂ）
中、符号１０で示すようにクラックが生ずることがある
。The resin on the bottom surface is phenolic resin and is hard, so when the terminal 5 (6) is pulled, the
During this process, cracks may occur as shown by reference numeral 10.
クラック１０が生ずると、水分が侵入して腐食する等の
耐湿性が損なわれ混成集積回路装置１は比較的短期間で
寿命となってしまう。When cracks 10 occur, moisture resistance is impaired due to moisture intrusion and corrosion, and the life of the hybrid integrated circuit device 1 ends in a relatively short period of time.
また、上面についてみると、凹凸を少なくして捺印をし
易くすべく、樹脂層の厚さを厚くすると、樹脂の硬化時
の収縮ストレスが大きくなり、基板２上の膜が剥離した
り、チップ部品３が離脱する虞れもある。Regarding the upper surface, if the thickness of the resin layer is increased in order to reduce unevenness and make it easier to stamp, the shrinkage stress during curing of the resin will increase, which may cause the film on the substrate 2 to peel off or the chip There is also a possibility that part 3 may come off.
本発明は耐湿性の向上を可能とする二列並行多端子型混
成集積回路を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a double-row parallel multi-terminal hybrid integrated circuit that can improve moisture resistance.
本発明は、基板の表面、裏面にチップ部品が実装され、
且つ該基板の表裏面が該チップ部品を覆うように樹脂に
より被覆され、該基板の側縁に沿って端子が二列に並行
に固定された二列並行多端子型混成集積回路装置におい
て、
上記基板の裏面及び周側面をシリコーン樹脂層により被
覆し、
上記基板の表面及び上記のシリコーン樹脂層のうち上記
周側面を覆っている部分をガラス状物質が添加されたフ
ェノール樹脂層により被覆してなる構成としたものであ
る。In the present invention, chip components are mounted on the front and back sides of the board,
Further, in a two-row parallel multi-terminal hybrid integrated circuit device in which the front and back surfaces of the board are coated with resin so as to cover the chip components, and terminals are fixed in two rows in parallel along the side edges of the board, the above-mentioned The back surface and circumferential surface of the substrate are covered with a silicone resin layer, and the surface of the substrate and the portion of the silicone resin layer that covers the circumferential surface is covered with a phenol resin layer to which a glassy substance is added. It is structured as follows.
シリコーン樹脂層は端子の変形に応じて弾性変形し、端
子に外力が作用しても耐湿性を低下させない。The silicone resin layer deforms elastically in accordance with the deformation of the terminal, and does not reduce moisture resistance even if an external force is applied to the terminal.
ガラス状物質が添加されたフェノール樹脂層はシリコー
ン樹脂層との接合界面の密着性を良くし、この部分の耐
湿性を保証する。The phenolic resin layer to which a glassy substance is added improves the adhesion of the bonding interface with the silicone resin layer, ensuring moisture resistance in this area.
また上記のフェノール樹脂層は熱硬化時の収縮量が少な
く且つ熱膨脹係数が小さく、熱硬化時のチップ部品への
影響及び温度変化時の基板への影響を軽減する。Further, the above-mentioned phenolic resin layer has a small amount of shrinkage and a small coefficient of thermal expansion during thermosetting, which reduces the influence on the chip components during thermosetting and the influence on the substrate when temperature changes.
第１図は本発明の一実施例の二列並行多端子型混成集積
回路装置２０を示す。同図中、第５図に示す構成部分と
対応する部分には同一符号を付し、その説明は省略する
。FIG. 1 shows a two-row parallel multi-terminal hybrid integrated circuit device 20 according to an embodiment of the present invention. In the figure, parts corresponding to those shown in FIG. 5 are denoted by the same reference numerals, and their explanations will be omitted.
２１．２２は端子であり、夫々上端側に基板２０を挟む
コ字状部２１ａ、２２ａ、この直ぐ下側に応力吸収のた
めのＬ字状部２１ｂ、２２ｂが形成しである。Terminals 21 and 22 have U-shaped portions 21a and 22a that sandwich the substrate 20 at their upper ends, and L-shaped portions 21b and 22b for stress absorption immediately below these.
この端子２１．２２は、第３図に併せて示すように、コ
？状部２１ａ、２２ａを基板２０に嵌合させてこれを挟
み、ランド２３に半田付けされて取り付けである。These terminals 21 and 22 are connected to the The shaped portions 21a and 22a are fitted onto the substrate 20, sandwiched therebetween, and soldered to the land 23 for installation.
２５はゴム硬度が８０°以下であるシリコーン樹脂層で
あり、基板２の裏面２ａ、更には周側面２ｃを覆って形
成しである。Reference numeral 25 denotes a silicone resin layer having a rubber hardness of 80° or less, and is formed to cover the back surface 2a of the substrate 2 and further the peripheral side surface 2c.
２６はガラスファイバが８０ｖＯＬ％添加されたフェノ
ール樹脂層であり、基板２の表面２ｂ及びシリコーン樹
脂層２５のうち基板２の周側面２ｃを覆っている部分２
５ａを覆って形成しである。Reference numeral 26 denotes a phenol resin layer to which 80 vOL% of glass fiber is added, and a portion 2 of the surface 2b of the substrate 2 and the silicone resin layer 25 that covers the peripheral side surface 2c of the substrate 2.
It is formed to cover 5a.
ここで、上記の各樹脂Ｇ２５．２６を形成する方法につ
いて、第２図を参照して説明する。Here, a method for forming each of the above-mentioned resins G25 and G26 will be explained with reference to FIG. 2.
まｆ１第２図（Ａ）に示すように、表面２ａを上面とし
て、デイスペンサ２７を使用してシリコーン樹脂を塗布
する。As shown in FIG. 2(A), silicone resin is applied using the dispenser 27 with the surface 2a facing upward.
シリコーン樹脂は流動性が良好であり、端子２１．２２
の裏側にも確実に廻り込み、第３図に示すように、端子
２１のコ字状部２１ａを完全に覆い且つ表面張力により
１字状部２１ｂの周りに円錐状部２５ｂを形成し、更に
は周側面２ｃ上も覆う。Silicone resin has good fluidity and terminals 21.22
3, it completely covers the U-shaped portion 21a of the terminal 21 and forms a conical portion 25b around the U-shaped portion 21b due to surface tension. also covers the circumferential side surface 2c.
次に、塗布したシリコーン樹脂を熱硬化させた後、第２
図（Ｂ）に示すように、基板２をガラスファイバが８Ｑ
ＶＯＬ％添加しであるフェノール樹脂液２９に而２ｂと
２０とがつかるようにデイツプし、同図（Ｃ）に示すよ
うに引き上げる。Next, after thermosetting the applied silicone resin, the second
As shown in Figure (B), the substrate 2 is connected to a glass fiber of 8Q.
Then, 2b and 20 were dipped in a phenolic resin liquid 29 containing VOL%, and then pulled up as shown in FIG. 3(C).
これにより、フェノール樹脂液が基板２に被着し熱硬化
され、シリコーン樹脂層２５が表面２ｂを覆って且つ一
部がシリコーン樹脂Ｍ２５を覆って形成される。As a result, the phenol resin liquid adheres to the substrate 2 and is thermally cured, forming a silicone resin layer 25 covering the surface 2b and partially covering the silicone resin M25.
次に、上記のように樹脂層２５．２６が形成された混成
集積回路装置２０の耐湿性について説明する。Next, the moisture resistance of the hybrid integrated circuit device 20 in which the resin layers 25 and 26 are formed as described above will be explained.
Ｏフェノール樹脂層２６及びシリコーン樹脂層２５につ
いて。Regarding the O phenol resin layer 26 and the silicone resin layer 25.
樹脂１１ｆｆ１２６．２５自体が共に耐湿性に優れたも
のである。The resin 11ff126.25 itself has excellent moisture resistance.
Ｏフェノール樹脂層２６とシリコーン樹脂層２５との接
合界面３０．３１について。Regarding the bonding interface 30.31 between the O phenol resin layer 26 and the silicone resin layer 25.
シリコーン樹脂層２５は他の樹脂との密着性が良くなく
、シリコーン樹脂層に重ねて形成された樹脂層は剥離し
易い。The silicone resin layer 25 does not have good adhesion to other resins, and the resin layer formed over the silicone resin layer is likely to peel off.
しかし、デイツプ塗布時において上記のフェノール樹脂
液はガラスファイバが多聞に混入されており、即乾性で
あるため、フェノール樹脂層２６はシリコーン樹脂層２
５のうち周側面２ｃを覆っている部分２５ａと比較的良
好に密着して形成され、剥離しにくい。However, at the time of dip coating, the phenolic resin liquid is mixed with a large amount of glass fiber and dries quickly.
5, it is formed in relatively good contact with the portion 25a covering the peripheral side surface 2c, and is difficult to peel off.
従って、接合界面３０．３１を通っての水分の混入は起
きない。Therefore, no moisture enters through the bonding interface 30.31.
Ｑ端子２１．２２に外力が作用したときの影響について
。About the effect when external force acts on Q terminals 21 and 22.
プリント基板９の反り等により、第４図（Ａ）中端子２
１に矢印六方向の力が作用すると、端子２１は同図（Ｂ
）に示すように１字状部２１ｂが伸びるように屈曲して
応力を吸収する。Due to warping of the printed circuit board 9, etc., the middle terminal 2 in FIG. 4(A)
When a force acts on the terminal 1 in the six directions of the arrows, the terminal 21 moves as shown in the figure (B
), the single-shaped portion 21b is bent to extend and absorb stress.
端子２１を変形させる力は、シリコーン樹脂層２５にも
及ぶ。The force that deforms the terminal 21 also extends to the silicone resin layer 25.
このシリコーン樹脂層２５はゴム硬度が８０”以下のも
のであり、第４図（Ｂ）に示すように端子２１の変形に
追従して弾性変形し、クラックは生じない。This silicone resin layer 25 has a rubber hardness of 80'' or less, and as shown in FIG. 4(B), it is elastically deformed following the deformation of the terminal 21, and no cracks occur.
端子２１が元の状態に復元すると、シリコーン樹脂層２
５も元の状態となる。When the terminal 21 is restored to its original state, the silicone resin layer 2
5 also returns to its original state.
反対側の端子２２に外力が作用したときにも端子２２の
周りのシリコーン樹脂層は上記と同様に弾性変形するだ
けであり、クラックは生じない。Even when an external force acts on the terminal 22 on the opposite side, the silicone resin layer around the terminal 22 only undergoes elastic deformation in the same manner as described above, and no cracks occur.
従って、端子２１．２２に外力が作用しても混成集積回
路装置２０の耐湿性は何ら損なわれず、装置２０は初期
の耐湿性を維持する。Therefore, even if an external force acts on the terminals 21 and 22, the moisture resistance of the hybrid integrated circuit device 20 is not impaired in any way, and the device 20 maintains its initial moisture resistance.
次に、フェノール樹脂層２６が有する耐湿性以外の特性
について説明する。Next, characteristics other than moisture resistance that the phenol resin layer 26 has will be explained.
フェノール樹脂はガラス物質が相当量混入されたもので
あり、熱硬化時の収縮量はガラス状物質が混入されてい
ない場合に比べて格段に少ない。The phenol resin contains a considerable amount of glassy substance mixed in, and the amount of shrinkage during heat curing is much smaller than when no glassy substance is mixed in.
これにより、熱硬化時に、基板２の表面２ｂ上の膜やチ
ップ３が剥離することが起きない。This prevents the film and chip 3 on the surface 2b of the substrate 2 from peeling off during thermosetting.
また上記のフェノール樹脂８１２６はガラス状物質が混
入されていることにより、熱膨脹係数はガラス状物質混
入無しのものに比べて格段に小さく、セラミック基板２
の熱膨脹係数と略近似したものとなっている。In addition, since the above-mentioned phenolic resin 8126 is mixed with a glassy substance, its thermal expansion coefficient is much smaller than that without glassy substance mixed, and the ceramic substrate 2
The coefficient of thermal expansion is approximately similar to that of .
これにより、装！２０の動作時に熱応力が生じに（く、
基板２が割れたり、樹脂層２５にクラックが入ったりす
ることも起きない。This allows you to wear it! Thermal stress occurs during the operation of 20.
Neither the substrate 2 nor the resin layer 25 is cracked.
またフェノール樹脂層２５にはインク捺印が可能である
。Further, ink can be imprinted on the phenol resin layer 25.
更に、フェノール樹脂層２５は硬く保護膜としても十分
に機能する。Furthermore, the phenol resin layer 25 is hard and functions well as a protective film.
次に端子２１．２２について説明する。端子２１は、応
力吸収部分を基板との接続部の直ぐ下側に設けた構成で
ある。Next, the terminals 21 and 22 will be explained. The terminal 21 has a structure in which a stress absorbing portion is provided immediately below the connection portion with the substrate.
これにより、第５図中の端子５のようにストレス吸収部
を端子の途中に設けた場合に比べて、装置２０はスタン
ドオフＨを従来に比べて低くして実装される。As a result, the device 20 is mounted with a standoff H lower than that in the conventional case, compared to a case where a stress absorbing portion is provided in the middle of the terminal as in the case of the terminal 5 in FIG.
以上説明した様に、本発明によれば、シリコーン樹脂層
とフェノール樹脂層との接合界面部分についても耐湿性
を向上させることが出来、且つ端子に外力が作用しても
耐湿性が損なわれることを避けることが出来、耐湿性の
向上を図ることが出来る。As explained above, according to the present invention, it is possible to improve the moisture resistance of the bonding interface between the silicone resin layer and the phenol resin layer, and the moisture resistance is prevented from being impaired even if an external force is applied to the terminal. can be avoided, and moisture resistance can be improved.
また表面の７１ノ一ル樹脂層は、熱硬化時の収縮が小さ
く、チップ部品の剥離等を確実に防止することが出来る
。更には、熱膨脹係数も小さく、基板の熱応力も軽減出
来る。Furthermore, the 71-noll resin layer on the surface has little shrinkage during heat curing, and can reliably prevent chip components from peeling off. Furthermore, the coefficient of thermal expansion is small, and thermal stress on the substrate can be reduced.
第１図は本発明の一実施例の二列並行多端子型混成集積
回路を示す図、
第２図はシリコーン樹脂層及びフェノール樹脂層を形成
する方法を説明する図、
第３図は端子部分のシリコーン樹脂層の形成状態を示す
図、
第４図は端子に外力が作用したときのシリコーン樹脂層
の状態を示す図、
第５図は従来例を示す図、
第６図は第５図の端子に外力が作用したとぎの状態を示
す図である。
図において、
２はセラミック基板、
２ａは裏面、
２ａは表面、
２ｃは周側面、
３．４はチップ部品、
２０は二列並行多端子型混成集積回路装置、２１は端子
、
２１ａはコ字状部、
２２ａはし字状部、
２５はシリコーン樹脂層、
２５ａは周側面を覆っている部分、
２５ｂは円錐状部、
２６はガラス状物質添加フェノール樹脂層、３０．３１
は接合界面
を示す。
特許出願人 富 士 通 株式会社
第１図
第３図
（Ａ）
（Ｃ）
ｆｓＺ図
、夕縛６そト直；２ドブ７ｆｆ詐￥＠し１；ヒＩミーノ
コーシ碑誓用１１都し１トシ１鰍；ｈ！、列１χ−６≧
１第
図
第６図Fig. 1 is a diagram showing a two-row parallel multi-terminal hybrid integrated circuit according to an embodiment of the present invention, Fig. 2 is a diagram illustrating a method for forming a silicone resin layer and a phenolic resin layer, and Fig. 3 is a terminal portion. Figure 4 is a diagram showing the state of the silicone resin layer when an external force is applied to the terminal, Figure 5 is a diagram showing a conventional example, and Figure 6 is a diagram showing the state of the silicone resin layer when an external force is applied to the terminal. FIG. 6 is a diagram showing a state in which an external force is applied to the terminal. In the figure, 2 is a ceramic substrate, 2a is a back surface, 2a is a front surface, 2c is a circumferential surface, 3.4 is a chip component, 20 is a double-row parallel multi-terminal hybrid integrated circuit device, 21 is a terminal, and 21a is a U-shaped 22a is a wedge-shaped portion, 25 is a silicone resin layer, 25a is a portion covering the circumferential side, 25b is a conical portion, 26 is a glassy substance-added phenol resin layer, 30.31
indicates the bonding interface. Patent applicant: Fujitsu Ltd. Figure 1 Figure 3 (A) (C) 1 fish; h! , column 1χ−6≧
Figure 1 Figure 6
Claims (1)
（３、４）が実装され、且つ該基板の表裏面が該チップ
部品を覆うように樹脂により被覆され、該基板の側縁に
沿って端子（２１、２２）が二列に並行に固定された二
列並行多端子型混成集積回路装置において、 上記基板（２）の裏面（２ａ）及び周側面 （２ｃ）をシリコーン樹脂層（２５）により被覆し、 上記基板の表面（２ｂ）及び上記のシリコーン樹脂層（
２５）のうち上記周側面（２ｃ）を覆っでいる部分（２
５ａ）をガラス状物質が添加されたフェノール樹脂層（
２６）により被覆してなる構成の二列並行多端子型混成
集積回路装置。[Claims] Chip components (3, 4) are mounted on the front surface (2b) and back surface (2a) of the substrate (2), and the front and back surfaces of the substrate are coated with resin so as to cover the chip components. , in a two-row parallel multi-terminal hybrid integrated circuit device in which terminals (21, 22) are fixed in two parallel rows along the side edges of the board, the back surface (2a) and the circumferential surface ( 2c) is coated with a silicone resin layer (25), and the surface of the substrate (2b) and the silicone resin layer (25) are coated with a silicone resin layer (25).
25), the part (2
5a) with a phenolic resin layer to which a glassy substance is added (
26) A two-row parallel multi-terminal hybrid integrated circuit device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1028136A JPH0695561B2 (en) | 1989-02-07 | 1989-02-07 | Two-row parallel multi-terminal hybrid integrated circuit device |
| US07/672,786 US5130780A (en) | 1989-02-07 | 1991-03-21 | Dual in-line packaging with improved moisture resistance |
| US07/875,270 US5219795A (en) | 1989-02-07 | 1992-04-28 | Dual in-line packaging and method of producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1028136A JPH0695561B2 (en) | 1989-02-07 | 1989-02-07 | Two-row parallel multi-terminal hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02207559A true JPH02207559A (en) | 1990-08-17 |
| JPH0695561B2 JPH0695561B2 (en) | 1994-11-24 |
Family
ID=12240357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1028136A Expired - Fee Related JPH0695561B2 (en) | 1989-02-07 | 1989-02-07 | Two-row parallel multi-terminal hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0695561B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267507A (en) * | 1992-03-24 | 1993-10-15 | Hitachi Ltd | Formation of protective layer for semiconductor device |
| EP0593148A2 (en) * | 1992-09-15 | 1994-04-20 | Itt Industries, Inc. | Electrical connectors |
| JPWO2007132612A1 (en) * | 2006-05-17 | 2009-09-24 | 株式会社村田製作所 | Composite substrate and manufacturing method thereof |
| JP2012112571A (en) * | 2010-11-24 | 2012-06-14 | Hitachi Appliances Inc | Air conditioner |
| JP2015139956A (en) * | 2014-01-29 | 2015-08-03 | 京セラ株式会社 | Thermal head and thermal printer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020596A (en) * | 1983-07-14 | 1985-02-01 | ニチコン株式会社 | Method of producing hybrid integrated circuit |
| JPS60194550A (en) * | 1984-03-16 | 1985-10-03 | Nec Corp | Hybrid ic |
| JPS6343478U (en) * | 1986-09-04 | 1988-03-23 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5819492A (en) * | 1981-07-27 | 1983-02-04 | Nippon Steel Corp | Surface treated steel plate for easy to open end |
-
1989
- 1989-02-07 JP JP1028136A patent/JPH0695561B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020596A (en) * | 1983-07-14 | 1985-02-01 | ニチコン株式会社 | Method of producing hybrid integrated circuit |
| JPS60194550A (en) * | 1984-03-16 | 1985-10-03 | Nec Corp | Hybrid ic |
| JPS6343478U (en) * | 1986-09-04 | 1988-03-23 |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267507A (en) * | 1992-03-24 | 1993-10-15 | Hitachi Ltd | Formation of protective layer for semiconductor device |
| EP0593148A2 (en) * | 1992-09-15 | 1994-04-20 | Itt Industries, Inc. | Electrical connectors |
| EP0593148A3 (en) * | 1992-09-15 | 1995-05-17 | Itt | Electrical connectors. |
| JPWO2007132612A1 (en) * | 2006-05-17 | 2009-09-24 | 株式会社村田製作所 | Composite substrate and manufacturing method thereof |
| JP4725817B2 (en) * | 2006-05-17 | 2011-07-13 | 株式会社村田製作所 | Manufacturing method of composite substrate |
| JP2012112571A (en) * | 2010-11-24 | 2012-06-14 | Hitachi Appliances Inc | Air conditioner |
| JP2015139956A (en) * | 2014-01-29 | 2015-08-03 | 京セラ株式会社 | Thermal head and thermal printer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0695561B2 (en) | 1994-11-24 |
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