JPS6334277Y2 - - Google Patents
Info
- Publication number
- JPS6334277Y2 JPS6334277Y2 JP1983113008U JP11300883U JPS6334277Y2 JP S6334277 Y2 JPS6334277 Y2 JP S6334277Y2 JP 1983113008 U JP1983113008 U JP 1983113008U JP 11300883 U JP11300883 U JP 11300883U JP S6334277 Y2 JPS6334277 Y2 JP S6334277Y2
- Authority
- JP
- Japan
- Prior art keywords
- adhesive resin
- cap
- wiring conductor
- thick film
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000919 ceramic Substances 0.000 claims description 15
- 239000004840 adhesive resin Substances 0.000 claims description 12
- 229920006223 adhesive resin Polymers 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 3
- 230000002093 peripheral effect Effects 0.000 claims 2
- 239000005357 flat glass Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Casings For Electric Apparatus (AREA)
Description
【考案の詳細な説明】
本考案は、電子部品を搭載した回路基板を接着
樹脂が塗布されたセラミツクキヤツプで封止した
混成集積回路装置に関する。[Detailed Description of the Invention] The present invention relates to a hybrid integrated circuit device in which a circuit board on which electronic components are mounted is sealed with a ceramic cap coated with adhesive resin.
従来のこのような混成集積回路装置は、第１図
ａの断面図に示す様に、電子部品１を搭載した厚
膜回路基板２に、周縁に接着樹脂３が塗布された
箱形のセラミツクキヤツプ４をかぶせ、接着樹脂
３により封止していた。７はリード端子である。 As shown in the cross-sectional view of FIG. 1a, such a conventional hybrid integrated circuit device consists of a thick film circuit board 2 on which an electronic component 1 is mounted, and a box-shaped ceramic cap on which an adhesive resin 3 is applied around the periphery. 4 and sealed with adhesive resin 3. 7 is a lead terminal.
ところが、第１図ａのＡ−Ａ矢視拡大断面を示
す同図ｂのように、セラミツクキヤツプ４と接触
する厚膜回路基板２の表面部分は配線導体５が一
層又は２層構造となつており、そして、配線導体
５と厚膜回路基板２のセラミツク表面との間に段
差があり、セラミツクキヤツプ４で封止した場
合、その段差の影響でセラミツクキヤツプ４に塗
布してある接着樹脂３では段差部にリーク穴８を
生じ、気密性の確保が十分でないという欠点があ
つた。又、この欠点は、厚膜回路基板２の反り、
セラミツクキヤツプ４の反り、接着樹脂３の不適
切な塗布量により顕著となる。 However, as shown in FIG. 1B, which shows an enlarged cross-section taken along the line A-A in FIG. If there is a step between the wiring conductor 5 and the ceramic surface of the thick film circuit board 2, and the ceramic cap 4 is used for sealing, the adhesive resin 3 applied to the ceramic cap 4 will be affected by the step. A leak hole 8 was formed at the stepped portion, and there was a drawback that airtightness was not sufficiently ensured. Moreover, this drawback is caused by warpage of the thick film circuit board 2,
Warping of the ceramic cap 4 and an inappropriate application amount of the adhesive resin 3 become noticeable.
本考案の目的は、このような気密性の問題の解
決された混成集積回路装置を提供することにあ
る。 An object of the present invention is to provide a hybrid integrated circuit device that solves the problem of airtightness.
本考案によれば、配線導体と回路基板表面の段
差を少なくするため、セラミツクキヤツプと接触
する基板の表面部分を保護ガラス又は絶縁ガラス
を印刷した厚膜回路基板を用いて構成した混成集
積回路装置が得られる。 According to the present invention, in order to reduce the level difference between the wiring conductor and the surface of the circuit board, the hybrid integrated circuit device is constructed using a thick film circuit board on which the surface portion of the board that contacts the ceramic cap is printed with protective glass or insulating glass. is obtained.
つぎに本考案を実施例により説明する。 Next, the present invention will be explained with reference to examples.
第２図ａは本考案の一実施例の断面図、同図ｂ
は図ａのＡ−Ａ矢視断面を示す図である。これら
の図において、電子部品１を搭載した回路基板２
に、周縁に接着樹脂３が塗布された箱形のセラミ
ツクキヤンプ４をかぶせて封止している。厚膜回
路基板２のセラミツクキヤツプ４と接触する配線
導体５の部分は、保護ガラス又は絶縁ガラス６が
印刷されている。その部分にセラミツクキヤツプ
４の周縁の接着樹脂３が接触し、加熱により接着
樹脂３を硬化させ封止している。この保護ガラス
や絶縁ガラス６により、セラミツクキヤンプ４の
接触する厚膜回路基板２の表面部分の平担性が確
保でき、気密性が保証できる。 Figure 2a is a sectional view of an embodiment of the present invention, Figure 2b
1 is a diagram showing a cross section taken along the line A-A in FIG. In these figures, a circuit board 2 on which an electronic component 1 is mounted
A box-shaped ceramic cap 4 whose periphery is coated with adhesive resin 3 is placed over and sealed. A protective glass or insulating glass 6 is printed on the portion of the wiring conductor 5 that contacts the ceramic cap 4 of the thick film circuit board 2. The adhesive resin 3 on the periphery of the ceramic cap 4 comes into contact with this portion, and the adhesive resin 3 is cured and sealed by heating. This protective glass or insulating glass 6 makes it possible to ensure the flatness of the surface portion of the thick film circuit board 2 that the ceramic cap 4 comes into contact with, thereby ensuring airtightness.
本考案は、以上説明した様に、厚膜回路基板上
のセラミツクキヤツプと接触する部分に保護ガラ
スや絶縁ガラスを印刷し、平担性を確保し、セラ
ミツクキヤツプによる封止の気密性を確保するこ
とに効果がある。 As explained above, the present invention prints protective glass or insulating glass on the part of the thick film circuit board that contacts the ceramic cap to ensure flatness and ensure the airtightness of the sealing by the ceramic cap. It is particularly effective.
第１図ａは、従来の混成集積回路装置の断面
図、同図ｂは同図ａのＡ−Ａ矢視拡大断面図、第
２図ａは本考案の一実施例の断面図、同図ｂは同
図ａのＡ−Ａ矢視拡大断面図である。
１……電子部品、２……厚膜回路基板、３……
接着樹脂、４……箱形セラミツクキヤツプ、５…
…配線導体、６……保護ガラスまたは絶縁ガラ
ス、７……リード端子、８……リーク穴。
FIG. 1a is a sectional view of a conventional hybrid integrated circuit device, FIG. 1b is an enlarged sectional view taken along the line A-A in FIG. b is an enlarged sectional view taken along the line A-A in FIG. 1...Electronic components, 2...Thick film circuit board, 3...
Adhesive resin, 4... Box-shaped ceramic cap, 5...
... Wiring conductor, 6 ... Protective glass or insulating glass, 7 ... Lead terminal, 8 ... Leak hole.
Claims (1)
上の所定領域に複数個の電子部品を搭載し、該複
数個の電子部品をセラミツクキヤツプをかぶせて
覆い、前記キヤツプの周縁と前記厚膜回路基板と
を接着樹脂で封止し、該基板の端部に前記配線導
体と接続されるリード端子を設けた混成集積回路
装置において、前記配線導体の上面及び側面をふ
くむ前記基板上の接着樹脂封止部に予じめ印刷形
成された平坦な上面を有する保護ガラスまたは絶
縁ガラスを設け、この平坦なガラス面に前記接着
樹脂の塗布されたキヤツプの周縁を接触させ封止
したことを特徴とする混成集積回路装置。 A plurality of electronic components are mounted on a predetermined area on the surface of a thick film circuit board having a wiring conductor on the surface, a ceramic cap is placed over the plurality of electronic components, and the peripheral edge of the cap and the thick film circuit are covered. In a hybrid integrated circuit device in which a substrate is sealed with adhesive resin and lead terminals connected to the wiring conductor are provided at the ends of the substrate, adhesive resin sealing is performed on the substrate including the upper surface and side surfaces of the wiring conductor. A protective glass or an insulating glass having a flat top surface printed in advance is provided on the stop portion, and the peripheral edge of the cap coated with the adhesive resin is brought into contact with the flat glass surface to seal the cap. Hybrid integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11300883U JPS6020146U (en) | 1983-07-20 | 1983-07-20 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11300883U JPS6020146U (en) | 1983-07-20 | 1983-07-20 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6020146U JPS6020146U (en) | 1985-02-12 |
| JPS6334277Y2 true JPS6334277Y2 (en) | 1988-09-12 |
Family
ID=30261764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11300883U Granted JPS6020146U (en) | 1983-07-20 | 1983-07-20 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020146U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6191787B2 (en) * | 2015-01-08 | 2017-09-06 | 株式会社村田製作所 | Method for manufacturing piezoelectric vibration component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54122870A (en) * | 1978-03-17 | 1979-09-22 | Tokyo Shibaura Electric Co | Thick film circuit board |
| JPS5735354A (en) * | 1980-08-13 | 1982-02-25 | Fujitsu Ltd | Sealing method for semiconductor housing container |
-
1983
- 1983-07-20 JP JP11300883U patent/JPS6020146U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54122870A (en) * | 1978-03-17 | 1979-09-22 | Tokyo Shibaura Electric Co | Thick film circuit board |
| JPS5735354A (en) * | 1980-08-13 | 1982-02-25 | Fujitsu Ltd | Sealing method for semiconductor housing container |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6020146U (en) | 1985-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6348183B2 (en) | ||
| JPS6334277Y2 (en) | ||
| JP2001168493A5 (en) | ||
| JP2562812Y2 (en) | Hybrid integrated circuit device | |
| JPH0423343Y2 (en) | ||
| JPS6134632Y2 (en) | ||
| KR900000826Y1 (en) | Package of semiconductor device | |
| JP2578399Y2 (en) | Parallel mounting structure of semiconductor elements | |
| JPS61199051U (en) | ||
| JPH0536300Y2 (en) | ||
| JPS6164146A (en) | Hybrid corresponding element | |
| JPH046209Y2 (en) | ||
| JPH10284828A (en) | Method for packaging hybrid integrated circuit device | |
| JPS629729Y2 (en) | ||
| JPS6314475Y2 (en) | ||
| JPH0536274Y2 (en) | ||
| JPS58158443U (en) | hybrid integrated circuit board | |
| JPH0452621B2 (en) | ||
| JPH032670U (en) | ||
| JPS61121745U (en) | ||
| JPS61180499A (en) | Hybrid ic device | |
| JPS59143070U (en) | integrated circuit board | |
| JPS63140641U (en) | ||
| JPH03106758U (en) | ||
| JPS63155733A (en) | Method for charging semiconductor chip |