JPS63140641U - - Google Patents

Info

Publication number
JPS63140641U
JPS63140641U JP3176687U JP3176687U JPS63140641U JP S63140641 U JPS63140641 U JP S63140641U JP 3176687 U JP3176687 U JP 3176687U JP 3176687 U JP3176687 U JP 3176687U JP S63140641 U JPS63140641 U JP S63140641U
Authority
JP
Japan
Prior art keywords
mounted electronic
coating agent
electronic component
substrate
soft coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3176687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3176687U priority Critical patent/JPS63140641U/ja
Publication of JPS63140641U publication Critical patent/JPS63140641U/ja
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この考案の一実施例を示す半導体装
置の平面図、第2図ないし第4図は従来の半導体
装置を説明するための図であり、第2図Aは、基
板の平面図、同図Bは、その側面図、第3図は、
基板の所定の面搭載型電子部品および外部リード
を配置した状態の平面図、同図Bは、同図BのA
―A線に沿う断面図、第4図は、パウダモールド
を施して完成した半導体装置を示し、同図Aは、
その平面図、同図Bは、その側面図である。 1……基板、2a,2b……導体パターン、3
……面搭載型電子部品。
FIG. 1 is a plan view of a semiconductor device showing an embodiment of this invention, FIGS. 2 to 4 are diagrams for explaining a conventional semiconductor device, and FIG. 2A is a plan view of a substrate. , Figure B is its side view, and Figure 3 is
A plan view of the board with predetermined surface-mounted electronic components and external leads arranged, Figure B is similar to A in Figure B.
-A cross-sectional view taken along line A, Figure 4 shows a semiconductor device completed by powder molding;
Its plan view and Figure B are its side view. 1...Substrate, 2a, 2b...Conductor pattern, 3
...Surface-mounted electronic components.

Claims (1)

【実用新案登録請求の範囲】 (1) 面搭載型電子部品を搭載するため導体パタ
ーンが形成された基板を有し、この基板の導体パ
ターン上に樹脂封止された面搭載型電子部品が搭
載・固着され、この面搭載型電子部品の近傍に軟
質コート剤が塗布され、前記面搭載型電子部品お
よび前記基板全体を樹脂封止してなる半導体装置
。 (2) 前記軟質コート剤は、耐熱性を有し、かつ
硬化反応しないグリース状の軟質コート剤である
実用新案請求の範囲第1項記載の半導体装置。
[Claims for Utility Model Registration] (1) A substrate having a conductive pattern formed thereon for mounting surface-mounted electronic components, and a surface-mounted electronic component sealed with resin is mounted on the conductive pattern of this substrate. - A semiconductor device in which the surface-mounted electronic component and the entire substrate are sealed with a resin, with a soft coating agent applied near the surface-mounted electronic component. (2) The semiconductor device according to claim 1, wherein the soft coating agent is a grease-like soft coating agent that has heat resistance and does not undergo curing reaction.
JP3176687U 1987-03-04 1987-03-04 Pending JPS63140641U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3176687U JPS63140641U (en) 1987-03-04 1987-03-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3176687U JPS63140641U (en) 1987-03-04 1987-03-04

Publications (1)

Publication Number Publication Date
JPS63140641U true JPS63140641U (en) 1988-09-16

Family

ID=30837804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3176687U Pending JPS63140641U (en) 1987-03-04 1987-03-04

Country Status (1)

Country Link
JP (1) JPS63140641U (en)

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