JPS61121745U - - Google Patents

Info

Publication number
JPS61121745U
JPS61121745U JP390585U JP390585U JPS61121745U JP S61121745 U JPS61121745 U JP S61121745U JP 390585 U JP390585 U JP 390585U JP 390585 U JP390585 U JP 390585U JP S61121745 U JPS61121745 U JP S61121745U
Authority
JP
Japan
Prior art keywords
electronic components
integrated circuit
covered
hybrid integrated
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP390585U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP390585U priority Critical patent/JPS61121745U/ja
Publication of JPS61121745U publication Critical patent/JPS61121745U/ja
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の断面図で、aはシ
ングルインラインタイプ、bはデユアルインライ
ンタイプである。第2図は従来の混成集積回路装
置の断面図でaはシングルインラインタイプ、b
はデユアルインラインタイプである。 1……厚膜回路基板、2……電子部品、3……
はんだ、4……外部リード、5……電子部品搭載
側端子部、6……電子部品非搭載側端子部、7…
…シリコン樹脂、8……電極パターン、9……フ
エノール樹脂又はエポキシ樹脂。
FIG. 1 is a sectional view of an embodiment of the present invention, in which a is a single in-line type and b is a dual in-line type. Figure 2 is a cross-sectional view of a conventional hybrid integrated circuit device, where a is a single in-line type and b is a single in-line type.
is a dual inline type. 1... Thick film circuit board, 2... Electronic components, 3...
Solder, 4...External lead, 5...Electronic component mounting side terminal part, 6...Electronic component non-mounting side terminal part, 7...
... Silicone resin, 8 ... Electrode pattern, 9 ... Phenol resin or epoxy resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 厚膜パターンをセラミツク基板の片面に形成し
、電子部品を搭載した外部リードを有する混成集
積回路において、電子部品搭載面をシリコン樹脂
で外装し、電子部品非搭載面の外部リード端子部
をフエノール樹脂又はエポキシ樹脂で塗布したこ
とを特徴とする混成集積回路装置。
In a hybrid integrated circuit in which a thick film pattern is formed on one side of a ceramic substrate and has external leads on which electronic components are mounted, the surface on which electronic components are mounted is covered with silicone resin, and the external lead terminals on the surface where electronic components are not mounted are covered with phenol resin. or a hybrid integrated circuit device characterized in that it is coated with epoxy resin.
JP390585U 1985-01-16 1985-01-16 Pending JPS61121745U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP390585U JPS61121745U (en) 1985-01-16 1985-01-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP390585U JPS61121745U (en) 1985-01-16 1985-01-16

Publications (1)

Publication Number Publication Date
JPS61121745U true JPS61121745U (en) 1986-07-31

Family

ID=30478971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP390585U Pending JPS61121745U (en) 1985-01-16 1985-01-16

Country Status (1)

Country Link
JP (1) JPS61121745U (en)

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