JPS63152272U - - Google Patents

Info

Publication number
JPS63152272U
JPS63152272U JP4358687U JP4358687U JPS63152272U JP S63152272 U JPS63152272 U JP S63152272U JP 4358687 U JP4358687 U JP 4358687U JP 4358687 U JP4358687 U JP 4358687U JP S63152272 U JPS63152272 U JP S63152272U
Authority
JP
Japan
Prior art keywords
lead
main body
wiring board
printed wiring
lead terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4358687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4358687U priority Critical patent/JPS63152272U/ja
Publication of JPS63152272U publication Critical patent/JPS63152272U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案の一実施例の断面図、第2図
は従来の混成集積回路の一例の断面図である。 1…セラミツク基板、2,3…回路素子、4,
4a…樹脂層、5,5a…本体部、6…リード端
子、7…ストツパ。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional hybrid integrated circuit. 1... Ceramic substrate, 2, 3... Circuit element, 4,
4a... Resin layer, 5, 5a... Main body, 6... Lead terminal, 7... Stopper.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁性の基板の両面に回路素子を搭載し外周を
樹脂被覆した本体部と、前記基板面にほぼ垂直な
一方向に導出した少くとも2本のリード端子と、
該リード端子を印刷配線板のリード穴に挿入した
とき前記本体部の表面が前記印刷配線板の表面に
接触しないよう前記リード端子に固着した絶縁性
のストツパとを含むことを特徴とする混成集積回
路。
a main body having circuit elements mounted on both sides of an insulating substrate and the outer periphery covered with resin; at least two lead terminals led out in one direction substantially perpendicular to the surface of the substrate;
and an insulating stopper fixed to the lead terminal so that the surface of the main body portion does not come into contact with the surface of the printed wiring board when the lead terminal is inserted into the lead hole of the printed wiring board. circuit.
JP4358687U 1987-03-24 1987-03-24 Pending JPS63152272U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4358687U JPS63152272U (en) 1987-03-24 1987-03-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4358687U JPS63152272U (en) 1987-03-24 1987-03-24

Publications (1)

Publication Number Publication Date
JPS63152272U true JPS63152272U (en) 1988-10-06

Family

ID=30860582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4358687U Pending JPS63152272U (en) 1987-03-24 1987-03-24

Country Status (1)

Country Link
JP (1) JPS63152272U (en)

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