JPS63152272U - - Google Patents
Info
- Publication number
- JPS63152272U JPS63152272U JP4358687U JP4358687U JPS63152272U JP S63152272 U JPS63152272 U JP S63152272U JP 4358687 U JP4358687 U JP 4358687U JP 4358687 U JP4358687 U JP 4358687U JP S63152272 U JPS63152272 U JP S63152272U
- Authority
- JP
- Japan
- Prior art keywords
- lead
- main body
- wiring board
- printed wiring
- lead terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Description
第１図は、本考案の一実施例の断面図、第２図
は従来の混成集積回路の一例の断面図である。
１…セラミツク基板、２，３…回路素子、４，
４ａ…樹脂層、５，５ａ…本体部、６…リード端
子、７…ストツパ。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional hybrid integrated circuit. 1... Ceramic substrate, 2, 3... Circuit element, 4,
4a... Resin layer, 5, 5a... Main body, 6... Lead terminal, 7... Stopper.
Claims (1)
樹脂被覆した本体部と、前記基板面にほぼ垂直な
一方向に導出した少くとも２本のリード端子と、
該リード端子を印刷配線板のリード穴に挿入した
とき前記本体部の表面が前記印刷配線板の表面に
接触しないよう前記リード端子に固着した絶縁性
のストツパとを含むことを特徴とする混成集積回
路。 a main body having circuit elements mounted on both sides of an insulating substrate and the outer periphery covered with resin; at least two lead terminals led out in one direction substantially perpendicular to the surface of the substrate;
and an insulating stopper fixed to the lead terminal so that the surface of the main body portion does not come into contact with the surface of the printed wiring board when the lead terminal is inserted into the lead hole of the printed wiring board. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4358687U JPS63152272U (en) | 1987-03-24 | 1987-03-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4358687U JPS63152272U (en) | 1987-03-24 | 1987-03-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63152272U true JPS63152272U (en) | 1988-10-06 |
Family
ID=30860582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4358687U Pending JPS63152272U (en) | 1987-03-24 | 1987-03-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63152272U (en) |
-
1987
- 1987-03-24 JP JP4358687U patent/JPS63152272U/ja active Pending