JPH05267507A - Formation of protective layer for semiconductor device - Google Patents
Formation of protective layer for semiconductor deviceInfo
- Publication number
- JPH05267507A JPH05267507A JP4065764A JP6576492A JPH05267507A JP H05267507 A JPH05267507 A JP H05267507A JP 4065764 A JP4065764 A JP 4065764A JP 6576492 A JP6576492 A JP 6576492A JP H05267507 A JPH05267507 A JP H05267507A
- Authority
- JP
- Japan
- Prior art keywords
- protective layer
- semiconductor device
- resin
- layer
- cured
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Epoxy Resins (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子機器に用いる回路
基板に半導体チップを搭載するチップオンボード構造の
半導体装置の保護層の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a protective layer of a semiconductor device having a chip-on-board structure in which a semiconductor chip is mounted on a circuit board used for electronic equipment.
【０００２】[0002]
【従来の技術】近年、半導体の実装密度を上げる目的
で、１個または複数個の半導体チップをプリント回路基
板上に直接ダイおよびワイヤボンディングして樹脂で封
止する、いわゆるチップオンボード技術が注目されるよ
うになってきた。2. Description of the Related Art In recent years, so-called chip-on-board technology, in which one or a plurality of semiconductor chips are directly die-bonded and wire-bonded on a printed circuit board and sealed with resin for the purpose of increasing the packaging density of semiconductors, has been attracting attention. It has started to be done.
【０００３】一方、従来から、半導体チップの保護方法
として、エポキシ樹脂やシリコン樹脂による樹脂のディ
ップコーティング法が主に用いられてきているが、加熱
により封止した樹脂をゲル化し、該ゲル化樹脂の表面層
をさらに紫外線照射によって硬化した半導体装置が提案
されている（特開昭６２−６９５３８号公報）。On the other hand, conventionally, as a method of protecting a semiconductor chip, a resin dip coating method using an epoxy resin or a silicon resin has been mainly used. However, the resin sealed by heating is gelated to form the gelled resin. There is proposed a semiconductor device in which the surface layer is further cured by irradiation with ultraviolet rays (Japanese Patent Laid-Open No. 62-69538).
【０００４】また、半導体チップを２層以上の樹脂の封
止層により封止する方法が記載されている（特開昭６０
−１９６９６１号公報）。これらの方法では、樹脂封止
層をゲル化または完全硬化するために加熱が行われる
が、加熱によって未硬化の樹脂が拡がるのを制御するこ
とが困難で、その結果、封止樹脂層が肉薄となり、信頼
性が低下すると云う問題があった。Further, a method of sealing a semiconductor chip with two or more layers of resin sealing layers has been described (Japanese Patent Laid-Open No. Sho 60).
-196961). In these methods, heating is performed in order to gel or completely cure the resin sealing layer, but it is difficult to control the spread of the uncured resin due to heating, and as a result, the sealing resin layer is thin. Therefore, there is a problem that reliability is lowered.
【０００５】こうした問題を解決するため、ガラス布や
ポリアミド紙などの基材にエポキシ樹脂を含浸させた積
層板を半導体チップの樹脂封止部の大きさに打ち抜いた
型枠を当て、ポッティング樹脂が拡がって封止樹脂層が
薄くなるのを抑制する制御板を用いる方法が提案されて
いる（特開平３−１５９１５８号公報）。また、別の方
法として、半導体チップを搭載する回路基板に凹部を設
け、凹部内に半導体チップを搭載した後、樹脂で封止す
る方法が提案されている（特開平３−１６９０５４号公
報）。In order to solve these problems, a laminated board in which a base material such as glass cloth or polyamide paper is impregnated with epoxy resin is punched to the size of the resin sealing portion of the semiconductor chip, and a potting resin is applied. A method using a control plate for suppressing the expansion and thinning of the sealing resin layer has been proposed (JP-A-3-159158). As another method, a method has been proposed in which a circuit board on which a semiconductor chip is mounted is provided with a recess, the semiconductor chip is mounted in the recess, and then sealed with a resin (Japanese Patent Laid-Open No. 3-169054).
【０００６】[0006]
【発明が解決しようとする課題】前記の各従来技術は、
封止樹脂の拡がりによる保護層の厚さの低下を抑制する
にはある程度の効果があるものの、特殊な形状の絶縁基
板や制御板（型枠）が必要となるため、チップオンボー
ドの作成工程が煩雑となる。また、微細部分や複雑な箇
所に搭載された半導体チップの封止には前記型枠の使用
は困難である。The respective prior arts mentioned above are
Although there is some effect in suppressing the reduction in the thickness of the protective layer due to the spread of the sealing resin, a specially shaped insulating substrate and control plate (form) are required, so the chip-on-board manufacturing process Becomes complicated. In addition, it is difficult to use the mold for sealing a semiconductor chip mounted on a fine portion or a complicated portion.
【０００７】本発明の目的は、配線基板の片側または両
側に搭載された半導体チップとそのワイヤボンディング
線を、特殊な型枠等を用いずに、所望の肉厚の保護層を
有する半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device having a semiconductor chip mounted on one side or both sides of a wiring board and a wire bonding wire thereof, which has a protective layer of a desired thickness, without using a special mold or the like. To provide.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置の保
護層の形成方法は、配線基板に搭載した半導体チップと
ワイヤボンディング線を樹脂の保護層を形成した後、樹
脂の硬化条件で硬化処理する際に起こる樹脂保護層の厚
さの低下、拡がり領域の変化を極力防止するものであ
る。そのために、保護層全体を硬化する前に、表面層の
樹脂を硬化することによって、特別な型枠等を使用せず
に、硬化処理時における保護層の形状を保持する方法で
あり、本発明の要旨は次のとおりである。According to a method of forming a protective layer of a semiconductor device of the present invention, a semiconductor chip mounted on a wiring board and a wire bonding wire are formed with a protective layer of resin and then cured under a curing condition of the resin. This is to prevent the decrease in the thickness of the resin protective layer and the change in the spread area as much as possible. Therefore, before curing the entire protective layer, by curing the resin of the surface layer, without using a special mold or the like, is a method of maintaining the shape of the protective layer during the curing treatment, The summary of is as follows.
【０００９】（１）配線基板上に搭載した少なくとも半
導体チップとワイヤボンディング線を樹脂組成物からな
る保護層で埋設する半導体装置の保護層の形成方法にお
いて、前記保護層はその表面層が先に硬化するよう硬化
速度に勾配を持たせた組成物で形成し、最終的に保護層
全体を一体に加熱硬化させることを特徴とする半導体装
置の保護層の形成方法。(1) In a method of forming a protective layer of a semiconductor device, in which at least a semiconductor chip and a wire bonding wire mounted on a wiring board are buried with a protective layer made of a resin composition, the surface layer of the protective layer is first formed. A method for forming a protective layer of a semiconductor device, comprising forming a composition having a curing rate gradient so as to cure, and finally heating and curing the entire protective layer integrally.
【００１０】（２）配線基板上に搭載した少なくとも半
導体チップとワイヤボンディング線を樹脂組成物からな
る保護層で埋設する半導体装置の保護層の形成方法にお
いて、前記保護層として樹脂組成物により第１の保護層
を形成し、その表面に第１の保護層よりも速硬化性の樹
脂組成物により第２の保護層を形成し、第２の保護層を
硬化後、保護層全体を一体に加熱硬化させることを特徴
とする半導体装置の保護層の形成方法。(2) In a method for forming a protective layer of a semiconductor device, in which at least a semiconductor chip and a wire bonding line mounted on a wiring board are buried with a protective layer made of a resin composition, the first protective layer is made of a resin composition. Forming a protective layer, forming a second protective layer on the surface of the resin composition, which is faster curable than the first protective layer, and curing the second protective layer, and then heating the entire protective layer integrally. A method for forming a protective layer of a semiconductor device, which comprises curing.
【００１１】（３）配線基板上に搭載した少なくとも半
導体チップとワイヤボンディング線を樹脂組成物からな
る保護層で埋設する半導体装置の保護層の形成方法にお
いて、前記保護層は樹脂組成物により形成し、かつ、少
なくともその表面層は光照射によって硬化する樹脂組成
物からなり、該表面層を光硬化後、保護層全体を一体に
加熱硬化させることを特徴とする半導体装置の保護層の
形成方法。(3) In a method of forming a protective layer of a semiconductor device, wherein at least a semiconductor chip and a wire bonding wire mounted on a wiring board are buried with a protective layer made of a resin composition, the protective layer is made of a resin composition. A method for forming a protective layer of a semiconductor device, characterized in that at least the surface layer is made of a resin composition which is cured by light irradiation, and the surface layer is photocured and then the entire protective layer is integrally heat-cured.
【００１２】（４）配線基板の両面上に搭載した少なく
とも半導体チップとワイヤボンディング線を樹脂組成物
からなる保護層で埋設する半導体装置の保護層の形成方
法において、前記保護層はその表面層が先に硬化するよ
う硬化速度に勾配を持たせて形成し、両面上のそれぞれ
保護層の表面層を硬化後、保護層全体を一体に加熱硬化
させることを特徴とする半導体装置の保護層の形成方
法。(4) In a method of forming a protective layer of a semiconductor device, wherein at least a semiconductor chip and a wire bonding wire mounted on both sides of a wiring board are embedded with a protective layer made of a resin composition, the surface layer of the protective layer is Formation of a protective layer for a semiconductor device, characterized in that the protective layer is formed with a gradient in curing speed so that it is cured first, and after the surface layers of the protective layers on both sides are cured, the entire protective layer is integrally heat-cured. Method.
【００１３】前記の樹脂組成物からなる保護層は硬化さ
れることによって保護層内部の樹脂の硬化が進み、絶縁
基板との密着性、接着性が高められ、耐熱性も向上する
ため、半導体装置の耐湿信頼性，耐半田耐熱性等の信頼
性を大幅に向上することができる。When the protective layer made of the above resin composition is cured, the resin inside the protective layer is cured, the adhesion and the adhesiveness to the insulating substrate are enhanced, and the heat resistance is also improved. It is possible to greatly improve reliability such as moisture resistance and solder heat resistance.
【００１４】本発明において前記表面層の樹脂組成物を
硬化するとは、表面層から内部に向けて硬化状態が勾配
を有する樹脂層を形成することである。また、硬化が表
面層から内部に向けて連続的に勾配を有するものだけで
なく、硬化状態があまり進んでいない樹脂層の上に硬化
状態が進んでいる樹脂層を積層したような場合も含む。
こうした保護層を形成するには、種々の方法があるが、
本発明では製造工数並びに樹脂保護層の特性や信頼性を
考慮すると、次に示す方法が好ましい。In the present invention, curing the resin composition of the surface layer means forming a resin layer having a curing state having a gradient from the surface layer toward the inside. Moreover, not only the case where the curing has a continuous gradient from the surface layer toward the inside, but also the case where the resin layer in the cured state is laminated on the resin layer in which the cured state is not so advanced is included. ..
There are various methods for forming such a protective layer,
In the present invention, the following method is preferable in consideration of the number of manufacturing steps and the characteristics and reliability of the resin protective layer.
【００１５】まず、室温近辺で粘稠または半固形のポッ
ティング樹脂組成物で所定の厚さを有する第一層を形成
した後、該第一層樹脂よりも速硬化性の樹脂組成物を用
いて第一層の外側を被う第二層をポッティング等の方法
で形成する。この時の第二層の厚さの最小値は、後の硬
化処理で保護層の形状が崩れない程度であれば十分であ
り、保護層としての全厚さの１／２０以上あれば問題な
い。First, a viscous or semi-solid potting resin composition around room temperature is used to form a first layer having a predetermined thickness, and then a resin composition faster curable than the first layer resin is used. A second layer covering the outside of the first layer is formed by a method such as potting. The minimum value of the thickness of the second layer at this time is sufficient as long as the shape of the protective layer does not collapse in the subsequent curing treatment, and there is no problem if it is 1/20 or more of the total thickness of the protective layer. ..
【００１６】上記第二層の樹脂組成物としては、室温あ
るいは第一層の樹脂組成物の軟化温度以下、具体的には
１００℃以下の温度で比較的短時間で硬化するものが好
ましい。また、この方法では第一層と第二層を形成する
樹脂組成物が必ずしも同じである必要はなく、例えば、
第一層は耐湿、耐熱の点で高信頼性のエポキシ樹脂と
し、第二層は室温で短時間に硬化することができるシリ
コン樹脂の組み合わせが考えられる。また、第一層と第
二層の樹脂組成物の主成分が同じでも硬化剤や硬化触媒
の種類や配合量を変えることによって、硬化速度に差を
付与することができることは説明するまでもない。ま
た、樹脂組成物をポッティングする時の温度を第一層よ
りも第二層を高温にすることによって、第二層の硬化を
速める方法をとることも可能である。The resin composition for the second layer is preferably one that cures at room temperature or below the softening temperature of the resin composition for the first layer, specifically below 100 ° C. in a relatively short time. Further, in this method, the resin composition forming the first layer and the second layer need not necessarily be the same, for example,
It is conceivable that the first layer is a highly reliable epoxy resin in terms of moisture resistance and heat resistance, and the second layer is a combination of silicone resins that can be cured at room temperature in a short time. Needless to say, even if the resin composition of the first layer and the resin composition of the second layer are the same, it is possible to give a difference in the curing speed by changing the type and blending amount of the curing agent or curing catalyst. .. It is also possible to adopt a method of accelerating the curing of the second layer by setting the temperature for potting the resin composition to be higher than that of the first layer.
【００１７】前記第一層としては耐湿信頼性や機械強度
に優れるフェノール樹脂硬化型エポキシ樹脂または酸無
水物硬化型エポキシ樹脂を、第二層としては耐湿信頼性
には若干劣るも速硬化性のアミン硬化型エポキシ樹脂を
用いる組合せが好ましい。As the first layer, a phenol resin-curable epoxy resin or an acid anhydride-curable epoxy resin having excellent moisture resistance reliability and mechanical strength is used, and as the second layer, moisture resistance reliability is slightly inferior, but quick curing property is high. Combinations using amine curable epoxy resins are preferred.
【００１８】さらに、耐温度サイクル信頼性を向上する
ために、配線基板の熱膨張率に近い低熱膨張性の無機質
フィラーを配合した樹脂組成物を用いることができる。
この場合、第一層および／または第二層に無機質フィラ
ーを配合することができる。なお、本発明において製造
工数を少なくするためには、保護層としては二層が望ま
しいが、二層以上の保護層の形成も可能である。Further, in order to improve the resistance to temperature cycle, a resin composition containing an inorganic filler having a low thermal expansion coefficient close to that of the wiring board can be used.
In this case, an inorganic filler can be added to the first layer and / or the second layer. In addition, in order to reduce the number of manufacturing steps in the present invention, two protective layers are preferable, but two or more protective layers can be formed.
【００１９】本発明において、表面層から内部に向けて
硬化状態に勾配を有する保護層を形成する別の方法とし
ては、配線基板に搭載した半導チップとワイヤボンディ
ング線を光および熱で硬化する樹脂で埋設した後、ま
ず、光照射によって樹脂表面層の硬化を進め、さらに加
熱硬化することにより保護層を形成する方法がある。こ
の場合の光源としては、装置の簡便さから紫外線が好適
であるが、場合によっては電子線を用いることもでき
る。In the present invention, as another method of forming the protective layer having a gradient in the cured state from the surface layer toward the inside, the semiconductor chip mounted on the wiring board and the wire bonding wire are cured by light and heat. After embedding with a resin, first, there is a method in which the resin surface layer is cured by irradiation with light and further cured by heating to form a protective layer. As the light source in this case, ultraviolet rays are preferable because of the simplicity of the apparatus, but electron beams can also be used in some cases.
【００２０】上記保護層を形成する樹脂組成物として
は、光硬化する樹脂と熱硬化する樹脂の混合物、または
一分子中に光硬化できる官能基と熱硬化できる官能基の
両方を有する樹脂組成物を用いることができる。樹脂組
成物には、一般に光重合開始剤と熱重合触媒が併用され
るが、この時の重合開始機構としてはラジカル、カチオ
ン、アニオン系のどれであっても構わない。例えば、エ
ポキシ樹脂にｐーメトキシベンゼンジアゾニウムヘキサ
フロロホスフェートで代表されるオニウム塩のカチオン
重合系の光重合開始剤と、アミン、フェニルリン酸塩、
イミダゾール系のカチオン、アニオン重合系の熱重合触
媒とを同時に加えることによって、上記目的を達成する
ことができる。紫外線照射によって樹脂の硬化は保護層
の表面で最も進み、内部ほど未硬化となる。このように
して、保護層を形成させた後、熱処理によって全樹脂を
完全硬化する。The resin composition forming the protective layer is a mixture of a photocurable resin and a thermosetting resin, or a resin composition having both a photocurable functional group and a thermosetting functional group in one molecule. Can be used. A photopolymerization initiator and a thermal polymerization catalyst are generally used together in the resin composition, and the polymerization initiation mechanism at this time may be any of radical, cation and anion systems. For example, a cationic photopolymerization initiator of an onium salt represented by p-methoxybenzenediazonium hexafluorophosphate in an epoxy resin, an amine, a phenyl phosphate,
The above object can be achieved by simultaneously adding an imidazole-based cation and an anionic polymerization-based thermal polymerization catalyst. The ultraviolet ray irradiation causes the resin to be hardened most on the surface of the protective layer, and becomes uncured toward the inside. After forming the protective layer in this way, the entire resin is completely cured by heat treatment.
【００２１】また、ベンゾインエチルエーテルなどの紫
外線によってラジカル重合する開始剤を含むアクリレー
ト、メタクリレートまたはエポキシアクリレート樹脂と
通常の熱重合触媒を含むエポキシ樹脂とを混合した組成
物を用いることによって、まず、紫外線硬化のアクリレ
ートやメタクリレート樹脂の表面層を形成し、その後、
熱硬化することによりエポキシ樹脂の硬化を行うことも
可能である。この場合、半導体チップを直接保護するの
はエポキシ樹脂であるため、種々の信頼性を確保するこ
とができる。なお、本方法においても、前記と同様に無
機質フィラーを配合した樹脂組成物を用いることができ
る。Further, by using a composition in which an acrylate, methacrylate or epoxy acrylate resin containing an initiator radically polymerized by ultraviolet rays such as benzoin ethyl ether and an epoxy resin containing a general thermal polymerization catalyst are used, first, Form a surface layer of cured acrylate or methacrylate resin, then
It is also possible to cure the epoxy resin by thermosetting. In this case, since the epoxy resin directly protects the semiconductor chip, various reliability can be secured. In this method as well, a resin composition containing an inorganic filler can be used in the same manner as described above.
【００２２】本発明においては、前記の方法により加熱
硬化処理中に保護層の変形が起こりにくいため、基板の
片側または両側に複数搭載された半導体チップとワイヤ
ボンディング線の保護層を同時に形成することができ
る。In the present invention, since the protective layer is unlikely to be deformed during the heat curing treatment by the above method, it is necessary to simultaneously form a plurality of semiconductor chips mounted on one side or both sides of the substrate and a protective layer for the wire bonding line. You can
【００２３】[0023]
【作用】本発明により前記保護層の形成が特別の型枠等
を用いることなく、熱硬化時の保護層の厚さ、拡がり領
域の変化を抑制できるのは、保護層を形成する樹脂の表
面層の硬化を先に進めるたことによる。According to the present invention, the formation of the protective layer can suppress the change of the thickness and the spread area of the protective layer at the time of thermosetting without using a special mold or the like because the surface of the resin forming the protective layer can be suppressed. This is because the curing of the layer proceeded.
【００２４】なお、保護層の表面は、前記熱硬化中保護
層の形状を保持できる程度に硬化されておれば十分であ
る。従って、完全硬化されていないために、その後の加
熱硬化時にガス成分等が発生しても比較的容易に揮散で
きるので、ボイド等の欠陥の発生を防止でき、半導体装
置の信頼性を高めることができる。It is sufficient that the surface of the protective layer is hardened to the extent that the shape of the protective layer can be maintained during the heat curing. Therefore, since it is not completely cured, even if a gas component or the like is generated during the subsequent heat curing, it can be relatively easily volatilized, so that the occurrence of defects such as voids can be prevented and the reliability of the semiconductor device can be improved. it can.
【００２５】[0025]
【実施例】本発明の実施例を図面を用いて説明する。Embodiments of the present invention will be described with reference to the drawings.
【００２６】〔実施例 １〕図１は本発明の保護層の形
成工程を示す半導体装置の模式断面図である。[Embodiment 1] FIG. 1 is a schematic sectional view of a semiconductor device showing a step of forming a protective layer of the present invention.
【００２７】図１（ａ）に示すように、所定の回路パタ
ーンを有する導体配線１を形成した厚さ１ｍｍの絶縁基
板２のアイランド部３に半導体チップ４をマウントし、
半導体チップ４と配線１をワイヤボンディング線５によ
り接続する。As shown in FIG. 1A, a semiconductor chip 4 is mounted on an island portion 3 of an insulating substrate 2 having a thickness of 1 mm on which a conductor wiring 1 having a predetermined circuit pattern is formed.
The semiconductor chip 4 and the wiring 1 are connected by the wire bonding wire 5.
【００２８】次に、図１（ｂ）に示すように、ビスフェ
ノールＡ型エポキシ樹脂と酸無水物からなるエポキシ樹
脂をポッティングにより、半導体チップ４とワイヤボン
ディング線５とを埋設することにより第１の保護層６を
形成する。この時、ポッティング樹脂は半導体チップと
ワイヤボンディング線を完全に埋設できる形状の保護層
を形成できるよう室温〜１００℃に加温して粘度の調整
を行う。Next, as shown in FIG. 1B, the semiconductor chip 4 and the wire bonding wire 5 are embedded by potting an epoxy resin composed of a bisphenol A type epoxy resin and an acid anhydride to form a first epoxy resin. The protective layer 6 is formed. At this time, the potting resin is heated at room temperature to 100 ° C. to adjust the viscosity so that a protective layer having a shape capable of completely embedding the semiconductor chip and the wire bonding wire can be formed.
【００２９】さらに、図１（ｃ）に示すように、第１の
保護層の樹脂よりも硬化の速いエポキシ樹脂をポッティ
ングして、第１の保護層の上に第２の保護層７を形成す
る。第２の保護層７の硬化が進んだことを確認後、図１
（ｄ）に示すように１５０℃４０分間加熱して保護層全
体を一体に硬化する。Further, as shown in FIG. 1C, an epoxy resin, which cures faster than the resin of the first protective layer, is potted to form the second protective layer 7 on the first protective layer. To do. After confirming that the second protective layer 7 has been hardened, FIG.
As shown in (d), the entire protective layer is integrally cured by heating at 150 ° C. for 40 minutes.
【００３０】このようにして得られた半導体装置は、半
導体チップとワイヤボンディング線とを樹脂層で完全に
埋設した保護層を有し、しかも第１の保護層６が耐湿性
に優れたエポキシ樹脂を用いているため、優れた耐湿信
頼性を有する。The semiconductor device thus obtained has a protective layer in which the semiconductor chip and the wire bonding wire are completely buried in the resin layer, and the first protective layer 6 is an epoxy resin excellent in moisture resistance. Has excellent moisture resistance reliability.
【００３１】〔実施例 ２〕図２は本発明の他の実施例
の保護層の形成工程を示す半導体装置の模式断面図であ
る。[Embodiment 2] FIG. 2 is a schematic sectional view of a semiconductor device showing a step of forming a protective layer according to another embodiment of the present invention.
【００３２】図２（ａ）に示すように、実施例１と同様
に半導体チップ４を絶縁基板２にマウントし、ワイヤボ
ンディング線５を接続する。As shown in FIG. 2A, the semiconductor chip 4 is mounted on the insulating substrate 2 and the wire bonding wire 5 is connected, as in the first embodiment.
【００３３】次に、図２（ｂ）に示すように、イミダゾ
ール系の熱硬化触媒とオニウム塩系の光硬化開始剤とを
含むビスフェノールＡ型エポキシ樹脂をポッティングし
て半導体チップとワイヤボンディング線を埋設し、保護
層８を形成する。これを、図２（ｃ）に示すように、１
Ｗ／ｃｍ2の照射強度で紫外線を３分間照射して保護層
８の表面の硬化を進め紫外線硬化層９を形成する。該紫
外線硬化層９は保護層内部に行くに従って硬化の程度が
低い勾配を有している。その後、図２（ｄ）に示すよう
に、１５０℃４０分間の加熱を行って保護層全体を一体
に硬化する。Next, as shown in FIG. 2 (b), a bisphenol A type epoxy resin containing an imidazole type thermosetting catalyst and an onium salt type photocuring initiator is potted to form a semiconductor chip and a wire bonding wire. Buried and a protective layer 8 is formed. 2 as shown in FIG.
Ultraviolet rays are irradiated for 3 minutes at an irradiation intensity of W / cm 2 to advance the hardening of the surface of the protective layer 8 to form an ultraviolet hardening layer 9. The ultraviolet curable layer 9 has a gradient that the degree of curing is low toward the inside of the protective layer. Then, as shown in FIG. 2D, heating at 150 ° C. for 40 minutes is performed to integrally cure the entire protective layer.
【００３４】このようにして得られた半導体装置は、半
導体チップとワイヤボンディング線とが樹脂からなる保
護層で完全に埋設、保護されており、優れた耐湿信頼性
を有する。In the semiconductor device thus obtained, the semiconductor chip and the wire bonding wire are completely buried and protected by the protective layer made of resin, and have excellent moisture resistance reliability.
【００３５】〔実施例 ３〕実施例２と同様にして絶縁
基板２の両面に半導体チップ４をマウントし、半導体チ
ップとワイヤボンディング線５を接続した。まず、片側
だけを実施例２と同様に紫外線硬化形のポッティング樹
脂を用い埋設して保護層８を形成する。該保護層８に実
施例２と同じ条件で紫外線照射を行い、保護層８の表面
に紫外線硬化層９を形成する。[Embodiment 3] In the same manner as in Embodiment 2, the semiconductor chips 4 were mounted on both surfaces of the insulating substrate 2, and the semiconductor chips and the wire bonding wires 5 were connected. First, the protective layer 8 is formed by embedding only one side using an ultraviolet curing potting resin as in the second embodiment. The protective layer 8 is irradiated with ultraviolet rays under the same conditions as in Example 2 to form an ultraviolet curable layer 9 on the surface of the protective layer 8.
【００３６】次に、配線基板のもう一方の面にマウン
ト、接続された半導体チップとワイヤボンディング線を
前記と同様にして紫外線硬化形のポッティング樹脂を用
いて埋設し保護層を形成して前記と同様に紫外線照射を
行い、保護層８の表面に紫外線硬化層９を形成する。Next, the semiconductor chip and the wire bonding wire mounted and connected to the other surface of the wiring board are embedded in the same manner as described above by using an ultraviolet-curing potting resin to form a protective layer, and the above-mentioned process is performed. Similarly, ultraviolet irradiation is performed to form the ultraviolet curable layer 9 on the surface of the protective layer 8.
【００３７】最後に、全体を１５０℃４０分間、加熱
し、前記保護層を一体に硬化して両面に半導体チップが
マウントされ、ワイヤボンディング線で接続された半導
体装置を得た。該半導体装置は実施例２と同様に優れた
耐湿信頼性を有する。Finally, the whole was heated at 150 ° C. for 40 minutes, the protective layer was integrally cured, semiconductor chips were mounted on both sides, and a semiconductor device connected by wire bonding wires was obtained. The semiconductor device has excellent moisture resistance reliability as in the second embodiment.
【００３８】〔比較例 １〕図３は従来の保護層の形成
方法を示す半導体装置の模式断面図である。Comparative Example 1 FIG. 3 is a schematic sectional view of a semiconductor device showing a conventional method of forming a protective layer.
【００３９】図３（ｂ）に示すように、実施例１と同じ
ビスフェノールＡ型エポキシ樹脂と酸無水物からなるエ
ポキシ樹脂をポッティングして半導体チップ４とワイヤ
ボンディング線５を埋設し、保護層を形成する。その
後、そのまゝ１５０℃４０分間の加熱硬化を行った。得
られた半導体装置は、図３（ｃ）に示すように保護層が
硬化時に流動して広がり、半導体チップ４の表面の一部
とワイヤボンディング線５のループ上部が露出した。As shown in FIG. 3B, the semiconductor chip 4 and the wire bonding wire 5 are embedded by potting the same bisphenol A type epoxy resin as in Example 1 and an epoxy resin composed of an acid anhydride, and a protective layer is formed. Form. After that, heat curing was performed at 150 ° C. for 40 minutes. In the obtained semiconductor device, as shown in FIG. 3C, the protective layer was fluidized and spread during curing, and part of the surface of the semiconductor chip 4 and the upper portion of the loop of the wire bonding wire 5 were exposed.
【００４０】〔比較例 ２〕図４は従来の保護層の他の
形成方法を示す半導体装置の模式断面図である。Comparative Example 2 FIG. 4 is a schematic sectional view of a semiconductor device showing another conventional method for forming a protective layer.
【００４１】図４（ｂ）に示すように、実施例２と同じ
ポッティング樹脂を用いて、半導体チップとワイヤボン
ディング線を埋設し、保護層を形成する。これを、図４
（ｃ）に示すように１１０℃１時間の加熱硬化を行い、
ゲル状の樹脂層を形成する。その後、（ｄ）に示すよう
に、１Ｗ／ｃｍ2の照射強度で３分間紫外線露光を行う
ことによって、保護層表面の硬化を進める。As shown in FIG. 4B, the semiconductor chip and the wire bonding line are buried by using the same potting resin as that used in the second embodiment to form a protective layer. This is shown in FIG.
As shown in (c), heat curing at 110 ° C. for 1 hour
A gel-like resin layer is formed. Thereafter, as shown in (d), ultraviolet rays are exposed at an irradiation intensity of 1 W / cm 2 for 3 minutes, whereby the surface of the protective layer is cured.
【００４２】このようにして得られた半導体装置は、ゲ
ル状樹脂層の形成を行う（ｃ）の工程で既に変形が起
り、チップ上の樹脂層の厚さが初期と比べて、約１／３
と薄くなった。そのため、実施例２で得られた半導体装
置と比べて、８５℃、８５％の高温、高湿信頼性試験に
よる半導体装置の寿命が実施例２のものに比べて約１／
５であった。The semiconductor device thus obtained is already deformed in the step (c) of forming the gel-like resin layer, and the thickness of the resin layer on the chip is about 1 / th of the initial thickness. Three
Became thin. Therefore, compared with the semiconductor device obtained in the second embodiment, the life of the semiconductor device by the high temperature and high humidity reliability test of 85 ° C. and 85% is about 1 / th that of the semiconductor device of the second embodiment.
It was 5.
【００４３】[0043]
【発明の効果】本発明によれば、絶縁配線基板に搭載さ
れた半導体チップとワイヤボンディング線を、所望の厚
さの保護層で保護でき、半導体装置の各種信頼性を向上
することができる。According to the present invention, the semiconductor chip and the wire bonding line mounted on the insulated wiring board can be protected by the protective layer having a desired thickness, and various reliability of the semiconductor device can be improved.
【００４４】また、絶縁基板の両面に搭載された半導体
チップとワイヤボンディング線の保護層の形成が容易に
できる。Further, the semiconductor chips mounted on both surfaces of the insulating substrate and the protective layers for the wire bonding lines can be easily formed.
【００４５】さらにまた、保護層の形成に特殊な枠を用
いなくとも半導体チップに所望の厚さを有する保護層を
容易に形成することができ、チップオンボードの製造工
程が簡単になる。Furthermore, the protective layer having a desired thickness can be easily formed on the semiconductor chip without using a special frame for forming the protective layer, and the manufacturing process of the chip-on-board is simplified.
【００４６】保護層の一体加熱によるあと硬化を行うこ
とにより保護層の特性が向上し、半導体装置の各種信頼
性を向上することができる。By post-curing by integrally heating the protective layer, the characteristics of the protective layer are improved and various reliability of the semiconductor device can be improved.
【図１】実施例１の保護層の形成工程を示す半導体装置
の模式断面図である。FIG. 1 is a schematic cross-sectional view of a semiconductor device showing a process of forming a protective layer of Example 1.
【図２】実施例２の保護層の形成工程を示す半導体装置
の模式断面図である。FIG. 2 is a schematic cross-sectional view of a semiconductor device showing a step of forming a protective layer of Example 2.
【図３】比較例１の保護層の形成工程を示す半導体装置
の模式断面図である。FIG. 3 is a schematic cross-sectional view of a semiconductor device showing a step of forming a protective layer of Comparative Example 1.
【図４】比較例２の保護層の形成工程を示す半導体装置
の模式断面図である。FIG. 4 is a schematic cross-sectional view of a semiconductor device showing a step of forming a protective layer of Comparative Example 2.
１…導体配線層、２…絶縁基板、３…アイランド部、４
…半導体チップ、５…ワイヤボンディング線、６…第１
の保護層、７…第２の保護層、８…保護層、９…紫外線
硬化表面層。1 ... Conductor wiring layer, 2 ... Insulating substrate, 3 ... Island portion, 4
... Semiconductor chip, 5 ... Wire bonding wire, 6 ... First
Protective layer, 7 ... Second protective layer, 8 ... Protective layer, 9 ... UV curable surface layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 石井 利昭 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 鈴木 和弘 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 小角 博義 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 北村 輝夫 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Ishii 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture, Hitachi Research Institute, Ltd. Hitachi Research Laboratory (72) Inventor Hiroyoshi Okazumi 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Institute, Ltd. (72) Inventor Teruo Kitamura 4026 Kuji Town, Hitachi City, Ibaraki Hitachi Research Laboratory, Ltd.
Claims (4)
ップとワイヤボンディング線を樹脂組成物からなる保護
層で埋設する半導体装置の保護層の形成方法において、
前記保護層はその表面層が先に硬化するよう硬化速度に
勾配を持たせた組成物で形成し、最終的に保護層全体を
一体に加熱硬化させることを特徴とする半導体装置の保
護層の形成方法。1. A method for forming a protective layer of a semiconductor device, wherein at least a semiconductor chip mounted on a wiring board and a wire bonding wire are buried with a protective layer made of a resin composition,
The protective layer is formed of a composition having a gradient in curing rate so that the surface layer is cured first, and finally the entire protective layer is integrally heat-cured, which is characterized in that Forming method.
ップとワイヤボンディング線を樹脂組成物からなる保護
層で埋設する半導体装置の保護層の形成方法において、
前記保護層として樹脂組成物により第１の保護層を形成
し、その表面に第１の保護層よりも速硬化性の樹脂組成
物により第２の保護層を形成し、第２の保護層を硬化
後、保護層全体を一体に加熱硬化させることを特徴とす
る半導体装置の保護層の形成方法。2. A method for forming a protective layer of a semiconductor device, wherein at least a semiconductor chip mounted on a wiring board and a wire bonding line are buried with a protective layer made of a resin composition,
A first protective layer is formed of a resin composition as the protective layer, and a second protective layer is formed on the surface of the resin composition which is faster curable than the first protective layer to form a second protective layer. A method for forming a protective layer of a semiconductor device, comprising the step of integrally heating and curing the entire protective layer after curing.
ップとワイヤボンディング線を樹脂組成物からなる保護
層で埋設する半導体装置の保護層の形成方法において、
前記保護層は樹脂組成物により形成し、かつ、少なくと
もその表面層は光照射によって硬化する樹脂組成物から
なり、該表面層を光硬化後、保護層全体を一体に加熱硬
化させることを特徴とする半導体装置の保護層の形成方
法。3. A method for forming a protective layer of a semiconductor device, wherein at least a semiconductor chip and a wire bonding line mounted on a wiring board are embedded with a protective layer made of a resin composition,
The protective layer is formed of a resin composition, and at least the surface layer is made of a resin composition that is cured by light irradiation. After the surface layer is photocured, the entire protective layer is integrally heat-cured. Method for forming protective layer of semiconductor device.
導体チップとワイヤボンディング線を樹脂組成物からな
る保護層で埋設する半導体装置の保護層の形成方法にお
いて、前記保護層はその表面層が先に硬化するよう硬化
速度に勾配を持たせて形成し、両面上のそれぞれ保護層
の表面層を硬化後、保護層全体を一体に加熱硬化させる
ことを特徴とする半導体装置の保護層の形成方法。4. A method for forming a protective layer of a semiconductor device, wherein at least a semiconductor chip and a wire bonding wire mounted on both sides of a wiring board are buried with a protective layer made of a resin composition, wherein the surface layer of the protective layer is first. A method for forming a protective layer for a semiconductor device, characterized in that the protective layer is formed with a gradient in curing speed so that the protective layer on both sides is cured, and then the entire protective layer is integrally heat-cured. ..
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4065764A JP2777500B2 (en) | 1992-03-24 | 1992-03-24 | Method for forming protective layer of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4065764A JP2777500B2 (en) | 1992-03-24 | 1992-03-24 | Method for forming protective layer of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05267507A true JPH05267507A (en) | 1993-10-15 |
| JP2777500B2 JP2777500B2 (en) | 1998-07-16 |
Family
ID=13296418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4065764A Expired - Fee Related JP2777500B2 (en) | 1992-03-24 | 1992-03-24 | Method for forming protective layer of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2777500B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018011116A1 (en) * | 2016-07-11 | 2018-01-18 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. | Method and curable compound for casting electronic components or component groups |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848429A (en) * | 1981-09-17 | 1983-03-22 | Seiko Keiyo Kogyo Kk | Sealing method of semiconductor device |
| JPS61181821A (en) * | 1985-02-07 | 1986-08-14 | Mitsubishi Electric Corp | Liquid resin rendered ultraviolet-curable and sealing of electrical circuit part using same |
| JPS61276332A (en) * | 1985-05-31 | 1986-12-06 | Niles Parts Co Ltd | Coating method for electronic component |
| JPS63168041A (en) * | 1987-01-05 | 1988-07-12 | Hitachi Maxell Ltd | Semiconductor device and manufacture thereof |
| JPH02207559A (en) * | 1989-02-07 | 1990-08-17 | Fujitsu Ltd | Two row parallel multi-terminal terminal hybrid integrated circuit device |
| JPH02280345A (en) * | 1989-03-22 | 1990-11-16 | American Teleph & Telegr Co <Att> | Method of sealing capsule of electronic device and manufacture of hybrid integrated circuit |
-
1992
- 1992-03-24 JP JP4065764A patent/JP2777500B2/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848429A (en) * | 1981-09-17 | 1983-03-22 | Seiko Keiyo Kogyo Kk | Sealing method of semiconductor device |
| JPS61181821A (en) * | 1985-02-07 | 1986-08-14 | Mitsubishi Electric Corp | Liquid resin rendered ultraviolet-curable and sealing of electrical circuit part using same |
| JPS61276332A (en) * | 1985-05-31 | 1986-12-06 | Niles Parts Co Ltd | Coating method for electronic component |
| JPS63168041A (en) * | 1987-01-05 | 1988-07-12 | Hitachi Maxell Ltd | Semiconductor device and manufacture thereof |
| JPH02207559A (en) * | 1989-02-07 | 1990-08-17 | Fujitsu Ltd | Two row parallel multi-terminal terminal hybrid integrated circuit device |
| JPH02280345A (en) * | 1989-03-22 | 1990-11-16 | American Teleph & Telegr Co <Att> | Method of sealing capsule of electronic device and manufacture of hybrid integrated circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018011116A1 (en) * | 2016-07-11 | 2018-01-18 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. | Method and curable compound for casting electronic components or component groups |
| CN109478539A (en) * | 2016-07-11 | 2019-03-15 | 弗劳恩霍夫应用研究促进协会 | The method and hardenable compositions for electronic component or the element group of casting |
| KR20190030684A (en) * | 2016-07-11 | 2019-03-22 | 프라운호퍼 게젤샤프트 쭈르 푀르데룽 데어 안겐반텐 포르슝 에. 베. | METHOD FOR CASTING ELECTRONIC COMPONENT OR COMPONENT GROUP AND CURABLE COMPOUND |
| US10896860B2 (en) | 2016-07-11 | 2021-01-19 | Robert Bosch Gmbh | Method and curable compound for casting electronic components or component groups |
| CN109478539B (en) * | 2016-07-11 | 2022-08-23 | 罗伯特·博世有限公司 | Method for casting electronic components or groups of components and hardenable composition |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2777500B2 (en) | 1998-07-16 |
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