JPS6269538A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPS6269538A
JPS6269538A JP60209509A JP20950985A JPS6269538A JP S6269538 A JPS6269538 A JP S6269538A JP 60209509 A JP60209509 A JP 60209509A JP 20950985 A JP20950985 A JP 20950985A JP S6269538 A JPS6269538 A JP S6269538A
Authority
JP
Japan
Prior art keywords
resin
substrate
semiconductor device
conducting
gel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60209509A
Other languages
Japanese (ja)
Inventor
Keiko Osada
長田　慶子
Hirofumi Fujioka
弘文 藤岡
Tadakatsu Watanabe
渡辺　忠勝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60209509A priority Critical patent/JPS6269538A/en
Publication of JPS6269538A publication Critical patent/JPS6269538A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve a yield rate, by covering a substrate, on which circuit element are mounted, with a mixed resin of thermosetting resin and ultravilet- ray setting resin, heating the resin, decomposing the resin into a gel shaped resin, projecting ultraviolet rays, and hardening the surface layer. CONSTITUTION:A conducting plate 3 is attached to the lower surface of a substrate 1. A conducting pattern 2 is formed on the upper surface. A semiconductor chip 5 is connected to the conducting plate 3 with conducting paste 4 and also connected to the conducting pattern 2 with bonding wires 6. In order to protect such a substrate, the surface is covered with a mixed resin of thermosetting resin and ultraviolet-ray setting resin. The resin is heated and decomposed into a gel shaped resin 8. Then ultraviolet rays (a) are projected and the surface is hardened. Thus, a solid state resin 9 is obtained. In this way, faults such as cracks in the chip 5 and the resin layer and breakdown of the bonding wires can be prevented, and the yield rate can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の歩留りを向上させ、かつ配線パタ
ーンを保護することのできる半導体装置の封止構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sealing structure for semiconductor devices that can improve the yield of semiconductor devices and protect wiring patterns.

〔従来の技術〕[Conventional technology]

一般に半導体チップなどが取付けられ、配線パターンが
形成された回路基板は、耐熱性、耐湿性、耐衝撃性をも
たせるために、合成樹脂などによるボッティングが行な
われる。Generally, circuit boards to which semiconductor chips and the like are attached and wiring patterns formed are bonded with synthetic resin or the like in order to provide heat resistance, moisture resistance, and impact resistance.

第２図は従来の合成樹脂などのボッティングによる樹脂
封止半導体装置の構造を示す図である。FIG. 2 is a diagram showing the structure of a conventional resin-sealed semiconductor device formed by botting with synthetic resin or the like.

図において、１は基板、２は導電パターン、３は導電板
、４は導電性ペースト、５は半導体チップ、６はボンデ
ィングワイヤ、７は封止樹脂である。In the figure, 1 is a substrate, 2 is a conductive pattern, 3 is a conductive plate, 4 is a conductive paste, 5 is a semiconductor chip, 6 is a bonding wire, and 7 is a sealing resin.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の樹脂封止半導体装置は以上のように構成されてお
り、回路基板の封止樹脂としては、例えばエポキシ樹脂
のような耐熱性、耐湿性にすぐれた樹脂が用いられるが
、半導体チ・ノブ（一般にシリコン）との熱膨張係数に
差があり、そのため温度変化に応じてストレスが生じ、
チップ、樹脂層。Conventional resin-sealed semiconductor devices are constructed as described above, and a resin with excellent heat resistance and moisture resistance, such as epoxy resin, is used as the encapsulation resin for the circuit board. There is a difference in the coefficient of thermal expansion with silicon (generally silicon), which causes stress in response to temperature changes.
Chip, resin layer.

あるいはチップ・樹脂間にクランクが発生し、そのすき
まからの水分などの介入により耐湿性が損なわれ、また
、樹脂層自体の熱収縮により応力が生じ、そのためボン
ディングワイヤなどの断線が起こるなどの故障が発生す
るという問題があった。Alternatively, a crank may occur between the chip and the resin, and moisture resistance may be impaired due to moisture entering through the gap, or stress may occur due to thermal contraction of the resin layer itself, resulting in failures such as disconnection of bonding wires, etc. There was a problem that occurred.

本発明は上記のような問題点を解消するためになされた
もので、半導体チップ、封止樹脂層のクランク、あるい
はチップ・樹脂間のクランク、ボンディングワイヤなど
の断線を防止できる樹脂封止半導体装置を提供すること
を目的とする。The present invention has been made to solve the above-mentioned problems, and provides a resin-sealed semiconductor device that can prevent disconnection of semiconductor chips, cranks of sealing resin layers, cranks between chips and resin, bonding wires, etc. The purpose is to provide

〔問題点を解決するための手段〕[Means for solving problems]

本発明にかかる樹脂封止半導体装置は、回路素子を搭載
した半導体基板を熱硬化樹脂と紫外線硬化樹脂との混合
樹脂により被覆し、該混合樹脂を加熱によりゲル化させ
、さらに紫外線照射によりゲル状樹脂の表面層を固体化
したものである。In the resin-sealed semiconductor device according to the present invention, a semiconductor substrate on which a circuit element is mounted is coated with a mixed resin of a thermosetting resin and an ultraviolet curing resin, the mixed resin is gelled by heating, and then gelled by ultraviolet irradiation. This is a solidified surface layer of resin.

〔作用〕[Effect]

この発明においては、回路素子を搭載した半導体基板を
ゲル状樹脂で被覆し、さらにその外側を固体状樹脂で被
覆しているから、半導体チップと封止樹脂の熱膨張係数
の差が小さくなり、外部力１らの熱があっても内部での
ストレスが緩和されて外部に与えるストレスも少なくな
り、さらに外部からの強い応力に耐えることができる。In this invention, the semiconductor substrate on which the circuit element is mounted is coated with a gel-like resin, and the outside thereof is further coated with a solid resin, so that the difference in thermal expansion coefficient between the semiconductor chip and the sealing resin is reduced. Even if there is heat from the external force 1, the internal stress is relaxed and the stress applied to the outside is reduced, and furthermore, it is possible to withstand strong external stress.

〔実施例〕〔Example〕

以下、本発明の一実施例について説明する。 An embodiment of the present invention will be described below.

第１図（ａ）は本発明の一実施例による樹脂封止半導体
装置の製造の主要プロセスを示す図であり、図において
１〜６は第２図と同一のものである。FIG. 1(a) is a diagram showing the main process of manufacturing a resin-sealed semiconductor device according to an embodiment of the present invention, and in the figure, numerals 1 to 6 are the same as those in FIG. 2.

８はゲル状樹脂であり、これは熱硬化によりゲル状とな
る樹脂（例えばシリコンゲル）と紫外線照射により固化
する樹脂（例えば末端にアクリル基を有するポリシロキ
サン）とを混合し、これを加熱することによって得られ
るものである。8 is a gel-like resin, which is made by mixing a resin that becomes gel-like by thermosetting (e.g. silicone gel) and a resin that hardens by ultraviolet irradiation (e.g. polysiloxane having an acrylic group at the end) and heating the mixture. This can be obtained by

また第１図（ｔ＋）は本発明の一実施例による樹脂封止
半導体装置の構造を示す図であり、図中１〜８は第１図
ｉＡ）と同一のものであり、９は樹脂８に数秒間紫外線
照射を行ない、これにより固化された部分である（第１
図（ａｌ参照）。Further, FIG. 1 (t+) is a diagram showing the structure of a resin-sealed semiconductor device according to an embodiment of the present invention, in which 1 to 8 are the same as those in FIG. 1 iA), and 9 is a resin 8 This is the part that is solidified by UV irradiation for several seconds (first
Figure (see al.).

このような本実施例では、樹脂８が弾性力を有したゲル
状態であるため、半導体チップ及び配線パターンを保護
し、ボンディングワイヤ同志の接触を防止するばかりで
なく、外部からの応力などを緩和できる。さらに樹脂Ｎ
９は固体状態であるため、機械的強度にすぐれ、上記ゲ
ル状樹脂８を外部からの強い応力から保護することがで
きる。゛なお、上記実施例では熱硬化樹脂にシリコンゲ
ルを用いたが、これはその耐熱性、耐湿性、耐衝撃性が
使用に播したもので使用環境においてゲル状態を保つこ
とができるものであればいがなるものでもよい。In this embodiment, since the resin 8 is in a gel state with elasticity, it not only protects the semiconductor chip and wiring pattern and prevents bonding wires from coming into contact with each other, but also relieves stress from the outside. can. Furthermore, resin N
Since the resin 9 is in a solid state, it has excellent mechanical strength and can protect the gel-like resin 8 from strong external stress.゛Although silicone gel was used as the thermosetting resin in the above examples, its heat resistance, moisture resistance, and impact resistance are important for use, and it is possible to maintain a gel state in the use environment. It can also be something that causes damage.

また、上記実施例では紫外線硬化樹脂に末端にアクリル
基を有するポリシロキサンを用いたが、これは上記熱硬
化樹脂と良好な条件で混合でき、熱硬化により固化する
ことがなく、紫外線照射により外側から固化できるもの
で、耐熱性、耐湿性、耐衝撃性を損なうものでなければ
いかなるものでもよい。In addition, in the above example, polysiloxane having an acrylic group at the end was used as the ultraviolet curable resin, but this can be mixed with the thermosetting resin described above under good conditions, does not harden due to thermosetting, and can be used on the outside by ultraviolet irradiation. Any material that can be solidified from scratch and that does not impair heat resistance, moisture resistance, and impact resistance may be used.

〔発明、の効果〕〔Effect of the invention〕

以上のように本発明にかかる樹脂封止半導体装置によれ
ば、半導体チップ、配線パターンおよびその他の回路素
子を搭載した半導体基板をゲル状樹脂及び固体状樹脂に
より二重に被覆するようにしたので、半導体チップ、封
止樹脂層のクランクあるいはチップ・樹脂間でのクラン
ク、ボンディングワイヤの断線などの故障を防止するこ
とができ、歩留りを向上できる効果がある。As described above, according to the resin-sealed semiconductor device of the present invention, the semiconductor substrate on which the semiconductor chip, wiring pattern, and other circuit elements are mounted is double coated with the gel-like resin and the solid resin. It is possible to prevent failures such as cranking of the semiconductor chip, the sealing resin layer, cranking between the chip and the resin, and disconnection of the bonding wire, thereby improving the yield.

【図面の簡単な説明】[Brief explanation of drawings]

第１図Ｔａｌは本発明の一実施例による樹脂封止半導体
装置の製造における主要プロセスを示す図、第１図山）
は該樹脂封止半導体装置の構造を示す図、第２図は従来
の樹脂封止半導体装置の構造を示す図である。 図において１は基板、２は導電パターン、３は導電板、
４は導電性ペースト、５は崖導体チップ、６はボンディ
ングワイヤ、８はゲル状樹脂、９は固体状樹脂である。 なお図中同一符号は同−又は相当部分を示す。Figure 1 (Tal) is a diagram showing the main processes in manufacturing a resin-sealed semiconductor device according to an embodiment of the present invention.
2 is a diagram showing the structure of the resin-sealed semiconductor device, and FIG. 2 is a diagram showing the structure of a conventional resin-sealed semiconductor device. In the figure, 1 is a substrate, 2 is a conductive pattern, 3 is a conductive plate,
4 is a conductive paste, 5 is a cliff conductor chip, 6 is a bonding wire, 8 is a gel-like resin, and 9 is a solid resin. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] （１）回路素子を搭載した半導体基板を熱硬化樹脂と紫
外線硬化樹脂との混合樹脂により被覆し、該混合樹脂を
加熱によりゲル状樹脂に変質させ、該ゲル状樹脂の表面
層を紫外線照射により固体状樹脂に変質させてなること
を特徴とする樹脂封止半導体装置。(1) A semiconductor substrate on which a circuit element is mounted is coated with a mixed resin of a thermosetting resin and an ultraviolet curable resin, the mixed resin is transformed into a gel-like resin by heating, and the surface layer of the gel-like resin is irradiated with ultraviolet rays. A resin-sealed semiconductor device characterized by being made of a solid resin.
JP60209509A 1985-09-20 1985-09-20 Resin sealed semiconductor device Pending JPS6269538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60209509A JPS6269538A (en) 1985-09-20 1985-09-20 Resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60209509A JPS6269538A (en) 1985-09-20 1985-09-20 Resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS6269538A true JPS6269538A (en) 1987-03-30

Family

ID=16573975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60209509A Pending JPS6269538A (en) 1985-09-20 1985-09-20 Resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS6269538A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0355898A (en) * 1989-07-25 1991-03-11 Matsushita Electric Ind Co Ltd Electronic circuit module
US5036024A (en) * 1987-07-22 1991-07-30 Toray Silicone Company, Inc. Method of treating a hardened semiconductor resin encapsulated layer with ultraviolet radiation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5036024A (en) * 1987-07-22 1991-07-30 Toray Silicone Company, Inc. Method of treating a hardened semiconductor resin encapsulated layer with ultraviolet radiation
JPH0355898A (en) * 1989-07-25 1991-03-11 Matsushita Electric Ind Co Ltd Electronic circuit module

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