JPS5821850A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPS5821850A JPS5821850A JP56122091A JP12209181A JPS5821850A JP S5821850 A JPS5821850 A JP S5821850A JP 56122091 A JP56122091 A JP 56122091A JP 12209181 A JP12209181 A JP 12209181A JP S5821850 A JPS5821850 A JP S5821850A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- silicon element
- semiconductor device
- sealing resin
- die pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
この発明は、半導体素子の特性劣化や破壊および内部配
線の破断等を防止した樹脂封止型半導体装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed semiconductor device that prevents deterioration and destruction of characteristics of semiconductor elements and breakage of internal wiring.
従来、半導体装置を樹脂封止する場合には次のように行
われていた。すなわち、第1図において、1は回路パタ
ーンが形成されているシリコン素子(半導体素子)、2
は前記シリコン素子1を保持固定する基板(以下ダイパ
ッドという)、3は前記シリコン素子10回路電極から
の配線を接続する外部リード用導体、4は前記シリコン
素子10回路電極と外部リード用導体3とを接続する内
部配線、5は封止用樹脂である。Conventionally, resin sealing of semiconductor devices has been carried out as follows. That is, in FIG. 1, 1 is a silicon element (semiconductor element) on which a circuit pattern is formed, 2
3 is a substrate for holding and fixing the silicon element 1 (hereinafter referred to as die pad); 3 is an external lead conductor for connecting the wiring from the silicon element 10 circuit electrode; 4 is the external lead conductor 3 between the silicon element 10 circuit electrode and the external lead conductor 3; 5 is a sealing resin.
この樹脂封止型半導体装置の樹脂封止は、まず、シリコ
ン素子1をダイパッド2の中央にろう付けし、クリフン
素子1の回路電極と外部リード用導体3とを内部配線4
によって接続し、シリコン素子1.ダイパッド2.内部
配線4.および外部リード用導体3の所要部分を封止用
樹脂5によって封止することにより行われる。To resin-seal this resin-sealed semiconductor device, first, the silicon element 1 is brazed to the center of the die pad 2, and the circuit electrodes of the cliffed element 1 and the external lead conductor 3 are connected to the internal wiring 4.
The silicon element 1. Die pad 2. Internal wiring 4. This is carried out by sealing a required portion of the external lead conductor 3 with a sealing resin 5.
従来の樹脂封止型半導体装置は以上のような工程により
製造されているので、次のような欠点がある。Since conventional resin-sealed semiconductor devices are manufactured through the steps described above, they have the following drawbacks.
第1に、封止用樹脂5の成形時には封止用樹脂5の硬化
にともなう体積収縮によりシリコン素子1および内部配
線4に機械的歪が加わり、これらに過大の内部応力を発
生させる。First, during molding of the sealing resin 5, mechanical strain is applied to the silicon element 1 and the internal wiring 4 due to volumetric contraction as the sealing resin 5 hardens, generating excessive internal stress therein.
第2に、装置使用時のヒートサイクルにより、クリコン
素子1.ダイパッド2.内部配線4.および封止用樹脂
5の各線膨張係数の差異のため、なかでも特に封止用樹
脂5がシリコン素子1および内部配線4に対し過大の熱
応力を発生させる。Second, due to the heat cycle during use of the device, the Cricon element 1. Die pad 2. Internal wiring 4. Due to the difference in linear expansion coefficients of the sealing resin 5 and the sealing resin 5, the sealing resin 5 in particular generates excessive thermal stress on the silicon element 1 and the internal wiring 4.
以上の要因により、シリコン素子1の電気的特性の劣化
、さらにはシリコン素子1の破壊、また内部配線4の破
断な引き起こすなどの欠点があった。Due to the above-mentioned factors, there were disadvantages such as deterioration of the electrical characteristics of the silicon element 1, furthermore, destruction of the silicon element 1 and rupture of the internal wiring 4.
この発明は上記の欠点を除去するため釦なされたもので
、シリコン素子、ダイパッド、および内部配線の各所要
部分を封止用樹脂よりも弾性率の低い樹脂で覆って保護
層を形成し、封止用樹脂の機械的歪が直接それらに加わ
らないよ5Kして、シリコン素子の特性劣化や破壊、ま
た内部配線の破断を防ぎ、信頼性の高い樹脂封止型半導
体装置を提供することを目的としている。以下、この発
明について説明する。This invention was developed to eliminate the above-mentioned drawbacks, and the silicon element, die pad, and internal wiring are covered with a resin having a lower elastic modulus than the sealing resin to form a protective layer. The purpose is to provide highly reliable resin-sealed semiconductor devices by preventing mechanical strain from being directly applied to the sealing resin, thereby preventing deterioration and destruction of silicon elements and rupture of internal wiring. It is said that This invention will be explained below.
第2図はこの発明の一実施例を示す樹脂封止型半導体装
置の断面図である。この製造について説明すると、まず
、シリコン素子1.ダイパッド2゜内部配線4を保護用
樹脂6でσつて保護層を形成し、その後、第1図と同様
な封止用樹脂5で樹脂封止して樹脂封止型半導体装置を
構成する。なお、3は外部リード用導体である。前記保
護用樹脂6は封止用樹脂5よりも弾性率の低い樹脂が用
いられる。FIG. 2 is a sectional view of a resin-sealed semiconductor device showing an embodiment of the present invention. To explain this manufacturing process, first, silicon element 1. A protective layer is formed by coating the die pad 2 and the internal wiring 4 with a protective resin 6, and then resin-sealed with the same sealing resin 5 as shown in FIG. 1 to form a resin-sealed semiconductor device. Note that 3 is a conductor for external leads. As the protective resin 6, a resin having a lower elastic modulus than the sealing resin 5 is used.
このように構成された樹脂封止型半導体装置は次のよう
な利点がある。The resin-sealed semiconductor device configured in this manner has the following advantages.
第1に、封止用樹脂5を所要の形状に成形する際に、硬
化過程で生じる体積収縮歪を封止用樹脂5よりも弾性率
の低い保護用樹脂6によって吸収し、シリコン素子1の
特性劣化や破壊、また内部配線4の破断を防止すること
ができる。First, when molding the sealing resin 5 into a desired shape, the volumetric shrinkage strain that occurs during the curing process is absorbed by the protective resin 6, which has a lower elastic modulus than the sealing resin 5, and the silicon element 1 is Deterioration and destruction of characteristics and breakage of the internal wiring 4 can be prevented.
第2に、本装置をヒートサイクルにかけたとき、シリコ
ン素子1.ダイパッド2.内部配線4.および封止用樹
脂5の各線膨張係数の差異により熱歪が生じるが、特に
ここでシリコン素子1および内部配線4に対する熱応力
の大きな要因となる封止用樹脂5の熱歪を、封止用樹脂
5よりも弾性率の低い保護用樹脂6によって吸収し、シ
リコン素子1の特性劣化や破壊、また内部配線の破断を
防止することができる。Second, when the device is subjected to a heat cycle, silicon elements 1. Die pad 2. Internal wiring 4. Thermal strain occurs due to the difference in the linear expansion coefficients of the sealing resin 5 and the sealing resin 5. In particular, the thermal strain of the sealing resin 5, which is a major cause of thermal stress on the silicon element 1 and the internal wiring 4, is It is absorbed by the protective resin 6, which has a lower elastic modulus than the resin 5, and can prevent characteristic deterioration and destruction of the silicon element 1 and breakage of internal wiring.
第3に、シリコン素子1.ダイパッド2.および内部配
線4を保護用樹脂6で覆い、その後これらを封止用樹脂
5で封止しているため、外部から封止用樹脂5に湿気が
入った場合でもこの保護用樹脂6によってそれ以上の浸
入を阻止し、シリコン素子1の特性劣化を防止すること
ができる。Thirdly, silicon element 1. Die pad 2. Since the internal wiring 4 is covered with the protective resin 6 and then sealed with the sealing resin 5, even if moisture gets into the sealing resin 5 from the outside, this protective resin 6 will prevent moisture from entering. It is possible to prevent the infiltration of the silicon element 1 and prevent deterioration of the characteristics of the silicon element 1.
第3図はこの発明の他の実施例を示すもので、シリコン
素子1.ダイパッド2.および内部配線4を保護用メタ
ルシール7を施して保護層を形成し、その後、封止用樹
脂5で封止したものであり、この方法によって得られた
樹脂封止型半導体装置も第2図の実施例と同様の効果を
奏する。FIG. 3 shows another embodiment of the present invention, in which a silicon element 1. Die pad 2. A protective metal seal 7 is applied to the internal wiring 4 to form a protective layer, and then the resin-sealed semiconductor device obtained by this method is also sealed with a sealing resin 5, as shown in FIG. The same effect as in the embodiment is achieved.
以上詳細に説明したように、この発明による樹脂封止型
半導体装置は、シリコン素子、ダイパッド、および内部
配線に対して保護層を設けたので、これらに直接封止用
樹脂の機械的歪が加わらず、したがって、シリコン素子
の特性劣化や破壊、また内部配線の破断を防止すること
ができ、信頼性の高い樹脂封止型半導体装置が得られる
効果がある。As explained in detail above, the resin-sealed semiconductor device according to the present invention has a protective layer for the silicon element, die pad, and internal wiring, so that the mechanical strain of the encapsulating resin is not directly applied to these. Therefore, it is possible to prevent the deterioration and destruction of the characteristics of the silicon element and the breakage of the internal wiring, and it is possible to obtain a highly reliable resin-sealed semiconductor device.
第1図は従来の樹脂封止型半導体装置の一例を示す断面
図、第2図はこの発明の一実施例を示す樹脂封止型半導
体装置の断面図、第3図はこの発明の他の実施例を示す
樹脂封止型半導体装置の断面図である。
図中、1はシリコン素子、2はダイパッド、3は外部リ
ード用導体、4は内部配線、5は封止用樹脂、6は保護
用樹脂、7は保護用メタルシールである。なお、図中の
同一符号は同一または相当部分を示す。
代理人 葛 野信−(外1名)FIG. 1 is a cross-sectional view showing an example of a conventional resin-sealed semiconductor device, FIG. 2 is a cross-sectional view of a resin-sealed semiconductor device showing an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing an example of a conventional resin-sealed semiconductor device. 1 is a cross-sectional view of a resin-sealed semiconductor device showing an example. In the figure, 1 is a silicon element, 2 is a die pad, 3 is an external lead conductor, 4 is internal wiring, 5 is a sealing resin, 6 is a protective resin, and 7 is a protective metal seal. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent: Nobu Kuzuno (1 other person)
Claims (1)
および一端が前記半導体素子に接続された内部配線に対
し形成された保護層、ならびに前記保護層上に所要の形
状に形成された封止用樹脂とからなることを特徴とする
樹脂封止型半導体装置。A semiconductor element, a protective layer formed on a substrate to which the semiconductor element is attached, and an internal wiring whose one end is connected to the semiconductor element, and a sealing resin formed in a desired shape on the protective layer. A resin-sealed semiconductor device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56122091A JPS5821850A (en) | 1981-08-03 | 1981-08-03 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56122091A JPS5821850A (en) | 1981-08-03 | 1981-08-03 | Resin-sealed semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5821850A true JPS5821850A (en) | 1983-02-08 |
Family
ID=14827423
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56122091A Pending JPS5821850A (en) | 1981-08-03 | 1981-08-03 | Resin-sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5821850A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4746392A (en) * | 1982-12-28 | 1988-05-24 | Gao Gesellschaft Fur Automation Und Organisation Mbh | Method for producing an identification card with an integrated circuit |
JPH0244339U (en) * | 1988-09-20 | 1990-03-27 | ||
US5047834A (en) * | 1989-06-20 | 1991-09-10 | International Business Machines Corporation | High strength low stress encapsulation of interconnected semiconductor devices |
US5192995A (en) * | 1988-08-26 | 1993-03-09 | Semiconductor Energy Laboratory Co., Ltd. | Electric device utilizing antioxidation film between base pad for semiconductor chip and organic encapsulating material |
US5208467A (en) * | 1988-07-28 | 1993-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a film-covered packaged component |
US5438222A (en) * | 1989-08-28 | 1995-08-01 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device with plural pad connection of semiconductor chip to leads |
EP1739740A3 (en) * | 2005-06-30 | 2008-04-09 | Hitachi, Ltd. | Power semiconductor |
JP2015225029A (en) * | 2014-05-29 | 2015-12-14 | 株式会社デンソー | Physical quantity sensor |
JP2016191656A (en) * | 2015-03-31 | 2016-11-10 | 株式会社不二工機 | Pressure sensor |
-
1981
- 1981-08-03 JP JP56122091A patent/JPS5821850A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4746392A (en) * | 1982-12-28 | 1988-05-24 | Gao Gesellschaft Fur Automation Und Organisation Mbh | Method for producing an identification card with an integrated circuit |
US5013900A (en) * | 1982-12-28 | 1991-05-07 | Gao Gesellschaft Fur Automation Und Organisation Mbh | Identification card with integrated circuit |
US5208467A (en) * | 1988-07-28 | 1993-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a film-covered packaged component |
US5192995A (en) * | 1988-08-26 | 1993-03-09 | Semiconductor Energy Laboratory Co., Ltd. | Electric device utilizing antioxidation film between base pad for semiconductor chip and organic encapsulating material |
JPH0244339U (en) * | 1988-09-20 | 1990-03-27 | ||
US5047834A (en) * | 1989-06-20 | 1991-09-10 | International Business Machines Corporation | High strength low stress encapsulation of interconnected semiconductor devices |
US5438222A (en) * | 1989-08-28 | 1995-08-01 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device with plural pad connection of semiconductor chip to leads |
EP1739740A3 (en) * | 2005-06-30 | 2008-04-09 | Hitachi, Ltd. | Power semiconductor |
JP2015225029A (en) * | 2014-05-29 | 2015-12-14 | 株式会社デンソー | Physical quantity sensor |
JP2016191656A (en) * | 2015-03-31 | 2016-11-10 | 株式会社不二工機 | Pressure sensor |
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