JPH07212013A - Manufacture of ball grid array and printed circuit board for ball grid array - Google Patents
Manufacture of ball grid array and printed circuit board for ball grid arrayInfo
- Publication number
- JPH07212013A JPH07212013A JP6023188A JP2318894A JPH07212013A JP H07212013 A JPH07212013 A JP H07212013A JP 6023188 A JP6023188 A JP 6023188A JP 2318894 A JP2318894 A JP 2318894A JP H07212013 A JPH07212013 A JP H07212013A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- ball grid
- circuit board
- printed circuit
- grid array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、集積回路用のボール・
グリッド・アレイ及びボール・グリッド・アレイ用のプ
リント回路基板の製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a ball for an integrated circuit.
The present invention relates to a method for manufacturing a printed circuit board for a grid array and a ball grid array.
【０００２】[0002]
【従来の技術】プリント回路基板の上に導電性接着剤を
用いて集積回路を固定し、集積回路と金メッキされた銅
パターンを金ワイヤを用いて結合し、基板表面の回路は
ヴィア・ホールを通じて基板裏面の回路と接続し、基板
裏面の各回路の末端はアレイ状に配列された球形のハン
ダに接続しているボール・グリッド・アレイはよく知ら
れている。従来のボール・グリッド・アレイの断面図を
図２に示す。このようなボール・グリッド・アレイを製
造するには、ガラス繊維で強化したエポキシ樹脂等の板
の両面に銅箔をラミネートした樹脂基板１に銅箔をエッ
チングすることにより銅パターン２を形成し、信号用ヴ
ィア・ホール３を明け、銅メッキを施すことによって基
板の表裏に回路を形成する。このとき同時に放熱を目的
としたサーマル・ヴィア・ホール４も明けられ銅メッキ
される。基板上の集積回路７を搭載する位置には、通常
サーマル・ヴィア・ホール４が何個か設けられる。次い
でプリント回路基板の片面にドライ・フィルム・レジス
ト６がラミネートされ、露光、現像され、さらに紫外線
照射が繰り返される。基板のもう一方の面にもドライ・
フィルム・レジスト６がラミネートされ、同様に露光、
現像、紫外線照射が行われるが、この間に反対の面上の
レジスト・フィルムはいわゆるオーバー・キュアの状態
となり、基板樹脂との密着性が低下することが多い。プ
リント回路基板は次いで金メッキ工程に送られるが、オ
ーバー・キュアとなり密着力の低下したレジスト・フィ
ルムと基板樹脂の間にメッキ液が浸み込み不良品となる
危険性が大きい。また、このように基板の両面をドライ
・フィルム・レジストで処理したプリント回路基板を用
いて製造した半導体装置は、集積回路の下部のサーマル
・ヴィア・ホールはレジスト・フィルムで覆われている
のみで中空であるので、この部分にピン・ホールが生ず
るとたちどころに水分が侵入し、性能に異常をきたす。
プリント回路基板１上の銅パターン２に金メッキを施し
たのち、集積回路７を導電性接着剤８によりプリント回
路基板に固定し、集積回路７と銅パターン２を金ワイヤ
９により接続し、次いで集積回路を搭載した面をトラン
スファ成形又はポッティングにより樹脂で封止する。封
止樹脂とプリント回路基板上のレジスト・フィルムの密
着性が十分でなく、この間隙から水分が侵入して不良の
原因となることも多い。2. Description of the Related Art An integrated circuit is fixed on a printed circuit board by using a conductive adhesive, and the integrated circuit and a gold-plated copper pattern are bonded by using a gold wire. The circuit on the surface of the board is through a via hole. Ball grid arrays are well known, which are connected to the circuit on the back surface of the substrate, and the ends of each circuit on the back surface of the substrate are connected to spherical solder arranged in an array. A cross-sectional view of a conventional ball grid array is shown in FIG. To manufacture such a ball grid array, a copper pattern 2 is formed by etching a copper foil on a resin substrate 1 in which copper foil is laminated on both sides of a plate made of glass fiber reinforced epoxy resin or the like, Circuits are formed on the front and back surfaces of the substrate by opening the signal via holes 3 and performing copper plating. At the same time, the thermal via hole 4 for the purpose of heat dissipation is also opened and plated with copper. Usually, some thermal via holes 4 are provided at the position where the integrated circuit 7 is mounted on the substrate. Next, a dry film resist 6 is laminated on one surface of the printed circuit board, exposed and developed, and ultraviolet irradiation is repeated. Dry on the other side of the board
Film resist 6 is laminated and exposed in the same way,
While development and ultraviolet irradiation are performed, the resist film on the opposite surface is in a so-called over-cure state during this time, and the adhesion with the substrate resin is often lowered. The printed circuit board is then sent to the gold plating process, but there is a high risk that the plating solution will penetrate between the resist film and the resin of the board, which have become over-cured and whose adhesion has deteriorated, resulting in a defective product. In addition, the semiconductor device manufactured using a printed circuit board whose both surfaces are treated with a dry film resist in this way has only the thermal via holes under the integrated circuit covered with a resist film. Since it is hollow, if a pin hole occurs in this part, moisture will infiltrate it immediately, causing abnormal performance.
After the copper pattern 2 on the printed circuit board 1 is plated with gold, the integrated circuit 7 is fixed to the printed circuit board by the conductive adhesive 8, the integrated circuit 7 and the copper pattern 2 are connected by the gold wire 9, and then integrated. The surface on which the circuit is mounted is sealed with resin by transfer molding or potting. Adhesion between the encapsulating resin and the resist film on the printed circuit board is not sufficient, and water often enters through this gap, causing defects.
【０００３】[0003]
【発明が解決しようとする課題】本発明は、レジスト・
フィルムと樹脂基板の間の密着力の低下がなく、金メッ
キ工程で不良の生ずるおそれがないボール・グリッド・
アレイ用のプリント回路基板の製造方法を提供すること
を目的とする。本発明はまた、集積回路の下部のサーマ
ル・ヴィア・ホールが適切に充填され、サーマル・ヴィ
ア・ホールからの水分の侵入のおそれのないボール・グ
リッド・アレイを提供することを目的とする。本発明は
さらに、集積回路搭載面のレジスト・フィルムと封止樹
脂の密着性が良好で、両者の間隙から水分の侵入するお
それのないボール・グリッド・アレイを提供することを
目的とする。SUMMARY OF THE INVENTION
A ball / grid that does not reduce the adhesion between the film and the resin substrate and does not cause defects in the gold plating process.
It is an object to provide a method of manufacturing a printed circuit board for an array. It is also an object of the present invention to provide a ball grid array in which the thermal via holes underneath the integrated circuit are properly filled and there is no risk of moisture ingress from the thermal via holes. A further object of the present invention is to provide a ball grid array in which the adhesion between the resist film on the integrated circuit mounting surface and the encapsulating resin is good, and there is no risk of water entering through the gap between the two.
【０００４】[0004]
【課題を解決するための手段】本発明者は、プリント回
路基板上のレジスト・フィルムの劣化がなく、集積回路
の下部のサーマル・ヴィア・ホールが適切に充填され、
集積回路搭載面のレジスト・フィルムと封止樹脂の密着
性が良好なボール・グリッド・アレイを鋭意研究し、プ
リント回路基板の一面は液状レジストで処理し、他方の
面をドライ・フィルム・レジストで処理し、かつ、レジ
スト・フィルムをプラズマ・ホーニングにより粗面化す
れば、サーマル・ヴィア・ホールは液状レジストで充填
され、ドライ・フィルム・レジストに最適条件の処理を
施すことができ、かつ、レジスト・フィルムと封止樹脂
の接着が強固になるので、高品質で信頼性の高いボール
・グリッド・アレイが得られることを見いだし、本発明
を完成するに至った。The inventor has found that the resist film on the printed circuit board is not deteriorated and the thermal via hole at the bottom of the integrated circuit is properly filled.
We have diligently studied a ball grid array that has good adhesion between the resist film on the integrated circuit mounting surface and the encapsulation resin. One surface of the printed circuit board is treated with liquid resist and the other surface with dry film resist. If the heat treatment is performed and the resist film is roughened by plasma honing, the thermal via holes are filled with the liquid resist, and the dry film resist can be subjected to the treatment under optimum conditions. -It has been found that a high quality and highly reliable ball grid array can be obtained because the adhesion between the film and the sealing resin becomes strong, and the present invention has been completed.
【０００５】すなわち、本発明は次の各項の発明よりな
るものである。 （１）プリント回路基板の集積回路搭載面をドライ・フ
ィルム・レジストで処理し、ボール・グリッド面を液状
レジストで処理したボール・グリッド・アレイ。 （２）プリント回路基板のボール・グリッド面に液状レ
ジストを印刷、硬化し、集積回路搭載面にドライ・フィ
ルム・レジストをラミネートし、露光、現像、紫外線照
射をすることを特徴とするボール・グリッド・アレイ用
のプリント回路基板の製造方法。 （３）プリント回路基板のボール・グリッド面に液状レ
ジストを塗布、露光、現像し、集積回路搭載面にドライ
・フィルム・レジストをラミネートし、露光、現像、紫
外線照射をすることを特徴とするボール・グリッド・ア
レイ用のプリント回路基板の製造方法。 （４）サーマル・ヴィア・ホールの容積の５０％以上を
液状レジストで充填する第２項又は第３項記載のボール
・グリッド・アレイ用のプリント回路基板の製造方法。 （５）集積回路搭載面のレジスト・フィルムをプラズマ
・ホーニングにより粗面化する第２項又は第３項記載の
ボール・グリッド・アレイ用のプリント回路基板の製造
方法。 （６）熱硬化性樹脂又は紫外線硬化性樹脂によりサーマ
ル・ヴィア・ホールを充填したのち、液状レジスト及び
ドライ・フィルム・レジストによる処理を行う第２項又
は第３項記載のボール・グリッド・アレイ用のプリント
回路基板の製造方法。 本発明のボール・グリッド・アレイを図１に示す。本発
明の方法の実施の態様の一例を次に述べる。銅箔を両面
にラミネートした樹脂基板１に、一時的なレジストによ
りパターンを形成し銅箔をエッチングしたのち一時的な
レジストを除去することにより銅パターン２を形成し、
信号用ヴィア・ホール３及びサーマル・ヴィア・ホール
４を明け、銅メッキを施して回路を形成する。次いでボ
ール・グリッド面を液状レジスト５で処理する。That is, the present invention comprises the inventions of the following items. (1) A ball grid array in which the integrated circuit mounting surface of a printed circuit board is treated with a dry film resist and the ball grid surface is treated with a liquid resist. (2) A ball grid characterized by printing and curing a liquid resist on the ball grid surface of a printed circuit board, laminating a dry film resist on the integrated circuit mounting surface, and exposing, developing, and irradiating with ultraviolet rays. A method of manufacturing a printed circuit board for an array. (3) A ball characterized by coating, exposing and developing a liquid resist on the ball grid surface of a printed circuit board, laminating a dry film resist on the integrated circuit mounting surface, and exposing, developing and irradiating ultraviolet rays. A method of manufacturing a printed circuit board for a grid array. (4) The method for manufacturing a printed circuit board for a ball grid array according to the item 2 or 3, wherein 50% or more of the volume of the thermal via hole is filled with a liquid resist. (5) The method for producing a printed circuit board for a ball grid array according to item 2 or 3, wherein the resist film on the integrated circuit mounting surface is roughened by plasma honing. (6) For ball grid array according to item 2 or 3, wherein thermal via holes are filled with a thermosetting resin or an ultraviolet curable resin and then treated with a liquid resist and a dry film resist. Of manufacturing a printed circuit board of. The ball grid array of the present invention is shown in FIG. An example of an embodiment of the method of the present invention will be described below. On the resin substrate 1 laminated with copper foil on both sides, a pattern is formed with a temporary resist, the copper foil is etched, and then the temporary resist is removed to form a copper pattern 2.
The signal via hole 3 and the thermal via hole 4 are opened and copper plating is performed to form a circuit. Then, the ball grid surface is treated with the liquid resist 5.
【０００６】本発明に用いられる液状レジストは、成分
及び処理方法に特に制限はなく、プリント回路基板の保
護効果のあるものを使用することができる。例えば、エ
ポキシ樹脂を主たる硬化成分とする液状レジストを印刷
したのち加熱により硬化することができるし、紫外線硬
化性樹脂を主たる成分とする液状レジストを印刷したの
ち紫外線を照射して硬化することもできる。或いは、ボ
ール・グリッド面に液状レジストを塗布し、ネガ又はポ
ジマスクを通して露光したのち現像することができる。
これらの処理に際して、液状レジストは粘度が低いの
で、サーマル・ヴィア・ホールは相当部分まで液状レジ
ストにより充填される。液状レジストが加熱又は紫外線
照射により硬化するとき、サーマル・ヴィア・ホールを
充填した液状レジストも同時に硬化する。液状レジスト
によって充填されるサーマル・ヴィア・ホールの容積は
サーマル・ヴィア・ホールの全容積の５０％以上、好ま
しくは７０％以上であり、さらにサーマル・ヴィア・ホ
ールが液状レジストにより完全に充填されている状態が
最も好ましい。液状レジストの硬化物がサーマル・ヴィ
ア・ホールの相当部分を充填しているので、水分がボー
ル・グリッド面からサーマル・ヴィア・ホールを通じて
侵入するおそれはない。液状レジストによって充填され
る容積がサーマル・ヴィア・ホールの全容積の５０％未
満の場合には十分な保護効果が得られない。サーマル・
ヴィア・ホールの充填は、ボール・グリッド面の液状レ
ジストによる処理に先だって行うこともできる。この場
合は、サーマル・ヴィア・ホールの充填のみを目的とし
て、樹脂の流動性及び硬化特性を選ぶことができるの
で、サーマル・ヴィア・ホールの完全な充填をより容易
に行うことができる。サーマル・ヴィア・ホールの充填
に用いる樹脂は、耐熱性が良好な硬化性樹脂であれば特
に制限なく用いることができ、例えば、熱硬化性樹脂で
充填したのち加熱により硬化してもよく、あるいは、紫
外線硬化性樹脂で充填したのち紫外線照射により硬化し
てもよい。また、サーマル・ヴィア・ホールを硬化性樹
脂で充填するだけにとどめ、硬化は液状レジスト又はド
ライ・フィルム・レジストの硬化と同時に行うこともで
きる。The liquid resist used in the present invention is not particularly limited in its components and treatment method, and those having a protective effect on the printed circuit board can be used. For example, a liquid resist containing an epoxy resin as a main curing component can be printed and then cured by heating, or a liquid resist containing an ultraviolet curable resin as a main component can be printed and then irradiated with ultraviolet rays to be cured. . Alternatively, the ball grid surface can be coated with a liquid resist, exposed through a negative or positive mask, and then developed.
During these processes, the liquid resist has a low viscosity, so that the thermal via holes are filled with the liquid resist to a considerable extent. When the liquid resist is cured by heating or irradiation with ultraviolet rays, the liquid resist filled with the thermal via holes is simultaneously cured. The volume of the thermal via holes filled with the liquid resist is 50% or more, preferably 70% or more of the total volume of the thermal via holes, and the thermal via holes are completely filled with the liquid resist. The best condition is Since the hardened material of the liquid resist fills a considerable portion of the thermal via hole, there is no risk of water entering from the ball grid surface through the thermal via hole. If the volume filled with the liquid resist is less than 50% of the total volume of the thermal via hole, a sufficient protective effect cannot be obtained. Thermal
The filling of the via holes can also be performed prior to the treatment of the ball grid surface with the liquid resist. In this case, the fluidity and curing characteristics of the resin can be selected only for the purpose of filling the thermal via holes, so that the complete filling of the thermal via holes can be performed more easily. The resin used for filling the thermal via hole can be used without particular limitation as long as it is a curable resin having good heat resistance. For example, it may be filled with a thermosetting resin and then cured by heating, or Alternatively, the resin may be filled with an ultraviolet curable resin and then cured by irradiation with ultraviolet rays. Further, the thermal via hole may be filled with a curable resin, and the curing may be performed simultaneously with the curing of the liquid resist or the dry film resist.
【０００７】集積回路を搭載する面にはドライ・フィル
ム・レジスト６が真空ラミネート法などによってラミネ
ートされ、露光、現像、紫外線照射が施される。本発明
に用いられるドライ・フィルム・レジストには特に制限
はなく、バインダー・ポリマー、光重合性モノマー、光
重合開始剤、染料その他の添加剤からなる感光層を通常
カバー・フィルム及びベース・フィルムで被覆したもの
を用いることができる。ドライ・フィルム・レジストを
ラミネートするのは集積回路を搭載する一面だけである
ので、ドライ・フィルム・レジストに対して最適の処理
条件を施すことができる。従って、レジスト・フィルム
の密着力が低下して、金メッキ工程でメッキ液がフィル
ム・レジストと樹脂基板の間に浸み込むおそれはない。
プリント回路基板のボール・グリッド面を液状レジスト
で処理したのち、集積回路を搭載する面をドライ・フィ
ルム・レジストで処理してもよいし、或いは集積回路搭
載面をドライ・フィルム・レジストで処理したのち、ボ
ール・グリッド面を液状レジストで処理することもでき
る。しかし、ボール・グリッド面を先に液状レジストで
処理する方がサーマル・ヴィア・ホールへの液状レジス
トの充填が容易に行われるので好ましい。A dry film resist 6 is laminated on the surface on which the integrated circuit is mounted by a vacuum laminating method or the like, and is exposed, developed and irradiated with ultraviolet rays. The dry film resist used in the present invention is not particularly limited, and a photosensitive layer composed of a binder polymer, a photopolymerizable monomer, a photopolymerization initiator, a dye and other additives is usually used as a cover film and a base film. A coated product can be used. Since the dry film resist is laminated only on one surface on which the integrated circuit is mounted, the dry film resist can be subjected to optimum processing conditions. Therefore, there is no possibility that the adhesive force of the resist film is lowered and the plating solution penetrates between the film resist and the resin substrate in the gold plating process.
After the ball grid surface of the printed circuit board is treated with a liquid resist, the surface on which the integrated circuit is mounted may be treated with a dry film resist, or the surface on which the integrated circuit is mounted is treated with a dry film resist. After that, the ball grid surface can be treated with a liquid resist. However, it is preferable to first treat the ball grid surface with the liquid resist because the thermal via holes can be easily filled with the liquid resist.
【０００８】本発明方法において、集積回路搭載面のレ
ジスト・フィルムをさらにプラズマ・ホーニングにより
粗面化することができる。レジスト・フィルムを粗面化
すれば、トランスファ成形又はポッティングにより集積
回路を樹脂で封止するときにレジスト・フィルムと封止
樹脂の密着性が良好となり、レジスト・フィルムと封止
樹脂の間隙から水分が侵入するおそれがない。プラズマ
・ホーニングは、レジスト・フィルムの表面が約１μｍ
エッチングされる程度に行えば、十分な効果が得られ
る。その後、プリント回路基板上の銅パターン２には金
メッキが施され、集積回路７が導電性接着剤８によりプ
リント回路基板に固定される。このとき、サーマル・ヴ
ィア・ホールに空間が残っていればその一部は導電性接
着剤によっても充填される。次いで集積回路７と金メッ
キされた銅パターン２が金ワイヤ９により接続され、集
積回路を搭載した面がトランスファ成形または液状レジ
ンのポッティングにより樹脂で保護される。最後にプリ
ント回路基板の裏面にハンダ・ボールが溶着されて本発
明のボール・グリッド・アレイとなる。信号用ハンダ・
ボール１１として用いられないハンダ・ボールのうち、
集積回路７の直下付近に位置し、サーマル・ヴィア・ホ
ールの近傍に存在するハンダ・ボールは、放熱用ハンダ
・ボール１０としてのはたらきを有する。In the method of the present invention, the resist film on the integrated circuit mounting surface can be further roughened by plasma honing. If the resist film is roughened, the adhesiveness between the resist film and the sealing resin will be good when the integrated circuit is sealed with resin by transfer molding or potting, and moisture will be absorbed from the gap between the resist film and the sealing resin. There is no danger of entering. Plasma honing has a resist film surface of about 1 μm
Sufficient effect can be obtained if the etching is performed. Then, the copper pattern 2 on the printed circuit board is plated with gold, and the integrated circuit 7 is fixed to the printed circuit board by the conductive adhesive 8. At this time, if a space remains in the thermal via hole, a part thereof is also filled with the conductive adhesive. Next, the integrated circuit 7 and the gold-plated copper pattern 2 are connected by a gold wire 9, and the surface on which the integrated circuit is mounted is protected by resin by transfer molding or potting with a liquid resin. Finally, solder balls are welded to the back surface of the printed circuit board to form the ball grid array of the present invention. Signal solder
Of the solder balls that are not used as ball 11,
The solder ball located immediately below the integrated circuit 7 and in the vicinity of the thermal via hole serves as a heat-dissipating solder ball 10.
【０００９】[0009]
【発明の効果】本発明の方法により製造されたボール・
グリッド・アレイは、サーマル・ヴィア・ホールの相当
部分が液状レジスト硬化物で充填されているので、サー
マル・ヴィア・ホールから水分の侵入するおそれがな
い。また、ドライ・フィルム・レジストは樹脂基板の片
面だけに施されるので、最適条件で処理することができ
高性能が保たれる。The ball manufactured by the method of the present invention
In the grid array, since a considerable part of the thermal via hole is filled with the liquid resist cured material, there is no risk of water entering through the thermal via hole. Further, since the dry film resist is applied only to one side of the resin substrate, it can be processed under optimum conditions and high performance can be maintained.
【図１】図１は、本発明のボール・グリッド・アレイの
断面図である。FIG. 1 is a cross-sectional view of a ball grid array of the present invention.
【図２】図２は、従来のボール・グリッド・アレイの断
面図である。FIG. 2 is a cross-sectional view of a conventional ball grid array.
１ 樹脂基板 ２ 銅パターン ３ 信号用ヴィア・ホール ４ サーマル・ヴィア・ホール ５ 液状レジスト ６ ドライ・フィルム・レジスト ７ 集積回路 ８ 導電性接着剤 ９ 金ワイヤ １０ 放熱用ハンダ・ボール １１ 信号用ハンダ・ボール 1 Resin Substrate 2 Copper Pattern 3 Signal Via Hole 4 Thermal Via Hole 5 Liquid Resist 6 Dry Film Resist 7 Integrated Circuit 8 Conductive Adhesive 9 Gold Wire 10 Heat Dissipating Solder Ball 11 Signal Soldering Ball
Claims (6)
イ・フィルム・レジストで処理し、ボール・グリッド面
を液状レジストで処理したボール・グリッド・アレイ。1. A ball grid array in which the integrated circuit mounting surface of a printed circuit board is treated with a dry film resist and the ball grid surface is treated with a liquid resist.
液状レジストを印刷、硬化し、集積回路搭載面にドライ
・フィルム・レジストをラミネートし、露光、現像、紫
外線照射をすることを特徴とするボール・グリッド・ア
レイ用のプリント回路基板の製造方法。2. A ball characterized by printing and curing a liquid resist on the ball grid surface of a printed circuit board, laminating a dry film resist on the integrated circuit mounting surface, and exposing, developing, and irradiating with ultraviolet rays. A method of manufacturing a printed circuit board for a grid array.
液状レジストを塗布、露光、現像し、集積回路搭載面に
ドライ・フィルム・レジストをラミネートし、露光、現
像、紫外線照射をすることを特徴とするボール・グリッ
ド・アレイ用のプリント回路基板の製造方法。3. A ball grid surface of a printed circuit board is coated with a liquid resist, exposed and developed, and a dry film resist is laminated on the integrated circuit mounting surface, and exposed, developed and irradiated with ultraviolet rays. Method for manufacturing printed circuit board for ball grid array.
以上を液状レジストで充填する請求項２又は請求項３記
載のボール・グリッド・アレイ用のプリント回路基板の
製造方法。4. The volume of the thermal via hole is 50%.
The method for manufacturing a printed circuit board for a ball grid array according to claim 2 or 3, wherein the above is filled with a liquid resist.
ラズマ・ホーニングにより粗面化する請求項２又は請求
項３記載のボール・グリッド・アレイ用のプリント回路
基板の製造方法。5. The method of manufacturing a printed circuit board for a ball grid array according to claim 2, wherein the resist film on the integrated circuit mounting surface is roughened by plasma honing.
サーマル・ヴィア・ホールを充填したのち、液状レジス
ト及びドライ・フィルム・レジストによる処理を行う請
求項２又は請求項３記載のボール・グリッド・アレイ用
のプリント回路基板の製造方法。6. The ball grid according to claim 2, wherein the thermal via hole is filled with a thermosetting resin or an ultraviolet curable resin, and then a treatment with a liquid resist and a dry film resist is performed. A method of manufacturing a printed circuit board for an array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6023188A JPH07212013A (en) | 1994-01-25 | 1994-01-25 | Manufacture of ball grid array and printed circuit board for ball grid array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6023188A JPH07212013A (en) | 1994-01-25 | 1994-01-25 | Manufacture of ball grid array and printed circuit board for ball grid array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07212013A true JPH07212013A (en) | 1995-08-11 |
Family
ID=12103690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6023188A Pending JPH07212013A (en) | 1994-01-25 | 1994-01-25 | Manufacture of ball grid array and printed circuit board for ball grid array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07212013A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1063699A1 (en) * | 1998-02-10 | 2000-12-27 | Nissha Printing Co., Ltd. | Base sheet for semiconductor module, method for manufacturing base sheet for semiconductor module, and semiconductor module |
| KR20020005822A (en) * | 2000-07-10 | 2002-01-18 | 윤종용 | Printed Circuit Board and Method for manufacturing thereof |
| KR20020065198A (en) * | 2001-02-06 | 2002-08-13 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and method for manufacturing the same |
| JP2003297966A (en) * | 2002-03-29 | 2003-10-17 | Mitsubishi Electric Corp | Semiconductor device |
| JP2006073586A (en) * | 2004-08-31 | 2006-03-16 | Renesas Technology Corp | Semiconductor device manufacturing method |
| JP2011160009A (en) * | 1996-03-28 | 2011-08-18 | Intel Corp | Method of reducing stress due to thermal expansion difference between board and integrated circuit die mounted on first surface of the same |
-
1994
- 1994-01-25 JP JP6023188A patent/JPH07212013A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011160009A (en) * | 1996-03-28 | 2011-08-18 | Intel Corp | Method of reducing stress due to thermal expansion difference between board and integrated circuit die mounted on first surface of the same |
| EP1063699A1 (en) * | 1998-02-10 | 2000-12-27 | Nissha Printing Co., Ltd. | Base sheet for semiconductor module, method for manufacturing base sheet for semiconductor module, and semiconductor module |
| EP1063699A4 (en) * | 1998-02-10 | 2007-07-25 | Nissha Printing | Base sheet for semiconductor module, method for manufacturing base sheet for semiconductor module, and semiconductor module |
| KR20020005822A (en) * | 2000-07-10 | 2002-01-18 | 윤종용 | Printed Circuit Board and Method for manufacturing thereof |
| KR20020065198A (en) * | 2001-02-06 | 2002-08-13 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and method for manufacturing the same |
| JP2003297966A (en) * | 2002-03-29 | 2003-10-17 | Mitsubishi Electric Corp | Semiconductor device |
| JP2006073586A (en) * | 2004-08-31 | 2006-03-16 | Renesas Technology Corp | Semiconductor device manufacturing method |
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