KR100406499B1 - equipment for molding of semiconductor package and molding method using it - Google Patents
equipment for molding of semiconductor package and molding method using it Download PDFInfo
- Publication number
- KR100406499B1 KR100406499B1 KR10-2001-0058529A KR20010058529A KR100406499B1 KR 100406499 B1 KR100406499 B1 KR 100406499B1 KR 20010058529 A KR20010058529 A KR 20010058529A KR 100406499 B1 KR100406499 B1 KR 100406499B1
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- South Korea
- Prior art keywords
- molding
- substrate
- semiconductor package
- mold
- runner
- Prior art date
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- 238000000465 moulding Methods 0.000 title claims abstract description 116
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000012778 molding material Substances 0.000 claims abstract description 12
- 229920001721 polyimide Polymers 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 150000001875 compounds Chemical class 0.000 abstract description 2
- 239000012790 adhesive layer Substances 0.000 description 6
- 239000007788 liquid Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 238000005429 filling process Methods 0.000 description 3
- 239000002341 toxic gas Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 몰딩물질(molding compound)을 사용하여 TBGA(Taped Ball Grid Array) 타입 또는 EPBGA(Enhanced Power Ball Grid Array) 타입의 패키지를 용이하게 제조할 수 있는 반도체패키지의 몰딩장비 및 이를 이용한 몰딩방법에 관해 개시한다.The present invention relates to a molding apparatus for a semiconductor package and a molding method using the same, which can easily manufacture a taped ball grid array (TBGA) type or an enhanced power ball grid array (EPBGA) type package using a molding compound. We start about.
개시된 본 발명의 반도체 패키지 몰딩장비는 반도체 칩이 탑재된 기판이 안착되는 하부몰딩금형와, 하부몰딩금형와 체결되며, 일측에는 몰딩물질이 주입되는 러너가 형성되고 러너와 연결되어 기판의 몰딩영역과 대응되는 부위에는 요입부가 형성된 상부 몰딩금형와, 기판과 상부 몰딩금형 사이에 개재되며, 기판 표면을 덮고 요입부를 개구시키는 개구부를 가진 몰딩판을 포함한다.In the disclosed semiconductor package molding apparatus of the present invention, a lower molding mold on which a substrate on which a semiconductor chip is mounted is mounted, and a lower molding mold are fastened to one side, and a runner in which molding material is injected is formed and connected to the runner to correspond to a molding region of the substrate. The site includes a molding plate having an upper molding mold in which recesses are formed, and an opening interposed between the substrate and the upper molding mold and covering the substrate surface and opening the recesses.
Description
본 발명은 반도체패키지의 몰딩장비 및 이를 이용한 몰딩방법에 관한 것으로, 보다 상세하게는 몰딩물질(molding compound)을 사용하여 TBGA(Taped Ball Grid Array) 타입 또는 EPBGA(Enhanced Power Ball Grid Array)타입의 패키지를 용이하게 제조할 수 있는 반도체패키지의 몰딩장비 및 이를 이용한 몰딩방법에 관한 것이다.The present invention relates to a molding apparatus for a semiconductor package and a molding method using the same, and more particularly, to a package of a taped ball grid array (TBGA) type or an enhanced power ball grid array (EPBGA) type using a molding compound. The present invention relates to a molding apparatus for a semiconductor package which can be easily manufactured and a molding method using the same.
일반적으로 알려진 바와 같이, 전자제품의 사이즈(size)가 경박단소화 되어가고, 반도체 칩의 집적도가 높아지고 연산속도가 증가되어 감에 따라, 합성수지몰드를 이용하지 않고, 합성수지재의 서킷테이프(circuit tape)를 이용하는 TBGA (Taped Ball Grid Array)타입의 패키지와 구동시 열방출을 위한 히트싱크(heat sink)가 구비되어 있으며, 파워(Power) 비·지·에이 패키지라고도 불리우는 EPBGA(EPBGA : Enhanced Power Ball Grid Array package)타입의 패키지가 개발되었다.As is generally known, as the size of electronic products becomes lighter and shorter, the degree of integration of semiconductor chips increases, and the operation speed increases, a circuit tape of a synthetic resin material is used without using a synthetic resin mold. Equipped with a TBGA (Taped Ball Grid Array) type package and a heat sink for heat dissipation during operation, EPBGA (EPBGA: Enhanced Power Ball Grid), also known as Power B / G / A package. Array package) type was developed.
하기에서는 편의상 TBGA타입의 반도체 패키지의 제조과정 만을 언급하기로 한다.In the following, only the manufacturing process of the semiconductor package of the TBGA type will be referred to for convenience.
도 1a 내지 도 1d는 종래 기술에 따른 TBGA타입의 반도체 패키지의 제조과정을 보인 공정단면도이다.1A to 1D are cross-sectional views illustrating a process of manufacturing a TBGA type semiconductor package according to the prior art.
상기 서킷테이프(1)는, 도 1a에 도시한 바와 같이, 폴리이미드 필름(polyimide film)에 회로를 형성한 서킷필름(circuit film)(2)의 배면에 형성된 접착층(4)과, 상기 접착층(4) 상에 부착되어 상기 접착층(4)이 오염되는 것을 방지하기 위한 보호테이프(6)로 구성된다.As shown in FIG. 1A, the circuit tape 1 includes an adhesive layer 4 formed on a rear surface of a circuit film 2 having a circuit formed on a polyimide film, and the adhesive layer ( It is attached to 4) is composed of a protective tape (6) for preventing the adhesive layer (4) from being contaminated.
상기 구성을 가진 서킷테이프를 이용한 TBGA 타입의 반도체 패키지의 제조방법은, 도 1b에 도시된 바와 같이, 먼저 서킷테이프(1)로부터 보호테이프(6)를 제거한다. 이어서, 도 1c에 도시된 바와 같이, 기판(10) 표면에 접착층(4)에 의해 서킷필름(2)을 부착시킨 후, 기판(10)의 안착부(11)에 반도체칩(8)을 탑재시킨다. 이때, 상기 반도체 칩(8)은 양면 접착테이프(미도시) 또는 접착제에 의해 안착부(11)에 탑재된다.In the method for manufacturing a TBGA type semiconductor package using the circuit tape having the above configuration, as shown in FIG. 1B, the protective tape 6 is first removed from the circuit tape 1. Subsequently, as shown in FIG. 1C, the circuit film 2 is attached to the surface of the substrate 10 by the adhesive layer 4, and then the semiconductor chip 8 is mounted on the mounting portion 11 of the substrate 10. Let's do it. At this time, the semiconductor chip 8 is mounted on the mounting portion 11 by a double-sided adhesive tape (not shown) or adhesive.
그 다음, 와이어본딩 공정에 의해 반도체 칩(8)의 칩패드(미도시)과 서킷필름(2)을 연결시키는 본딩와이어(14)를 형성한다. 이때, 본딩와이어(14)는 반도체칩(8)과 서킷필름(2)의 회로를 상호 연결하는 역할을 한다.Next, a bonding wire 14 for connecting the chip pad (not shown) of the semiconductor chip 8 and the circuit film 2 is formed by a wire bonding process. In this case, the bonding wire 14 serves to interconnect the circuits of the semiconductor chip 8 and the circuit film 2.
이어서, 서킷필름(2) 상에 반도체 칩(8)을 애워싸도록 댐(dam)(12)을 형성한다. 이때, 댐(12)은 시린지(syringe)를 이용하여 에폭시(epoxy) 등의 코팅액을 주입하여 형성한다.Next, a dam 12 is formed on the circuit film 2 to surround the semiconductor chip 8. In this case, the dam 12 is formed by injecting a coating liquid such as epoxy using a syringe.
상기 댐(12)은 이 후의 패키지 몰딩 공정에서 주입되는 용융된 열경화성 수지가 외부로 흘러넘치는 현상을 방지하기 위한 역할을 한다.The dam 12 serves to prevent a phenomenon that the molten thermosetting resin injected in a subsequent package molding process overflows to the outside.
그 다음, 도 1d에 도시된 바와 같이, 액상의 용융된 열경화성 수지를 이용하여 필링(filling) 공정을 진행시킴으로써 반도체 칩(8)을 덮는 몰딩체(16)를 형성한다.Next, as shown in FIG. 1D, a molding 16 covering the semiconductor chip 8 is formed by performing a filling process using a liquid molten thermosetting resin.
이때, 상기 필링 공정 진행 시에 열처리 공정이 수반된다. 상기 몰딩체(16)는 반도체 칩(8)을 외부 환경으로부터 보호하기 위한 것이다.At this time, a heat treatment process is involved in the peeling process. The molding 16 is for protecting the semiconductor chip 8 from an external environment.
이 후, 상기 서킷필름(2)의 회로면에 작은 납알갱이로 구성된 솔더볼(12)을 부착하여 패키지 제조를 완성한다.Thereafter, a solder ball 12 made of small lead particles is attached to the circuit surface of the circuit film 2 to complete the package manufacture.
상기 서킷테이프(1)를 이용한 TBGA 타입의 패키지는 통상적인 반도체 패키지에 비해, 전기신호의 이동경로가 짧아져 처리속도가 향상되며 저전력구동이 가능할 뿐 아니라, 작은 크기에 더 많은 리드를 넣을 수 있으며, 열발생 및 방출에도 유리하다.TBGA type package using the circuit tape (1) is shorter than the conventional semiconductor package, the movement path of the electrical signal is shortened to improve the processing speed and low power drive, and can put more leads in a small size It is also advantageous for heat generation and release.
종래의 TBGA 타입의 패키지 또는 EPBGA 타입의 패키지를 몰딩할 경우, 몰딩물질이 유입되는 통로인 러너(runner)가 없기 때문에 통상적으로 사용되는 몰딩장비를 사용하지 못하고, 시린지를 이용하여 용융된 액상의 열경화성 수지를 댐 내부에 필링하는 방식으로 몰딩 공정을 진행하였다.When molding a conventional TBGA-type package or EPBGA-type package, there is no runner that is a passage through which the molding material flows, so that a molding apparatus that is not commonly used cannot be used, and the liquid thermosetting property of the melted liquid using a syringe The molding process was performed by filling the resin into the dam.
따라서, 종래의 기술에서는 별도의 댐 형성공정, 필링 공정 및 열공정이 각각 수반됨에 따라, 몰딩 공정이 복잡해질 뿐더러, 제품의 생산시간이 장시간 소요되고 제품의 생산 수율이 저하되었다.Therefore, in the conventional technology, as a separate dam forming process, a filling process, and a thermal process are respectively involved, the molding process is complicated, and the production time of the product is long, and the yield of the product is reduced.
또한, 상기 액상의 열경화성 수지를 경화시키는 과정에서 유독가스가 발생되므로, 상기 유독가스를 배출하기 위한 별도의 배관 등의 환경시설 구비해야 하는 문제점이 있었다.In addition, since the toxic gas is generated in the process of curing the liquid thermosetting resin, there was a problem that should be provided with an environmental facility such as a separate pipe for discharging the toxic gas.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, TBGA타입 또는 EPBGA 타입의 반도체 패키지의 몰딩 공정을 용이하게 진행할 수 있는 반도체패키지 몰딩장비를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a semiconductor package molding apparatus that can easily proceed the molding process of a semiconductor package of the TBGA type or EPBGA type to solve the conventional problems.
본 발명의 다른 목적은 상기 몰딩장비에 의해 TBGA타입 또는 EPBGA 타입의 반도체 패키지의 몰딩 공정을 용이하게 진행할 수 있는 반도체패키지의 몰딩방법을 제공함에 있다.Another object of the present invention is to provide a molding method of a semiconductor package that can easily proceed the molding process of the semiconductor package of the TBGA type or EPBGA type by the molding equipment.
도 1a 내지 도 1d는 종래 기술에 따른 TBGA타입의 반도체 패키지의 제조과정을 보인 공정단면도.1A to 1D are cross-sectional views illustrating a process of manufacturing a TBGA type semiconductor package according to the prior art.
도 2는 본 발명에 따른 몰딩장비의 단면도.2 is a cross-sectional view of the molding equipment according to the present invention.
도 3은 본 발명에 따른 몰딩장비에서 몰딩판의 평면도.3 is a plan view of a molding plate in the molding apparatus according to the present invention.
도 4a 내지 도 4e는 본 발명의 몰딩장비를 이용하여 TBGA타입의 반도체 패키지의 몰딩과정을 보인 공정단면도.4A to 4E are cross-sectional views illustrating a molding process of a TBGA type semiconductor package using the molding apparatus of the present invention.
도 5a 내지 도 5d는 본 발명의 몰딩장비를 이용하여 TBGA타입의 반도체 패키지의 몰딩과정을 보인 공정평면도.5a to 5d is a process plan view showing a molding process of the semiconductor package of the TBGA type using the molding equipment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
100. 하부 몰딩금형 102. 안착부100. Lower molding mold 102. Seating part
120. 반도체 칩 122. 본딩와이어120. Semiconductor Chip 122. Bonding Wire
130. 기판 132. 접착제130. Substrate 132. Adhesive
134. 서킷필름 150. 몰딩판134. Circuit Film 150.Moulding Plate
160. 상부 몰딩금형 162. 돌기부160. Upper molding mold 162. Protrusion
상기 목적을 달성하기 위한 본 발명의 반도체패키지 몰딩장비는 반도체 칩이 탑재된 기판이 안착되는 하부몰딩금형와, 하부몰딩금형와 체결되며, 일측에는 몰딩물질이 주입되는 러너가 형성되고 러너와 연결되어 기판의 몰딩영역과 대응되는 부위에는 요입부가 형성된 상부 몰딩금형와, 기판과 상부 몰딩금형 사이에 개재되며, 기판 표면을 덮고 요입부를 개구시키는 개구부를 가진 몰딩판을 포함한 것을 특징으로 한다.The semiconductor package molding equipment of the present invention for achieving the above object is fastened to the lower molding mold and the lower molding mold is seated on which the substrate on which the semiconductor chip is mounted, and formed on the one side a runner is injected with a molding material and connected to the runner of the substrate A portion corresponding to the molding region is characterized by including a molding plate having an upper molding mold having a recessed portion formed therebetween, and a molding plate interposed between the substrate and the upper molding mold, and having an opening covering the substrate surface and opening the recess.
상기 다른 목적을 달성하기 위해, 상기 몰딩판이 구비된 몰딩장비에 의해 본 발명의 반도체패키지를 몰딩하는 방법은 하부 몰딩금형 상에 반도체 칩이 탑재된 기판을 안착시키는 단계; 기판 상에 몰딩판을 안착시키는 단계; 상기 구조의 하부 몰딩금형에 상부 몰딩금형를 체결하는 단계; 러너를 통해 요입부 내로 몰딩물질을 주입시키는 단계; 주입된 몰딩물질을 고형화하여 몰딩체를 형성하는 단계; 및 상부 몰딩금형과 몰딩판을 제거하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above another object, a method of molding a semiconductor package of the present invention by the molding equipment equipped with the molding plate comprises the steps of: mounting a substrate on which a semiconductor chip is mounted on a lower molding mold; Mounting a molding plate on the substrate; Fastening the upper molding mold to the lower molding mold of the structure; Injecting molding material into the recess through the runner; Solidifying the injected molding material to form a molding; And removing the upper molding mold and the molding plate.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명의 반도체패키지 몰딩장비 및 이를 이용한 몰딩방법은 TBGA타입 또는EPBGA타입의 반도체 패키지 모두 적용되나, 편의상 하기에서는 TBGA타입의 반도체패키지에 적용한 것을 기술한다.The semiconductor package molding equipment of the present invention and a molding method using the same are applied to both a TBGA type or EPBGA type semiconductor package, but for convenience, the following description is applied to a TBGA type semiconductor package.
도 2는 본 발명에 따른 몰딩장비의 단면도이고, 도 3은 본 발명에 따른 몰딩장비에서 몰딩판의 평면도이다.2 is a cross-sectional view of a molding apparatus according to the present invention, Figure 3 is a plan view of a molding plate in the molding equipment according to the present invention.
본 발명의 반도체패키지 몰딩장비는, 도 2 및 도 3에 도시된 바와같이, 반도체 칩(120)이 탑재된 기판이 안착되는 제 1안착부(102)가 형성된 하부 몰딩금형(100)와, 하부 몰딩금형(100)와 체결되며 일측에는 몰딩물질이 주입되는 러너(164)가 형성되고 상기 러너(164)와 연결되어 반도체 칩(120)과 대응되는 부위에 형성된 요입부(166)이 형성된 상부 몰딩금형(160)와, 기판(130)과 상부 몰딩금형(160) 사이에 개재되며 기판(130) 표면을 덮고 요입부(166)를 개구시키는 개구부(152)를 가진 몰딩판(150)을 포함하여 구성된다.As shown in FIGS. 2 and 3, the semiconductor package molding apparatus of the present invention includes a lower molding mold 100 having a first seating portion 102 on which a substrate on which the semiconductor chip 120 is mounted is formed, and a lower portion thereof. The upper molding is fastened to the molding mold 100 and the runner 164 is formed on one side is injected with a molding material and is connected to the runner 164 formed with a recess 166 formed in a portion corresponding to the semiconductor chip 120 And a molding plate 150 having a mold 160 and an opening 152 interposed between the substrate 130 and the upper molding mold 160 and covering the surface of the substrate 130 and opening the recess 166. It is composed.
상기 기판(130)은 접착층(132)에 의해 서킷필름(134)이 부착되어 있으며, 중심부위에는 반도체 칩(120)이 안착되는 제 2안착부(104)가 형성되어 있다.The circuit board 134 is attached to the substrate 130 by the adhesive layer 132, and a second seating part 104 on which the semiconductor chip 120 is seated is formed on the center.
상기 반도체 칩(120)과 서킷필름(134)은 본딩와이어(122)에 의해 전기적으로 연결된다.The semiconductor chip 120 and the circuit film 134 are electrically connected by the bonding wires 122.
상기 상부 몰딩금형(160)의 러너(164)와 요입부(166) 사이에는 돌기부를 형성된다.A protrusion is formed between the runner 164 and the recess 166 of the upper molding mold 160.
상기 몰딩판의 재질은 폴리이미드계 테이프 또는 동판을 이용한다.The molding plate may be made of polyimide tape or copper plate.
도 4a 내지 도 4e는 본 발명의 몰딩장비를 이용하여 TBGA타입의 반도체 패키지의 몰딩과정을 보인 공정단면도이고, 도 5a 내지 도 5d는 본 발명의 몰딩장비를이용하여 TBGA타입의 반도체 패키지의 몰딩과정을 보인 공정평면도이다.4A to 4E are cross-sectional views illustrating a molding process of a TBGA type semiconductor package using the molding apparatus of the present invention, and FIGS. 5A to 5D illustrate a molding process of a TBGA type semiconductor package using the molding apparatus of the present invention. This is a process plan view.
상기 구성을 가진 본 발명의 몰딩장비에 의해 반도체패키지를 몰딩하는 방법은, 도 4a 및 도 5a에 도시된 바와 같이, 하부 몰딩금형(100)의 제 1안착부(102) 상에 기판(130)을 위치시킨다. 상기 기판(130)에는 접착층(132)에 의해 서킷필름(134)이 부착되어 있으며, 중심부위의 제 2안착부(104)에 반도체 칩(120)이 탑재되어 있다. 또한, 상기 반도체 칩(120)과 서킷필름(134)은 본딩와이어(122)에 의해 전기적으로 연결된다.The method of molding a semiconductor package by the molding apparatus of the present invention having the above configuration, as shown in Figures 4a and 5a, the substrate 130 on the first seating portion 102 of the lower molding mold 100 Locate it. The circuit film 134 is attached to the substrate 130 by the adhesive layer 132, and the semiconductor chip 120 is mounted on the second seating portion 104 on the center portion. In addition, the semiconductor chip 120 and the circuit film 134 are electrically connected by the bonding wires 122.
이어서, 도 4b 및 도 5b에 도시된 바와 같이, 하부 몰딩금형(100) 및 기판(130)의 서킷필름(134) 상에 이 후의 몰딩 공정에서 러너 역할을 하는 몰딩판(150)을 안착시킨다. 이때, 반도체 칩(120) 및 제 2안착부(104)은 몰딩판(150)의 개구부(152)에 의해 노출된다. 또한, 상기 몰딩판의 재질로는 폴리이미드계 테이프 또는 동판을 이용한다.Subsequently, as shown in FIGS. 4B and 5B, the molding plate 150 serving as a runner in a subsequent molding process is mounted on the lower molding mold 100 and the circuit film 134 of the substrate 130. In this case, the semiconductor chip 120 and the second seating part 104 are exposed by the opening 152 of the molding plate 150. In addition, a polyimide tape or a copper plate is used as a material of the molding plate.
그 다음, 도 4c에 도시된 바와 같이, 상기 구조의 하부 몰딩금형(100)에 상부 몰딩금형(160)을 체결한다.Then, as shown in Figure 4c, the upper molding mold 160 to the lower molding mold 100 of the structure.
이 후, 도 4d 및 도 5c에 도시된 바와 같이, 러너(164)를 통해 요입부(166) 내로 몰딩물질(137)을 주입한 후, 상기 몰딩물질(137)을 경화시키어 몰딩체(138)를 형성한다. 이때, 돌기부(162)에 의해 러너(164) 주변부위의 몰딩체(138)의 형상이 일정하게 유지된다.Thereafter, as illustrated in FIGS. 4D and 5C, after the molding material 137 is injected into the recess 166 through the runner 164, the molding material 137 is cured to form the molding 138. To form. At this time, the shape of the molding body 138 around the runner 164 is maintained by the protrusion 162.
이어서, 도 4e 및 도 5d에 도시된 바와 같이, 상부 몰딩금형을 오픈시킨 후, 몰딩판 및 몰딩찌꺼기를 제거하여 패키지 몰딩을 완료한다.Then, as shown in Figures 4e and 5d, after opening the upper molding mold, the molding plate and the molding residue is removed to complete the package molding.
이상에서와 같이, 본 발명의 장비를 이용하여 러너가 없는 TBGA 또는 EPBGA 타입의 반도체패키지를 몰딩함으로써, 별도의 댐 형성 및 필링 공정이 추가되지 않기 때문에 몰딩 공정이 단순화될 뿐더러, 제품의 생산시간이 단축되고 제품의 생산 수율이 향상된다.As described above, by molding the runner-free TBGA or EPBGA-type semiconductor package using the equipment of the present invention, the molding process is simplified because no additional dam forming and filling process is added, and the production time of the product is Shorten the production yield of the product.
또한, 본 발명에서는 상부 몰딩금형가 체결된 상태에서 몰딩 물질의 경화 공정이 진행되므로, 경화 공정 시에 발생되는 유독가스 등을 배출시키기 위한 별도의 배관 등의 환경시설이 필요하지 않는다.In addition, in the present invention, since the curing process of the molding material proceeds in the state in which the upper molding mold is fastened, an environmental facility such as a piping for discharging toxic gases generated during the curing process is not required.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR19990028774U (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Molding die |
| KR19990031250U (en) * | 1997-12-30 | 1999-07-26 | 김규현 | Molding molds for manufacturing ball grid array semiconductor packages using flexible circuit boards |
| JP2000200862A (en) * | 1999-01-07 | 2000-07-18 | Hitachi Ltd | Semiconductor device and manufacture thereof |
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| KR19990028774U (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Molding die |
| KR19990031250U (en) * | 1997-12-30 | 1999-07-26 | 김규현 | Molding molds for manufacturing ball grid array semiconductor packages using flexible circuit boards |
| JP2000200862A (en) * | 1999-01-07 | 2000-07-18 | Hitachi Ltd | Semiconductor device and manufacture thereof |
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