JPH09199639A - Semiconductor device and its formation - Google Patents
Semiconductor device and its formationInfo
- Publication number
- JPH09199639A JPH09199639A JP8004700A JP470096A JPH09199639A JP H09199639 A JPH09199639 A JP H09199639A JP 8004700 A JP8004700 A JP 8004700A JP 470096 A JP470096 A JP 470096A JP H09199639 A JPH09199639 A JP H09199639A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- resin
- semiconductor device
- chip
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、特に薄形化、軽
量化および高放熱性を必要とする半導体装置およびその
成形方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which requires particularly thinness, light weight and high heat dissipation and a method for molding the same.
【０００２】[0002]
【従来の技術】従来、エポキシ樹脂の成形による半導体
装置の構造は、その中心部にダイパッドおよびチップを
置き、その全体をエポキシ樹脂で覆っているものが一般
的である。また、近年の半導体装置の薄形化への要望を
満たすためチップ、リードフレーム、或いはそれらを覆
う樹脂の厚みそのものの薄肉化を図ってきた。2. Description of the Related Art Conventionally, a structure of a semiconductor device formed by molding an epoxy resin is generally one in which a die pad and a chip are placed at the center thereof and the whole is covered with the epoxy resin. In addition, in order to meet the recent demand for thinner semiconductor devices, the thickness of the chip, the lead frame, or the resin covering them has been reduced.
【０００３】また、通常、ＱＦＰ（ｑｕａｄ ｆｌａｔ
ｐａｃｋａｇｅ）といわれる半導体装置の成形は、特
定の形を彫り込んだ金型を搭載したプレス機を使用し、
ワイヤーボンドが終了した製品を上下から挟み込み熱を
かけペレット状に固められた樹脂を溶融しながら流し込
む方法が取られている。このとき溶融した樹脂の注入の
仕方としては、チップとチップを乗せているダイパッド
をチップ上とダイパッド下で均等に覆っていくようにす
ることが理想的であり、そういう流れになるように設備
においては金型温度、樹脂注入速度、金型においてはゲ
ート口の大きさ、角度を調整するといった対応を取って
いる。In addition, a QFP (quad flat) is usually used.
For the molding of semiconductor device called "package", a press machine equipped with a mold engraved with a specific shape is used,
The method of sandwiching the product for which wire bonding has been completed from the top and bottom and applying heat to melt the resin that has been solidified into pellets is used. At this time, it is ideal to inject the molten resin so that the chip and the die pad on which the chip is placed are evenly covered on the chip and under the die pad. Takes measures such as adjusting the mold temperature, the resin injection speed, and the size and angle of the gate opening in the mold.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、それら
材料の薄肉化は強度の確保或いは成形性の安定化という
面において困難となり、さらなる薄形化を図るために
は、現在開発が進んでいるテープキャリアパッケージ或
いはチップサイズパッケージ等への展開が必要となって
くる。しかしそれらの方法を用いる場合、半導体装置自
体の構造が変わり実装方法も変えていく必要があること
から、すぐに扱えないという問題点もある。However, it is difficult to reduce the thickness of these materials in terms of securing strength or stabilizing the moldability, and in order to achieve further reduction in thickness, tape carriers that are currently being developed. It becomes necessary to develop into packages or chip size packages. However, when using these methods, the structure of the semiconductor device itself changes and the mounting method also needs to be changed, so that there is a problem that it cannot be handled immediately.
【０００５】また、成形する場合も、パッケージが薄く
なり、チップ上およびダイパッド下の樹脂が流れ込む空
間が薄くなるにしたがってスムーズな樹脂の流れが損な
われ、それにともなってチップ上とダイパッド下の樹脂
の注入の仕方が不均等になると、ダイパッドが上に或い
は下にシフトする。特に薄いパッケージの場合、パッケ
ージ表面にワイヤーが露出したり、切れるというような
不具合が起こる。Also, in the case of molding, as the package becomes thinner and the space on the chip and under the die pad where the resin flows in becomes thinner, the smooth resin flow is impaired, and accordingly, the resin on the chip and under the die pad decreases. The uneven implantation causes the die pad to shift up or down. Particularly in the case of a thin package, there are problems such as the wire being exposed on the surface of the package or being cut.
【０００６】さらに、半導体装置の薄形化にともない耐
クラック性が問題視されている中、一般的に報告されて
いる、ダイパッド裏面と樹脂との界面に溜まった水分や
チップ裏面とダイパッドとの界面にある水分が実装中の
加熱により気化膨張しパッケージクラックを引き起こす
ことがある。したがって、この発明の目的は、従来の実
装設備で実装が行え、安定した樹脂成形が行えるととも
にさらなる薄形化が可能になる半導体装置およびその成
形方法を提供することである。Further, as crack resistance has been regarded as a problem with the thinning of semiconductor devices, it has been generally reported that water accumulated at the interface between the back surface of the die pad and the resin and the back surface of the chip and the die pad. Moisture at the interface may evaporate and expand due to heating during mounting, causing package cracks. Therefore, an object of the present invention is to provide a semiconductor device which can be mounted by conventional mounting equipment, can perform stable resin molding, and can be further thinned, and a molding method thereof.
【０００７】[0007]
【課題を解決するための手段】請求項１記載の半導体装
置は、ダイパッドの表面上にチップを固定し、その全体
を樹脂で被覆した半導体装置であって、ダイパッドの裏
面が外部に露出したことを特徴とするものである。この
ように、ダイパッドの裏面が外部に露出しているので、
ダイパッドの裏面の樹脂の厚み分、薄形化を図ることが
できる。また、外形においても従来のものとでは厚み以
外変わるところはないので、実装についても従来の技術
を持って実施できる。また、ダイパッド裏面が露出して
いることから、放熱性に優れている。さらに、本構造は
ダイパッド裏面とエポキシ樹脂との界面が存在しないた
め、ダイパッド裏面と樹脂との界面に水分が溜まらず、
この水分の気化膨張によるパッケージクラックを引き起
こすことがない。また、ダイパッド裏面が露出している
ことから、チップ裏面とダイパッドとの界面にある水分
が実装中の加熱により気化しても、気化した蒸気はダイ
パッド側面をたどり、即外部に逃がすことができ、パッ
ケージクラックには至らない。これらのことより耐クラ
ック性においても優れた半導体装置といえる。A semiconductor device according to claim 1 is a semiconductor device in which a chip is fixed on the front surface of a die pad and the whole is covered with a resin, and the back surface of the die pad is exposed to the outside. It is characterized by. In this way, since the back surface of the die pad is exposed to the outside,
It is possible to reduce the thickness of the resin on the back surface of the die pad by the thickness. Also, since the outer shape is the same as the conventional one except for the thickness, the mounting can be performed with the conventional technique. Further, since the back surface of the die pad is exposed, it has excellent heat dissipation. Furthermore, in this structure, since there is no interface between the back surface of the die pad and the epoxy resin, moisture does not collect at the interface between the back surface of the die pad and the resin,
This does not cause package cracking due to vaporization and expansion of water. Further, since the back surface of the die pad is exposed, even if the moisture at the interface between the back surface of the die and the die pad is vaporized by heating during mounting, the vaporized vapor can trace the side surface of the die pad and immediately escape to the outside. Does not lead to package cracks. From these, it can be said that the semiconductor device is excellent in crack resistance.
【０００８】請求項２記載の半導体装置の成形方法は、
ダイパッドの表面上にチップを固定しこのチップとリー
ドをワイヤで接続する工程と、分割可能な金型の対向面
に形成されたキャビティにチップおよびダイパッドを配
置した状態でリードをキャビティの外周部で保持する工
程と、チップの上方に流れるように樹脂をキャビティ内
に注入する工程とを含むものである。A method of molding a semiconductor device according to claim 2 is
The process of fixing the chip on the surface of the die pad and connecting the chip and the lead with a wire, and the lead at the outer periphery of the cavity with the chip and the die pad arranged in the cavity formed on the facing surface of the mold that can be divided. It includes a step of holding and a step of injecting a resin into the cavity so as to flow above the chip.
【０００９】このように、樹脂がチップの上方に流れる
ようにキャビティ内に樹脂を注入すると、その樹脂の圧
力によりチップを固定したダイパッドは下に沈み金型に
当接してその姿勢が規制される。このため、樹脂注入に
おいてダイパッドが上下にシフトすることがなく、ワイ
ヤに対しても負担が小さくなる。特に薄形のパッケージ
の場合でもワイヤがパッケージ表面に露出したり切れる
というようなことがなく、安定した成形が行える。ま
た、成形後のパッケージは、ダイパッド裏面が外部に露
出し、請求項１と同様の効果が得られる。As described above, when the resin is injected into the cavity so that the resin flows above the chip, the die pad, which fixes the chip, is sunk by the pressure of the resin and abuts on the die to regulate its posture. . Therefore, the die pad does not shift up and down during resin injection, and the load on the wire is reduced. In particular, even in the case of a thin package, the wire is not exposed or cut on the package surface, and stable molding can be performed. Further, the back surface of the die pad of the molded package is exposed to the outside, and the same effect as that of claim 1 is obtained.
【００１０】[0010]
【発明の実施の形態】この発明の実施の形態の半導体装
置およびその成形方法を図１ないし図４に基づいて説明
する。この半導体装置は、ダイパッド３の表面上に接着
剤でチップ４を固定し、ダイパッド３の裏面を除いてそ
の全体をエポキシ樹脂１で被覆している。また、チップ
４とリード５はワイヤ２で接続されている。BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device and a method of molding the same according to an embodiment of the present invention will be described with reference to FIGS. In this semiconductor device, the chip 4 is fixed on the front surface of the die pad 3 with an adhesive, and the entire surface of the die pad 3 except the back surface is covered with the epoxy resin 1. The chip 4 and the lead 5 are connected by the wire 2.
【００１１】リード５は樹脂成形されたパッケージ側面
から一列に、半導体装置の裏面から一定の距離ｔを置い
たところから外側に向けて突出している。また、ダイパ
ッド３とリード５との間には一定の段差ｈを設け、リー
ド５が落ちないように樹脂１で確実に固定されている。
ワイヤ２は金、アルミニウム或いは銅等からなり、この
ワイヤ２を介してチップ４上の回路から発信される信号
がリード５に送られる。また、ダイパッド３の裏面はパ
ッケージの裏面と面一になり外部に露出している。The leads 5 are projected in a line from the side surface of the resin-molded package and outwardly from a position a certain distance t from the back surface of the semiconductor device. Further, a constant step h is provided between the die pad 3 and the lead 5, and the lead 5 is securely fixed by the resin 1 so as not to fall.
The wire 2 is made of gold, aluminum, copper or the like, and a signal transmitted from a circuit on the chip 4 is sent to the lead 5 through the wire 2. The back surface of the die pad 3 is flush with the back surface of the package and is exposed to the outside.
【００１２】つぎに、この半導体装置の成形方法につい
て説明する。この成形に使用される金型Ａは分割可能な
上型１２と下型１３とからなり、対向面にキャビティ１
４が形成される。このキャビティ１４の外周部１５はリ
ード５を保持できるような形状にしてある。また、樹脂
１をキャビティ１４内に注入するためのランナ７および
ゲート口８が設けてある。また、封止成形後のダイパッ
ド３とリード５との間には、上記のように一定の段差ｈ
が設けられる構造にしておく。Next, a method of molding this semiconductor device will be described. The mold A used for this molding is composed of an upper mold 12 and a lower mold 13 which can be divided, and has a cavity 1 on the opposite surface.
4 are formed. The outer peripheral portion 15 of the cavity 14 has a shape capable of holding the lead 5. A runner 7 and a gate port 8 for injecting the resin 1 into the cavity 14 are provided. Further, as described above, a constant step h is provided between the die pad 3 and the lead 5 after the sealing molding.
Is provided.
【００１３】そして、図２に示すように、ダイパッド３
の表面上にチップ４が接着剤で固定され、チップ４とリ
ード５がワイヤ２で繋がれ状態のワイヤボンド済みのリ
ードフレームを金型Ａに装着する。この場合、ダイパッ
ド３が下型１３から浮いた状態でキャビティ１４の中央
に配置されるように、ワイヤ２で繋がれたリード５の一
端をキャビティ１４内に突出させてリード５の他端を外
周部１５にて保持する。この際、ダイパッド３の裏面が
できるだけ下型１３に接近するように設定しておく。つ
ぎに、図３に示すように、ゲート口８からキャビティ１
４内に樹脂１を注入する。この際、従来と同様にペレッ
ト状に固められた樹脂１を溶融しながら流し込む。矢印
Ｃは樹脂１の流動方向を示している。樹脂１を注入する
際は、ゲート口８の角度或いは注入速度の調整により樹
脂１がチップ４の上方に流れるようにし、その上からの
樹脂１の圧力で利用しダイパッド３が沈むようにする。
このように、必ず注入中の樹脂１が上方に流れるように
設定しておけば、チップ４を乗せたダイパッド３は下に
沈むしかなく、下は金型Ａの下型１３で規制されるため
安定した成形が得られる。Then, as shown in FIG.
The chip 4 is fixed on the surface of the substrate with an adhesive, and the wire-bonded lead frame in which the chip 4 and the lead 5 are connected by the wire 2 is mounted on the mold A. In this case, one end of the lead 5 connected by the wire 2 is projected into the cavity 14 so that the die pad 3 is arranged in the center of the cavity 14 while being floated from the lower mold 13, and the other end of the lead 5 is surrounded by the outer periphery. It is held by the section 15. At this time, the back surface of the die pad 3 is set as close to the lower die 13 as possible. Next, as shown in FIG. 3, from the gate opening 8 to the cavity 1
Resin 1 is injected into 4. At this time, the resin 1 that has been solidified into a pellet form is poured while melting, as in the conventional case. The arrow C indicates the flow direction of the resin 1. When the resin 1 is injected, the resin 1 is made to flow above the chip 4 by adjusting the angle of the gate opening 8 or the injection speed, and the die pad 3 is sunk by utilizing the pressure of the resin 1 from above.
In this way, if the resin 1 being injected is set to flow upwards without fail, the die pad 3 on which the chip 4 is placed must be sunk below, and the lower part is restricted by the lower mold 13 of the mold A. Stable molding can be obtained.
【００１４】さらに成形後、図３に示すように露出した
ダイパッド３の裏面に樹脂ばり１０がある場合は、ウオ
ータージェット等のばり取りを実施することで、きれい
にすることができる。以上の工程により、図１に示すよ
うなダイパッド３の裏面が外部に露出した半導体装置を
得ることができる。この実施の形態によれば、ダイパッ
ド３の裏面が外部に露出しているので、ダイパッド３の
裏面の樹脂１の厚み分、薄形化を図ることができる。ま
た、外形においても従来のものとでは厚み以外変わると
ころはないので、実装についても従来の技術を持って実
施できる。また、ダイパッド３の裏面が露出しているこ
とから、放熱性に優れている。さらに、本構造はダイパ
ッド３の裏面とエポキシ樹脂１との界面が存在しないた
め、ダイパッド３の裏面と樹脂１との界面に水分が溜ま
らず、この水分の気化膨張によるパッケージクラックを
引き起こすことがない。また、ダイパッド３の裏面が露
出していることから、チップ４の裏面とダイパッド３と
の界面にある水分が実装中の加熱により気化しても、気
化した蒸気はダイパッド３の側面をたどり、即外部に逃
がすことができ、パッケージクラックには至らない。こ
れらのことより耐クラック性においても優れた半導体装
置といえる。Further, after molding, if there is a resin burr 10 on the back surface of the exposed die pad 3 as shown in FIG. 3, it can be cleaned by deburring with a water jet or the like. Through the above steps, a semiconductor device as shown in FIG. 1 in which the back surface of the die pad 3 is exposed to the outside can be obtained. According to this embodiment, since the back surface of the die pad 3 is exposed to the outside, it is possible to reduce the thickness by the thickness of the resin 1 on the back surface of the die pad 3. Also, since the outer shape is the same as the conventional one except for the thickness, the mounting can be performed with the conventional technique. Further, since the back surface of the die pad 3 is exposed, it has excellent heat dissipation. Further, in this structure, since the interface between the back surface of the die pad 3 and the epoxy resin 1 does not exist, moisture does not accumulate at the interface between the back surface of the die pad 3 and the resin 1, and package cracking due to vaporization expansion of this moisture does not occur. . Further, since the back surface of the die pad 3 is exposed, even if the moisture at the interface between the back surface of the chip 4 and the die pad 3 is vaporized by heating during mounting, the vaporized vapor follows the side surface of the die pad 3 and immediately It can be released to the outside and does not lead to package cracks. From these, it can be said that the semiconductor device is excellent in crack resistance.
【００１５】また、樹脂１がチップ４の上方に流れるよ
うにキャビティ１４内に樹脂１を注入すると、その樹脂
１の圧力によりチップ４を固定したダイパッド３は下に
沈み金型Ａに当接してその姿勢が規制される。このた
め、樹脂１の注入においてダイパッド３が上下にシフト
することがなく、ワイヤ２に対しても負担が小さくな
る。特に薄形のパッケージの場合でもワイヤ２がパッケ
ージ表面に露出したり切れるというようなことがなく、
安定した成形が行える。Further, when the resin 1 is injected into the cavity 14 so that the resin 1 flows above the chip 4, the die pad 3 to which the chip 4 is fixed by the pressure of the resin 1 sinks downward and contacts the die A. Its attitude is regulated. Therefore, the die pad 3 does not shift up and down when the resin 1 is injected, and the load on the wire 2 is reduced. Even in the case of a thin package, the wire 2 is not exposed or cut on the package surface,
Stable molding can be performed.
【００１６】なお、ダイパッド３を金型Ａの下型１３に
接した状態で樹脂成形を行ってもよい。Resin molding may be performed with the die pad 3 in contact with the lower mold 13 of the mold A.
【００１７】[0017]
【発明の効果】請求項１記載の半導体装置によれば、ダ
イパッドの裏面が外部に露出しているので、ダイパッド
の裏面の樹脂の厚み分、薄形化を図ることができる。ま
た、外形においても従来のものとでは厚み以外変わると
ころはないので、実装についても従来の技術を持って実
施できる。また、ダイパッド裏面が露出していることか
ら、放熱性に優れている。さらに、本構造はダイパッド
裏面とエポキシ樹脂との界面が存在しないため、ダイパ
ッド裏面と樹脂との界面に水分が溜まらず、この水分の
気化膨張によるパッケージクラックを引き起こすことが
ない。また、ダイパッド裏面が露出していることから、
チップ裏面とダイパッドとの界面にある水分が実装中の
加熱により気化しても、気化した蒸気はダイパッド側面
をたどり、即外部に逃がすことができ、パッケージクラ
ックには至らない。これらのことより耐クラック性にお
いても優れた半導体装置といえる。According to the semiconductor device of the first aspect, since the back surface of the die pad is exposed to the outside, it is possible to reduce the thickness of the resin on the back surface of the die pad by the thickness. Also, since the outer shape is the same as the conventional one except for the thickness, the mounting can be performed with the conventional technique. Further, since the back surface of the die pad is exposed, it has excellent heat dissipation. Further, in this structure, since the interface between the back surface of the die pad and the epoxy resin does not exist, moisture does not collect at the interface between the back surface of the die pad and the resin, and package cracking due to vaporization and expansion of the moisture does not occur. Also, since the back surface of the die pad is exposed,
Even if the moisture on the interface between the back surface of the chip and the die pad is vaporized by heating during mounting, the vaporized vapor can trace the side surface of the die pad and immediately escape to the outside, which does not lead to package cracking. From these, it can be said that the semiconductor device is excellent in crack resistance.
【００１８】請求項２記載の半導体装置の成形方法によ
れば、樹脂がチップの上方に流れるようにキャビティ内
に樹脂を注入すると、その樹脂の圧力によりチップを固
定したダイパッドは下に沈み金型に当接してその姿勢が
規制される。このため、樹脂注入においてダイパッドが
上下にシフトすることがなく、ワイヤに対しても負担が
小さくなる。特に薄形のパッケージの場合でもワイヤが
パッケージ表面に露出したり切れるというようなことが
なく、安定した成形が行える。また、成形後のパッケー
ジは、ダイパッド裏面がパッケージの外部に露出し、請
求項１と同様の効果が得られる。According to the method of molding a semiconductor device of the second aspect, when the resin is injected into the cavity so that the resin flows above the chip, the die pad fixing the chip is sunk by the pressure of the resin and the mold is sunk. And its posture is regulated. Therefore, the die pad does not shift up and down during resin injection, and the load on the wire is reduced. In particular, even in the case of a thin package, the wire is not exposed or cut on the package surface, and stable molding can be performed. Further, in the package after molding, the back surface of the die pad is exposed to the outside of the package, and the same effect as in claim 1 is obtained.
【図１】この発明の実施の形態の半導体装置の断面側面
図である。FIG. 1 is a sectional side view of a semiconductor device according to an embodiment of the present invention.
【図２】ワイヤーボンド済み製品を金型に設置した状態
の説明図である。FIG. 2 is an explanatory diagram showing a state in which a wire-bonded product is installed in a mold.
【図３】ワイヤーボンド済み製品を金型に設置した後、
樹脂を注入している状態の説明図である。[Fig. 3] After installing the wire-bonded product in the mold,
It is explanatory drawing of the state which is injecting resin.
【図４】封止済み製品をダイパッドが露出している側か
ら見た平面図である。FIG. 4 is a plan view of the sealed product as seen from the side where the die pad is exposed.
１ 樹脂 ２ ワイヤ ３ ダイパッド ４ チップ ５ リード ７ ランナ ８ ゲート口 １０ 薄ばり １２ 上型 １３ 下型 １４ キャビティ １５ 外周部 Ａ 金型 1 Resin 2 Wire 3 Die Pad 4 Chip 5 Lead 7 Runner 8 Gate Port 10 Light Beam 12 Upper Die 13 Lower Die 14 Cavity 15 Outer Part A Mold
Claims (2)
その全体を樹脂で被覆した半導体装置であって、前記ダ
イパッドの裏面が外部に露出したことを特徴とする半導
体装置。1. A chip is fixed on the surface of a die pad,
A semiconductor device having the entire surface thereof covered with a resin, wherein the back surface of the die pad is exposed to the outside.
のチップとリードをワイヤで接続する工程と、分割可能
な金型の対向面に形成されたキャビティに前記チップお
よびダイパッドを配置した状態で前記リードを前記キャ
ビティの外周部で保持する工程と、前記チップの上方に
流れるように樹脂を前記キャビティ内に注入する工程と
を含む半導体装置の成形方法。2. A step of fixing a chip on a surface of a die pad and connecting the chip and a lead with a wire, and a state in which the chip and the die pad are arranged in a cavity formed on a facing surface of a mold that can be divided. A method of molding a semiconductor device, comprising: a step of holding a lead on an outer peripheral portion of the cavity; and a step of injecting a resin into the cavity so as to flow above the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP470096A JP3023303B2 (en) | 1996-01-16 | 1996-01-16 | Semiconductor device molding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP470096A JP3023303B2 (en) | 1996-01-16 | 1996-01-16 | Semiconductor device molding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09199639A true JPH09199639A (en) | 1997-07-31 |
| JP3023303B2 JP3023303B2 (en) | 2000-03-21 |
Family
ID=11591168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP470096A Expired - Fee Related JP3023303B2 (en) | 1996-01-16 | 1996-01-16 | Semiconductor device molding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3023303B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008130750A (en) * | 2006-11-20 | 2008-06-05 | Rohm Co Ltd | Semiconductor device |
| JPWO2016072012A1 (en) * | 2014-11-07 | 2017-06-22 | 三菱電機株式会社 | Power semiconductor device and manufacturing method thereof |
| JPWO2017002268A1 (en) * | 2015-07-02 | 2017-10-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US11088056B2 (en) | 2018-10-24 | 2021-08-10 | Mitsui High-Tec, Inc. | Leadframe and leadframe package |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04114455A (en) * | 1990-09-05 | 1992-04-15 | Seiko Epson Corp | Semiconductor device and mounting structure thereof |
| JPH0529529A (en) * | 1991-07-24 | 1993-02-05 | Matsushita Electron Corp | Resin-sealed semiconductor device |
| JPH06252318A (en) * | 1993-02-26 | 1994-09-09 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH0730016A (en) * | 1993-06-24 | 1995-01-31 | Fujitsu Ltd | Semiconductor device with heat radiating plate and manufacture thereof |
-
1996
- 1996-01-16 JP JP470096A patent/JP3023303B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04114455A (en) * | 1990-09-05 | 1992-04-15 | Seiko Epson Corp | Semiconductor device and mounting structure thereof |
| JPH0529529A (en) * | 1991-07-24 | 1993-02-05 | Matsushita Electron Corp | Resin-sealed semiconductor device |
| JPH06252318A (en) * | 1993-02-26 | 1994-09-09 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH0730016A (en) * | 1993-06-24 | 1995-01-31 | Fujitsu Ltd | Semiconductor device with heat radiating plate and manufacture thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008130750A (en) * | 2006-11-20 | 2008-06-05 | Rohm Co Ltd | Semiconductor device |
| JPWO2016072012A1 (en) * | 2014-11-07 | 2017-06-22 | 三菱電機株式会社 | Power semiconductor device and manufacturing method thereof |
| JPWO2017002268A1 (en) * | 2015-07-02 | 2017-10-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US11088056B2 (en) | 2018-10-24 | 2021-08-10 | Mitsui High-Tec, Inc. | Leadframe and leadframe package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3023303B2 (en) | 2000-03-21 |
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