JPH10326800A - Manufacture of semiconductor device and mold for semiconductor manufacturing device - Google Patents

Manufacture of semiconductor device and mold for semiconductor manufacturing device

Info

Publication number
JPH10326800A
JPH10326800A JP13536897A JP13536897A JPH10326800A JP H10326800 A JPH10326800 A JP H10326800A JP 13536897 A JP13536897 A JP 13536897A JP 13536897 A JP13536897 A JP 13536897A JP H10326800 A JPH10326800 A JP H10326800A
Authority
JP
Japan
Prior art keywords
mold
substrate
resin
semiconductor
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP13536897A
Other languages
Japanese (ja)
Inventor
Naoki Nishizawa
直樹 西沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP13536897A priority Critical patent/JPH10326800A/en
Publication of JPH10326800A publication Critical patent/JPH10326800A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Moulds For Moulding Plastics Or The Like (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the warping of a plastic package, practically, such a package that is formed by sealing one surface of a substrate, such as the BGA, etc., with a resin caused by the difference in coefficient of thermal contraction of the package. SOLUTION: A substrate is warped in advance in the direction opposite to the warping direction of the package before the substrate is sealed with a resin 8. In a mold (first mold) 1 a recessed section (cavity) 3 for enclosing the resin 8 and the flowing passage (runner) 4 for resin communicated with the cavity 3 are provided. In another mold (second mold) 2, a convex part 5 is provided at the position where the center of the convex part 5 comes to the center of the cavity 3 when the molds 1 and 2 are put together. A substrate 7 mounted with a semiconductor 6 is set in the mold 1 with the semiconductor 6 on the down side so that the semiconductor 6 may come to the center of the cavity 3. Therefore, the substrate 7 is curved by means of the convex part of the mold 2 and, while the substrate 7 is curved, the cavity 3 is filled up with the resin 8 through the runner 4.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はプラスチックパッケ
ージの樹脂封止後に発生するパッケージの反りを防止す
る方法と、防止するための製造装置に関するののであ
り、特にボールグリッドアレイのような基板片面に樹脂
封止するプラスチックパッケージにに適した半導体製造
方法及び製造装置に関する物である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for preventing a package from being warped after a plastic package is sealed with a resin, and a manufacturing apparatus for preventing the warpage. The present invention relates to a semiconductor manufacturing method and a manufacturing apparatus suitable for a plastic package to be sealed.

【0002】[0002]

【従来の技術】従来プラスチックパッケージの樹脂封止
工程は、150℃から200℃程度の間に加熱された上
下金型の間に半導体を搭載した基板を挟み込み、キャビ
ティーと呼ばれるパッケージを形成するため金型に設け
られたくぼみの部分に、ランナーとよばれる樹脂の流入
経路をを通して樹脂を封入しあるる程度熱による硬化が
進んだ後金型を開いて樹脂封入の終了した基板を取り出
す工程であるが、この時半導体を搭載した基板は、平板
状で金型同士に挟み込まれていた。
2. Description of the Related Art Conventionally, a resin encapsulation process of a plastic package involves forming a package called a cavity by sandwiching a substrate on which a semiconductor is mounted between upper and lower molds heated to about 150 ° C. to 200 ° C. In the process of taking out the resin-filled substrate after opening the mold after the resin is sealed in the cavity provided in the mold through a resin inflow path called a runner and curing by a certain degree of heat has progressed. However, at this time, the substrate on which the semiconductor was mounted was flat and sandwiched between molds.

【0003】[0003]

【発明が解決しようとする課題】樹脂封入を行い、パッ
ケージが形成された後、常温までパッケージ温度が下が
ってくると、封入樹脂と基板の熱収縮率の違いのため、
パッケージに反りが生じてくる。一般に基板に用いられ
る材料、例えばガラスエポキシ、BTレジン、ポリイミ
ド等の熱収縮率よりも、エポキシやビフェニル樹脂を主
剤に、シリカ粒子を配合したパッケージ形成用樹脂の熱
収縮率の方がが大きいため、パッケージは基板面側の中
央部が凸状になるようにそってしまう。
After the resin is sealed and the package is formed, when the package temperature falls to room temperature, the difference in the heat shrinkage between the sealed resin and the substrate causes the difference.
The package warps. In general, the heat shrinkage of a resin for forming a package containing silica particles as a main component is larger than the heat shrinkage of a material used for a substrate, for example, glass epoxy, BT resin, polyimide, etc. The package is bent so that the central portion on the substrate surface side is convex.

【0004】このようにパッケージに反りが生ずると、
パッケージを基板に実装する時、パッケージの接続端子
が、基板上に設けてある接続用のランドに均一に接する
ことができず、実装不良となってしまう場合があった。
When the package is warped as described above,
When a package is mounted on a substrate, the connection terminals of the package may not uniformly contact the connection lands provided on the substrate, resulting in a mounting failure.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
に本発明はなされたもので、請求項1に記載の半導体装
置の製造方法は、回路基板の一方の面側は外部端子が形
成され、前記回路基板の他方の面側には半導体チップが
搭載され、前記半導体チップがプラスチック樹脂にて封
止される半導体装置の製造方法であって、前記プラスチ
ック樹脂にて前記半導体チップを封止する工程におい
て、前記半導体チップを搭載した基板を湾曲させた状態
にて封止を行うことを特徴とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein an external terminal is formed on one surface of a circuit board. A method for manufacturing a semiconductor device in which a semiconductor chip is mounted on the other surface side of the circuit board and the semiconductor chip is sealed with a plastic resin, wherein the semiconductor chip is sealed with the plastic resin In the step, sealing is performed in a state where the substrate on which the semiconductor chip is mounted is curved.

【0006】また、請求項2に記載のように請求項1の
方法に加えて、前記回路基板を前記半導体チップの搭載
された面の相反する面側に湾曲させた状態にて前記プラ
スチック樹脂による封止を行うことを特徴とする。すな
わち、基板と樹脂の熱収縮率の違いによるパッケージの
反りを改善するため、樹脂封入時に予めパッケージ完成
後に反る方向と逆方向に基板に反りを加える事を特徴と
する。
According to a second aspect of the present invention, in addition to the method of the first aspect, the circuit board is formed of the plastic resin in a state where the circuit board is curved to a side opposite to a side on which the semiconductor chip is mounted. Sealing is performed. That is, in order to improve the warpage of the package due to the difference in the thermal shrinkage between the substrate and the resin, the substrate is characterized in that the substrate is warped in the direction opposite to the warping direction after the package is completed before sealing the resin.

【0007】また、本発明における半導体製造装置用金
型としては、請求項3に記載のように、回路基板の一方
の面側は外部端子が形成され、前記回路基板の他方の面
側には半導体チップが搭載され、前記半導体チップがプ
ラスチック樹脂にて封止するための半導体製造装置用金
型であって、前記回路基板における前記半導体チップの
搭載された面側に位置し、前記半導体チップを含み、樹
脂の注入される凹部が形成された第1金型と、前記回路
基板における前記半導体チップの搭載された面に相対す
る面側において、前記回路基板の前記面と当接する位置
に凸形状を設けてなる第2金型と、を有してなることを
特徴とする。つまり、ここで基板に反りを加える手段と
しては、金型の基板に反りを加える部分に接する部分に
凸形状を加え、上下金型で基板を挟み込んだとき、金型
の凸部が基板を押し、結果として基板に反りが加わるよ
うにする。金型の凸形状は基板を反らした時、基板と金
型の間に隙間が出来ない形状が金型の熱が基板に最も伝
わり易い為好ましいが、イジェクタピンの様に一点支持
にしても構わない。反りが最も大きくなる場所はパッケ
ージの中心となる位置にする。
According to a third aspect of the present invention, an external terminal is formed on one surface of a circuit board and the other surface of the circuit board is formed on the other surface of the circuit board. A semiconductor chip is mounted, the semiconductor chip is a mold for a semiconductor manufacturing apparatus for sealing with a plastic resin, and is located on a surface side of the circuit board on which the semiconductor chip is mounted, and the semiconductor chip is A first mold in which a concave portion into which resin is injected is formed, and a convex shape is formed at a position in contact with the surface of the circuit board on a surface side of the circuit board opposite to a surface on which the semiconductor chip is mounted. And a second mold provided with the second mold. In other words, here, as means for warping the substrate, a convex shape is added to a portion in contact with a portion of the mold that warps the substrate, and when the substrate is sandwiched between the upper and lower molds, the convex portion of the mold pushes the substrate. As a result, the substrate is warped. The convex shape of the mold is preferably a shape in which no gap is formed between the substrate and the mold when the substrate is warped, since the heat of the mold is most easily transmitted to the substrate, but it may be supported at one point like an ejector pin. Absent. The location where the warp is greatest is located at the center of the package.

【0008】[0008]

【発明の実施の形態】以下、本発明の実施方法の一例を
図面に基づいて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0009】図面1は、樹脂封止に用いる金型に半導体
を搭載した基板を載せた状態の断面図であり、図面2は
上下金型で半導体を搭載した基板を挟み込んだ状態の断
面図、図面3は樹脂封入直後のパッケーを示した図面、
図面4は常温に下がった時のパッケージを示した図面で
ある。
FIG. 1 is a cross-sectional view of a state in which a substrate on which a semiconductor is mounted is mounted on a mold used for resin sealing, and FIG. 2 is a cross-sectional view of a state in which the substrate on which the semiconductor is mounted is sandwiched between upper and lower dies. Drawing 3 is a drawing showing the package immediately after resin encapsulation,
FIG. 4 is a drawing showing the package when it has been cooled to room temperature.

【0010】まず図面1において樹脂封止用半導体製造
装置を説明する。樹脂封止に用いる装置は150℃から
200℃程度に加熱した金型1金型2にて構成されてい
る。金型1(第1金型)には樹脂を封入するためのくぼ
み3(以後キャビティーと呼ぶ)と、キャビティー3に
通じる樹脂の流動路4(以後ランナーと呼ぶ)が設けら
れている。
First, a semiconductor manufacturing apparatus for resin encapsulation will be described with reference to FIG. The apparatus used for resin sealing is composed of a mold 1 and a mold 2 heated to about 150 ° C. to 200 ° C. The mold 1 (first mold) is provided with a cavity 3 (hereinafter referred to as a cavity) for enclosing the resin, and a resin flow path 4 (hereinafter referred to as a runner) leading to the cavity 3.

【0011】金型2(第2金型)には本発明の特徴であ
る凸形状5が設けられており、凸形状の位置は金型1,
2を重ね合わせたとき、その中心が金型1のキャビティ
ー3の中心にくるようにしてある。
The mold 2 (second mold) is provided with a convex shape 5 which is a feature of the present invention.
When the two are superimposed, the center of the two is located at the center of the cavity 3 of the mold 1.

【0012】半導体6を搭載した基板7は半導体6がキ
ャビティー3のセンターにくるように半導体6を下向き
して金型1にセットされる。
The substrate 7 on which the semiconductor 6 is mounted is set in the mold 1 with the semiconductor 6 facing downward so that the semiconductor 6 is at the center of the cavity 3.

【0013】図面2は基板7を金型1にセットした後、
樹脂を充填するため、金型2にて挟み込んだ状態を示し
ている。
FIG. 2 shows that after the substrate 7 is set in the mold 1,
The figure shows a state where the resin is sandwiched by the mold 2 to fill the resin.

【0014】基板7は、金型2に設けた凸形状5によっ
て湾曲した状態となり、そこにランナー4を通じて樹脂
8がキャビティー3の内部に充填される。
The substrate 7 is curved by the convex shape 5 provided on the mold 2, and the resin 8 is filled into the cavity 3 through the runner 4.

【0015】図面3は樹脂封止直後のパッケージ9を示
している。パッケージは金型2の凸形状5により基板側
中央部が凹となるように湾曲している。
FIG. 3 shows the package 9 immediately after resin sealing. The package is curved by the convex shape 5 of the mold 2 so that the central portion on the substrate side is concave.

【0016】図面4はパッケージ9が常温まで温度が下
がった状態を示している。パッケージ9を構成する樹脂
8と基板7の熱収縮率の差によりパッケージの湾曲が矯
正され、結果としてパッケージ9は平坦な形状となる。
しかる後、基板7に半田ボールを搭載するとボールグリ
ッドアレイのパッケージができあがる。
FIG. 4 shows a state where the temperature of the package 9 has been lowered to room temperature. The curvature of the package is corrected by the difference in the thermal shrinkage between the resin 8 and the substrate 7 constituting the package 9, and as a result, the package 9 has a flat shape.
Thereafter, when solder balls are mounted on the substrate 7, a package of a ball grid array is completed.

【0017】[0017]

【発明の効果】本発明により、基板片面に樹脂封止をし
たプラスチックパッケージの熱収縮率の違いによる反り
は改善でき、パッケージの基板実装時円滑に実装する事
ができる。
According to the present invention, the warpage due to the difference in the thermal shrinkage of the plastic package having one side of the substrate resin-sealed can be improved and the package can be mounted smoothly when mounted on the substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】樹脂封止に用いる金型に半導体を登載した基板
を乗せた図。
FIG. 1 is a diagram in which a substrate on which a semiconductor is mounted is placed on a mold used for resin sealing.

【図2】図面1の金型を樹脂封止のためクランプした
図。
FIG. 2 is a diagram in which the mold of FIG. 1 is clamped for resin sealing.

【図3】図1の装置及び方法によって樹脂封止された直
後のプラスチックパッケージを示す図。
FIG. 3 is a view showing a plastic package immediately after resin sealing by the apparatus and method of FIG. 1;

【図4】図3のパッケージが常温に冷えた状態を示す
図。
FIG. 4 is a diagram showing a state in which the package of FIG. 3 has cooled to room temperature.

【符号の説明】[Explanation of symbols]

1・・・金型(下型) 2・・・金型(上型) 3・・・キャビティー 4・・・ランナー 5・・・凸形状 6・・・半導体 7・・・基板 8・・・樹脂 9・・・プラスチックパッケージ DESCRIPTION OF SYMBOLS 1 ... Die (lower die) 2 ... Die (upper die) 3 ... Cavity 4 ... Runner 5 ... Convex shape 6 ... Semiconductor 7 ... Substrate 8 ...・ Resin 9 ・ ・ ・ Plastic package

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】回路基板の一方の面側は外部端子が形成さ
れ、前記回路基板の他方の面側には半導体チップが搭載
され、前記半導体チップがプラスチック樹脂にて封止さ
れる半導体装置の製造方法であって、前記プラスチック
樹脂にて前記半導体チップを封止する工程において、前
記半導体チップを搭載した基板を湾曲させた状態にて封
止を行うことを特徴とする半導体装置の製造方法。
An external terminal is formed on one side of a circuit board, a semiconductor chip is mounted on the other side of the circuit board, and the semiconductor chip is sealed with a plastic resin. A method of manufacturing a semiconductor device, wherein in the step of sealing the semiconductor chip with the plastic resin, sealing is performed in a state where a substrate on which the semiconductor chip is mounted is curved.
【請求項2】前記回路基板を前記半導体チップの搭載さ
れた面の相反する面側に湾曲させた状態にて前記プラス
チック樹脂による封止を行うことを特徴とする請求項1
記載の半導体装置の製造方法。
2. The method according to claim 1, wherein said circuit board is sealed with said plastic resin in a state where said circuit board is curved to a surface opposite to a surface on which said semiconductor chip is mounted.
The manufacturing method of the semiconductor device described in the above.
【請求項3】回路基板の一方の面側は外部端子が形成さ
れ、前記回路基板の他方の面側には半導体チップが搭載
され、前記半導体チップがプラスチック樹脂にて封止す
るための半導体製造装置用金型であって、前記回路基板
における前記半導体チップの搭載された面側に位置し、
前記半導体チップを含み、樹脂の注入される凹部が形成
された第1金型と、前記回路基板における前記半導体チ
ップの搭載された面に相対する面側において、前記回路
基板の前記面と当接する位置に凸形状を設けてなる第2
金型と、を有してなることを特徴とする半導体製造装置
用金型。
3. A semiconductor manufacturing method in which external terminals are formed on one side of a circuit board, a semiconductor chip is mounted on the other side of the circuit board, and the semiconductor chip is sealed with a plastic resin. An apparatus mold, which is located on a side of the circuit board on which the semiconductor chip is mounted,
A first mold including the semiconductor chip and having a recess into which resin is injected, and a surface of the circuit board facing the surface of the circuit board on a surface side opposite to a surface on which the semiconductor chip is mounted; The second having a convex shape at the position
A mold for a semiconductor manufacturing apparatus, comprising: a mold;
JP13536897A 1997-05-26 1997-05-26 Manufacture of semiconductor device and mold for semiconductor manufacturing device Withdrawn JPH10326800A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13536897A JPH10326800A (en) 1997-05-26 1997-05-26 Manufacture of semiconductor device and mold for semiconductor manufacturing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13536897A JPH10326800A (en) 1997-05-26 1997-05-26 Manufacture of semiconductor device and mold for semiconductor manufacturing device

Publications (1)

Publication Number Publication Date
JPH10326800A true JPH10326800A (en) 1998-12-08

Family

ID=15150099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13536897A Withdrawn JPH10326800A (en) 1997-05-26 1997-05-26 Manufacture of semiconductor device and mold for semiconductor manufacturing device

Country Status (1)

Country Link
JP (1) JPH10326800A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100567129B1 (en) * 2001-04-13 2006-03-31 앰코 테크놀로지 코리아 주식회사 Molding die for manufacturing semiconductor package and method for molding semiconductor package using the same
EP1946373A2 (en) * 2005-10-19 2008-07-23 Texas Instruments Incorporated Semiconductor assembly for improved device warpage and solder ball coplanarity
US7563651B2 (en) 2005-04-11 2009-07-21 Nec Electronics Corporation Method of fabricating a substrate with a concave surface
JP2010214595A (en) * 2009-03-13 2010-09-30 Apic Yamada Corp Resin sealing apparatus
US8198141B2 (en) 2008-12-15 2012-06-12 Elpida Memory, Inc. Intermediate structure of semiconductor device and method of manufacturing the same
JP2014154806A (en) * 2013-02-13 2014-08-25 Fuji Electric Co Ltd Semiconductor device manufacturing method
CN107978533A (en) * 2016-10-25 2018-05-01 南亚科技股份有限公司 Semiconductor structure and its manufacture method
CN108010877A (en) * 2017-12-29 2018-05-08 中芯长电半导体(江阴)有限公司 The encapsulating structure and method for packing of semiconductor chip
JP2021156516A (en) * 2020-03-27 2021-10-07 三菱電機株式会社 Method for manufacturing decorative grille
CN113799316A (en) * 2020-06-17 2021-12-17 五行科技股份有限公司 Method for manufacturing composite board
CN113811104A (en) * 2020-06-17 2021-12-17 五行科技股份有限公司 Composite board and manufacturing method thereof
US20230061379A1 (en) * 2021-08-24 2023-03-02 Applied Materials, Inc. Low warpage curing methodology by inducing curvature

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100567129B1 (en) * 2001-04-13 2006-03-31 앰코 테크놀로지 코리아 주식회사 Molding die for manufacturing semiconductor package and method for molding semiconductor package using the same
US7563651B2 (en) 2005-04-11 2009-07-21 Nec Electronics Corporation Method of fabricating a substrate with a concave surface
EP1946373A2 (en) * 2005-10-19 2008-07-23 Texas Instruments Incorporated Semiconductor assembly for improved device warpage and solder ball coplanarity
EP1946373A4 (en) * 2005-10-19 2010-04-07 Texas Instruments Inc Semiconductor assembly for improved device warpage and solder ball coplanarity
US8198141B2 (en) 2008-12-15 2012-06-12 Elpida Memory, Inc. Intermediate structure of semiconductor device and method of manufacturing the same
JP2010214595A (en) * 2009-03-13 2010-09-30 Apic Yamada Corp Resin sealing apparatus
JP2014154806A (en) * 2013-02-13 2014-08-25 Fuji Electric Co Ltd Semiconductor device manufacturing method
CN107978533A (en) * 2016-10-25 2018-05-01 南亚科技股份有限公司 Semiconductor structure and its manufacture method
CN108010877A (en) * 2017-12-29 2018-05-08 中芯长电半导体(江阴)有限公司 The encapsulating structure and method for packing of semiconductor chip
JP2021156516A (en) * 2020-03-27 2021-10-07 三菱電機株式会社 Method for manufacturing decorative grille
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