JPS6020596A - Method of producing hybrid integrated circuit - Google Patents
Method of producing hybrid integrated circuitInfo
- Publication number
- JPS6020596A JPS6020596A JP12912683A JP12912683A JPS6020596A JP S6020596 A JPS6020596 A JP S6020596A JP 12912683 A JP12912683 A JP 12912683A JP 12912683 A JP12912683 A JP 12912683A JP S6020596 A JPS6020596 A JP S6020596A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- resin
- coating
- producing hybrid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はデュアルインライン型混成集積回路の製造方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a dual-in-line hybrid integrated circuit.
一般にデュアルインフィン型の混成集積回路の多くはケ
ースに収納され、外被したものや、トランスファー、セ
ラミック外装などで外被されている。Generally, many dual-in-fin type hybrid integrated circuits are housed in a case and covered with an outer cover, a transfer case, a ceramic outer cover, etc.
しかし、これらの方法はいずれも一般電子部品の樹脂デ
ィッピング法による外装に比較して工数が多く、また材
料費用が商いものとなっていたためコストダウ２２図る
べく腎力しているか、充分な効果を奏することができな
かった。However, all of these methods require more man-hours than the resin-dipping method used to package general electronic components, and material costs are high, so efforts are being made to reduce costs22, or they are not sufficiently effective. I couldn't.
したがって、一般電子部品の外装方法である樹脂ディッ
プ法により外装すると、夷１図に示すように塗料の表面
張力などにより平面基板１の両端に装着された引出リー
ド線２−トに不要な塗料Ｈが塗装３され、混成集積回路
をプリント基板に組込んで半田付けしたとき、塗料３の
上から半田付けされるため半田付は不良となる欠点があ
った。またこのようにリード線２上の塗料Ｈを少なくし
て塗装すると第２図のように基板１の全体が樹脂で覆わ
れなく基板１の一部が露出し均一な樹脂塗装ができず、
したがって修正などによυ均一な外観を構成しようとす
ると多大な工数を有する。一方基板露出の状態ではヒー
トサイクル試験で樹脂の応力が基板に均一にかからず破
壊に到らしめる。Therefore, when packaging with the resin dipping method, which is a packaging method for general electronic components, unnecessary paint H is applied to the lead wires 2 attached to both ends of the flat board 1 due to the surface tension of the paint, as shown in Figure 1. When the hybrid integrated circuit is assembled into a printed circuit board and soldered with paint 3, there is a drawback that the soldering is defective because the soldering is done over the paint 3. Also, if the paint H on the lead wire 2 is reduced in this way, the entire board 1 will not be covered with resin as shown in Fig. 2, and a part of the board 1 will be exposed, making it impossible to apply the resin uniformly.
Therefore, it takes a large amount of man-hours to construct a uniform appearance through modification or the like. On the other hand, when the substrate is exposed, the stress of the resin is not uniformly applied to the substrate during a heat cycle test, leading to destruction.
また耐湿性においても問題のあるものであった。Moreover, there was also a problem in moisture resistance.
本発明は上述の欠点を除去するもので、デュアルインフ
ィン型混成集積回路基板にあらかじめ部品などが載置さ
れた該基板の両端に倒立するリード線間の基板面に粉体
樹脂を塗布し、その後他面に同一塗料を塗布してなる完
全基板被覆を行なってなる混成集積回路の製造方法を提
供するものである。The present invention eliminates the above-mentioned drawbacks by applying powder resin to the board surface between the lead wires that are inverted at both ends of a dual-in-fin type hybrid integrated circuit board on which components are mounted in advance. The present invention provides a method for manufacturing a hybrid integrated circuit by completely covering the substrate by applying the same paint to the other side.
以下、第３図に示す実施例により詳述する。The present invention will be explained in detail below using the embodiment shown in FIG.
第３図は本発明の一実施例の混成集積回路の断面図で、
１１は基板、１２はリード線、１３は１次塗装樹脂、１
４は２次塗装樹脂を示し、アｌレミナ、ホーローなどの
基板ＩＩの表面に電極パターンを配し、該パターン上に
ＩＣ、コンデンサ、抵抗１５などを、またリード線１２
を配して構成された混成集積回路素子のリード引出し側
のへ版面に粉体樹脂１３を塗布する１次塗装を行い、そ
の後他面と基板全体をガう粉体樹脂内で２次塗装を行い
熱硬化してなる混成集積回路の製造方法である。FIG. 3 is a cross-sectional view of a hybrid integrated circuit according to an embodiment of the present invention.
11 is a board, 12 is a lead wire, 13 is a primary coating resin, 1
Reference numeral 4 indicates a secondary coating resin, and an electrode pattern is arranged on the surface of a substrate II made of alumina, enamel, etc., and an IC, a capacitor, a resistor 15, etc. are placed on the pattern, and a lead wire 12 is placed on the surface of the substrate II.
A first coating is applied by applying powder resin 13 to the front surface of the lead drawer side of the hybrid integrated circuit element configured by disposing the wafer, and then a second coating is applied in the powder resin to the other surface and the entire board. This is a method of manufacturing a hybrid integrated circuit formed by heating and curing.
なお、上述の実施例において、粉体樹脂１３．１４の硬
化は熱硬化性としたが、光硬化性樹脂であってもよい。In the above embodiments, the powder resins 13 and 14 were cured by thermosetting, but they may also be photocurable resins.
以上のように本発明は、粉体樹脂で第１次塗装し、さら
に第２次塗装して外缶しているのて、液状樹脂のように
流れ落ちず、樹脂被覆量および厚みがコントロールしゃ
すく均−七なり、耐ヒートサイクル性、耐水性に優れ工
業上有益なものである。As described above, the present invention uses a powder resin for the first coating and then a second coating for the outer can, so unlike liquid resin, it does not run off and the amount and thickness of the resin coating can be easily controlled. It has excellent heat cycle resistance and water resistance, and is industrially useful.
第１図および第２図は従来の混成集積回路の断面図、第
３図は本発明の一実施例の混成集積回路の断面図である
。
１１：基 板
１２： リード線
１３：１次塗装樹脂
１４：２次塗装樹脂
特許出願人
日本コンデンサ工業株式会社1 and 2 are cross-sectional views of a conventional hybrid integrated circuit, and FIG. 3 is a cross-sectional view of a hybrid integrated circuit according to an embodiment of the present invention. 11: Substrate 12: Lead wire 13: Primary coating resin 14: Secondary coating resin Patent applicant Nippon Capacitor Industries Co., Ltd.
Claims (1)
において、該混成８ｉ！！積回路の基板の一方の而に粉
体樹脂を１次塗装し、次いで他面を同一材料で２次塗装
し硬化させてなる混成集積回路の製造方法。In a powder resin packaging method for a dual in-line hybrid integrated circuit, the hybrid 8i! ! A method for manufacturing a hybrid integrated circuit, which comprises firstly coating one side of a substrate of the integrated circuit with a powder resin, then secondly coating the other side with the same material and curing it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12912683A JPS6020596A (en) | 1983-07-14 | 1983-07-14 | Method of producing hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12912683A JPS6020596A (en) | 1983-07-14 | 1983-07-14 | Method of producing hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6020596A true JPS6020596A (en) | 1985-02-01 |
Family
ID=15001728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12912683A Pending JPS6020596A (en) | 1983-07-14 | 1983-07-14 | Method of producing hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020596A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62180692U (en) * | 1986-05-09 | 1987-11-16 | ||
| JPS6373596U (en) * | 1986-10-31 | 1988-05-17 | ||
| JPH02207559A (en) * | 1989-02-07 | 1990-08-17 | Fujitsu Ltd | Two row parallel multi-terminal terminal hybrid integrated circuit device |
| JP2017115039A (en) * | 2015-12-24 | 2017-06-29 | 株式会社フロロテクノロジー | Protective coating agent for printed wiring board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5438559A (en) * | 1977-09-02 | 1979-03-23 | Hitachi Ltd | Method of protecting outside of hybrid integrated circuit |
| JPS5756990A (en) * | 1980-09-22 | 1982-04-05 | Matsushita Electric Works Ltd | Method of mounting electronic part |
-
1983
- 1983-07-14 JP JP12912683A patent/JPS6020596A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5438559A (en) * | 1977-09-02 | 1979-03-23 | Hitachi Ltd | Method of protecting outside of hybrid integrated circuit |
| JPS5756990A (en) * | 1980-09-22 | 1982-04-05 | Matsushita Electric Works Ltd | Method of mounting electronic part |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62180692U (en) * | 1986-05-09 | 1987-11-16 | ||
| JPS6373596U (en) * | 1986-10-31 | 1988-05-17 | ||
| JPH02207559A (en) * | 1989-02-07 | 1990-08-17 | Fujitsu Ltd | Two row parallel multi-terminal terminal hybrid integrated circuit device |
| JPH0695561B2 (en) * | 1989-02-07 | 1994-11-24 | 富士通株式会社 | Two-row parallel multi-terminal hybrid integrated circuit device |
| JP2017115039A (en) * | 2015-12-24 | 2017-06-29 | 株式会社フロロテクノロジー | Protective coating agent for printed wiring board |
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