JPS6339969Y2 - - Google Patents
Info
- Publication number
- JPS6339969Y2 JPS6339969Y2 JP19142781U JP19142781U JPS6339969Y2 JP S6339969 Y2 JPS6339969 Y2 JP S6339969Y2 JP 19142781 U JP19142781 U JP 19142781U JP 19142781 U JP19142781 U JP 19142781U JP S6339969 Y2 JPS6339969 Y2 JP S6339969Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- hybrid integrated
- resin
- semiconductor chip
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920005989 resin Polymers 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 11
- 238000005476 soldering Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000000576 coating method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
【考案の詳細な説明】
本考案は混成集積回路の改良に関するものであ
る。DETAILED DESCRIPTION OF THE PRESENT EMBODIMENT The present invention relates to an improvement in hybrid integrated circuits.
一般に混成集積回路は第１図に示すようにアル
ミナなどの絶縁基板１の表面に銀、パラジウム−
銀などの配線導体層２および抵抗体層３をスクリ
ーン印刷法によつて順次印刷、焼成して回路パタ
ーンを形成し、これに半導体チツプ４を塔載しボ
ンデイングワイヤ５でボンデイングし、その上に
シリコン樹脂、エポキシ樹脂などの保護用樹脂７
を塗布し、チツプ形コンデンサなどの個別部品お
よび引出端子６を装着してそれぞれはんだで接続
した後、デイツプ法、粉体塗装法などによつて外
装樹脂８を被覆して構成されていた。しかし上述
の保護用樹脂７を塗布した際、該樹脂７が毛細管
現象により厚膜配線導体層２の表面を伝わつて広
がり、周辺部のはんだ付け用電極ランド部９にに
じみ出た樹脂７′が付着し、個別部品がはんだ付
けできず、断線状態になる欠点があつた。そして
樹脂７′を研摩して除去するなどの手数を要して
いた。そのためボンデイング部の周辺部に保護用
樹脂７の流れを阻止するためガラス層などの絶縁
層の堤を形成したものが考案されているが、印刷
工数が増加するなどの欠点があつた。 In general, hybrid integrated circuits are made of silver, palladium, etc. on the surface of an insulating substrate 1 made of alumina, etc., as shown in
A wiring conductor layer 2 such as silver and a resistor layer 3 are sequentially printed and fired by screen printing to form a circuit pattern, and a semiconductor chip 4 is mounted on this and bonded with a bonding wire 5. Protective resin 7 such as silicone resin and epoxy resin
After applying individual parts such as chip capacitors and lead-out terminals 6 and connecting them with solder, an exterior resin 8 is coated using a dip method, a powder coating method, or the like. However, when the above-mentioned protective resin 7 is applied, the resin 7 spreads along the surface of the thick film wiring conductor layer 2 due to capillary action, and the resin 7' that oozes out adheres to the soldering electrode land 9 in the peripheral area. However, it had the disadvantage that individual parts could not be soldered, resulting in disconnection. Further, it takes time and effort to remove the resin 7' by polishing. Therefore, a method has been devised in which a bank of an insulating layer such as a glass layer is formed around the bonding part in order to prevent the flow of the protective resin 7, but this method has disadvantages such as an increase in the number of printing steps.
本考案は上述の欠点を除去し、安価に生産でき
る混成集積回路を提供するものである。 The present invention eliminates the above-mentioned drawbacks and provides a hybrid integrated circuit that can be produced at low cost.
以下、本考案を第３図および第４図に示す実施
例により説明する。 The present invention will be explained below with reference to the embodiments shown in FIGS. 3 and 4.
第３図は混成集積回路の要部切断正面図で、ア
ルミナなどの絶縁基板１の表面に銀、銀−パラジ
ウム銀などの配線導体層２および抵抗体層３をス
クリーン印刷法によつて順次印刷、焼成して回路
パターンを形成する。このとき半導体チツプ４ま
たはボンデイングワイヤ５と接続する配線導体層
２のボンデイング部と配線導体層２のはんだ付用
電極ランド部９間の配線パターンは屈曲させて印
刷される。 Figure 3 is a cutaway front view of the main parts of a hybrid integrated circuit, in which a wiring conductor layer 2 and a resistor layer 3 made of silver, silver-palladium silver, etc. are sequentially printed on the surface of an insulating substrate 1 made of alumina or the like by screen printing. , and then fired to form a circuit pattern. At this time, the wiring pattern between the bonding portion of the wiring conductor layer 2 connected to the semiconductor chip 4 or the bonding wire 5 and the soldering electrode land portion 9 of the wiring conductor layer 2 is printed in a bent manner.
つぎに半導体チツプ４を熱圧着などして塔載し
ボンデイングワイヤ５でボンデイングし、その上
にシリコン樹脂、エポキシ樹脂などの保護用樹脂
７を塗布すると、第４図に示すように保護用樹脂
７が、毛細管現象により厚膜配線導体層２の表面
を伝わつて広がつても、該配線導体層２が屈曲し
て形成されているので、はんだ付け用電極ランド
部９まで広がらず、にじみ出た樹脂７′がはんだ
付け用電極ランド部９に付着しない。そのためは
んだ付け用電極ランド部９の全面にはんだが付着
できるので、チツプ形コンデンサなどの個別部品
が確実にかつ強固に接続でき、断線事故を防止す
ることができる効果がある。 Next, the semiconductor chip 4 is placed on a tower by thermocompression bonding, bonded with bonding wire 5, and a protective resin 7 such as silicone resin or epoxy resin is applied thereon, as shown in FIG. Even if the resin spreads along the surface of the thick-film wiring conductor layer 2 due to capillarity, the resin does not spread to the soldering electrode land portion 9 because the wiring conductor layer 2 is bent. 7' does not adhere to the soldering electrode land portion 9. Therefore, since solder can be applied to the entire surface of the soldering electrode land portion 9, individual components such as chip capacitors can be connected reliably and firmly, and disconnection accidents can be prevented.
なお、上述の配線導体層２はコの字形に屈曲し
た配線パターンについて述べたが、フの字形など
屈曲の形状は適宣変形でき、その幅も細幅のもの
や順次細くなるように形成してもよい。 Although the wiring conductor layer 2 described above has a wiring pattern bent in a U-shape, the shape of the bend, such as a fold-back shape, can be modified as appropriate, and the width can also be formed to be narrow or gradually become narrower. You can.
叙上のように本考案の混成集積回路は、半導体
チツプとはんだ付け用個別部品が近接して配置さ
れる高密度配線には特に有効で、小形化と生産性
の向上を容易に実現でき、実用的価値の極めて大
なるものである。 As mentioned above, the hybrid integrated circuit of the present invention is particularly effective for high-density wiring in which semiconductor chips and individual soldering components are placed in close proximity, and can easily achieve miniaturization and improve productivity. It has enormous practical value.
第１図は従来の混成集積回路の外装樹脂を一部
切除した要部正面図、第２図は従来の混成集積回
路のはんだ付け要部の斜視図、第３図は本考案の
混成集積回路の一実施例の外装樹脂を一部切除し
た要部正面図、第４図は本考案の混成集積回路の
一実施例のはんだ付け要部の斜視図である。
１：絶縁基板、２：配線導体層、４：半導体チ
ツプ、７：保護用樹脂、９：はんだ付け用ランド
部。
Figure 1 is a front view of the main parts of a conventional hybrid integrated circuit with part of the exterior resin removed, Figure 2 is a perspective view of the soldering main parts of a conventional hybrid integrated circuit, and Figure 3 is the hybrid integrated circuit of the present invention. FIG. 4 is a front view of the main parts of one embodiment of the present invention with the exterior resin partially removed, and FIG. 4 is a perspective view of the main parts to be soldered in one embodiment of the hybrid integrated circuit of the present invention. 1: Insulating substrate, 2: Wiring conductor layer, 4: Semiconductor chip, 7: Protective resin, 9: Land portion for soldering.
Claims (1)
厚膜回路パターンを形成し、半導体チツプをボン
デイングして該半導体チツプのボンデイング部に
保護用樹脂を塗布してなる混成集積回路におい
て、上記半導体チツプのボンデイング部と配線導
体層のはんだ付け用電極ランド部間の配線パター
ンを屈曲させたことを特徴とする混成集積回路。 In a hybrid integrated circuit, a thick film circuit pattern such as a wiring conductor layer and a semiconductor chip is formed on an insulating substrate, a semiconductor chip is bonded, and a protective resin is applied to the bonding portion of the semiconductor chip. A hybrid integrated circuit characterized in that a wiring pattern between a bonding part and a soldering electrode land part of a wiring conductor layer is bent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19142781U JPS5895046U (en) | 1981-12-21 | 1981-12-21 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19142781U JPS5895046U (en) | 1981-12-21 | 1981-12-21 | hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5895046U JPS5895046U (en) | 1983-06-28 |
| JPS6339969Y2 true JPS6339969Y2 (en) | 1988-10-19 |
Family
ID=30104888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19142781U Granted JPS5895046U (en) | 1981-12-21 | 1981-12-21 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5895046U (en) |
-
1981
- 1981-12-21 JP JP19142781U patent/JPS5895046U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5895046U (en) | 1983-06-28 |
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