JPS6038292Y2 - Printed board - Google Patents
Printed boardInfo
- Publication number
- JPS6038292Y2 JPS6038292Y2 JP9730481U JP9730481U JPS6038292Y2 JP S6038292 Y2 JPS6038292 Y2 JP S6038292Y2 JP 9730481 U JP9730481 U JP 9730481U JP 9730481 U JP9730481 U JP 9730481U JP S6038292 Y2 JPS6038292 Y2 JP S6038292Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductive pattern
- solder
- chip component
- resist
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Description
【考案の詳細な説明】
本考案はプリント基板に関し、特に、導電パターンのは
がれが少なく、チップ部品の破損のないものを提供せん
とするものである。[Detailed Description of the Invention] The present invention relates to a printed circuit board, and in particular, it is an object of the present invention to provide a printed circuit board in which conductive patterns are less likely to peel off and chip components are not damaged.
従来、この種のプリント基板１は、第１図、第２図示の
如く、絶縁基板２の一面に対向して形成した導電パター
ン３ａ、３ｂ上に、抵抗器あるいはコンデンサ等のチッ
プ部品４の電極４ａを載置すると共に、プリント基板１
を取付けるための金属製の筐体５を、プリント基板１の
端に配置し、チップ部品４の電極４ａを導電パターン３
ａ、３ｂに半田６付けすると共に、筐体５を導電パター
ン３ａに半田６付けするものであるが、この場合、導電
パターン３ａ面上に半田６が広がり、筐体５と導電パタ
ーン３ａとの間、および、チップ部品４の電極４ａと導
電パターン３ａとの間における半田６ののりが悪く、半
田６量が少なく、半田６付は不良を生ずるという欠点が
あった。Conventionally, this type of printed circuit board 1 has electrodes of chip components 4 such as resistors or capacitors on conductive patterns 3a and 3b formed oppositely on one surface of an insulating substrate 2, as shown in FIGS. 1 and 2. 4a and the printed circuit board 1.
A metal housing 5 for mounting is placed on the edge of the printed circuit board 1, and the electrode 4a of the chip component 4 is connected to the conductive pattern 3.
A, 3b are soldered 6, and the casing 5 is soldered 6 to the conductive pattern 3a. The solder 6 does not adhere well between the electrode 4a of the chip component 4 and the conductive pattern 3a, and the amount of solder 6 is small, resulting in defects in solder 6 attachment.
また、この欠点を解消せんとして、従来、第３図、第４
図の如く、筐体５の半田６付は部と、チップ部品４の半
田６付は部との間において、導電パターン３ａ上を横断
するように、レジスト７を塗布等して形成し、このレジ
スト７によって、導電パターン３ａ上における半田６の
広がりを防止して、筐体５と導電パターン３ａ間、およ
びチップ部品４と導電パターン３ａ間の半田６ののりを
良くしたものである。In addition, in order to eliminate this drawback, conventional
As shown in the figure, a resist 7 is formed by applying or the like across the conductive pattern 3a between the solder 6 part of the casing 5 and the solder 6 part of the chip component 4. The resist 7 prevents the solder 6 from spreading on the conductive pattern 3a, and improves the adhesion of the solder 6 between the casing 5 and the conductive pattern 3a and between the chip component 4 and the conductive pattern 3a.
しかし乍ら、前者および後者は、いずれも、導電パター
ン３ａが絶縁基板２上に帯状に形成され、且つ、半田６
付けされて導電パターン３ａが硬化されたものであり、
従って、熱あるいは経年変化等によって絶縁基板２およ
び半田６付けされた導電パターン３ａは共に伸縮するが
、絶縁基板２と導電パターン３ａの伸縮度合が異なり、
これが帯状の導電パターン３ａ全体に影響を受け、導電
パターン３ａが絶縁基板２からはがれる上に、強度的に
弱い電極４ａと半田６付けとの間に応力が集中して、チ
ップ部品４が破損するという欠点があった。However, in both the former and the latter, the conductive pattern 3a is formed in a band shape on the insulating substrate 2, and the solder 6
conductive pattern 3a is hardened.
Therefore, both the insulating substrate 2 and the conductive pattern 3a attached with the solder 6 expand and contract due to heat or aging, but the degree of expansion and contraction of the insulating substrate 2 and the conductive pattern 3a is different.
This affects the entire strip-shaped conductive pattern 3a, causing the conductive pattern 3a to peel off from the insulating substrate 2, and stress to concentrate between the weak electrode 4a and the solder 6, causing damage to the chip component 4. There was a drawback.
本考案は上記従来の欠点を解消せんとするもので、以下
、本考案を第５図、第６図に基づいて説明する。The present invention aims to solve the above-mentioned drawbacks of the conventional technology, and will be described below with reference to FIGS. 5 and 6.
なお、次に述べる本考案の要部以外は、従来例と同様で
あるので、ここでは従来例と同一部品に同一番号を付し
、詳細な説明を省略する。It should be noted that since the present invention is similar to the conventional example except for the main parts of the present invention described below, the same parts as in the conventional example are given the same numbers and detailed explanations are omitted here.
そして、本考案の要部について説明すると、チップ部品
４の電極４ａを半田６付けし、且つ、筐体５を半田６付
けする導電パターン３ａには、その両半田６付は間に位
置し、接続部３ｃを残した状態で、スリット状の導電パ
ターン除去部３ｄを形成すると共に、導電パターン除去
部３ｄと接続部３ｃを覆い、導電パターン３ａを横断す
るようにレジスト７が形成されている。To explain the main part of the present invention, the conductive pattern 3a to which the electrode 4a of the chip component 4 is soldered 6 and the casing 5 is soldered 6 is located between the two solders 6, A slit-shaped conductive pattern removed portion 3d is formed with the connecting portion 3c remaining, and a resist 7 is formed so as to cover the conductive pattern removed portion 3d and the connecting portion 3c and to cross the conductive pattern 3a.
そして、このような状態で、それぞれチップ部品４と筐
体５を導電パターン３ａに半田６付けすると、レジスト
７によって半田６の広がりが防止されて、筐体５と導電
パターン３ａ間、およびチップ部品４と導電パターン３
ａ間の半田６ののりがよく、また、スリット状の導電パ
ターン除去部３ｄを設けることによって、絶縁基板２お
よび半田６付けされて硬化された導電パターン３ａの伸
縮度合の違いによる影響が緩和され、導電パターン３ａ
のはがれが少なく、且つ、強度的に弱い電極４ａと半田
６付は間への応力を軽減でき、チップ部品４の破損を無
くすることができる。In this state, when the chip component 4 and the casing 5 are soldered 6 to the conductive pattern 3a, the resist 7 prevents the solder 6 from spreading, and the solder 6 is soldered between the casing 5 and the conductive pattern 3a and the chip component. 4 and conductive pattern 3
The adhesiveness of the solder 6 between the spaces a is good, and by providing the slit-shaped conductive pattern removal portion 3d, the influence of the difference in the degree of expansion and contraction of the insulating substrate 2 and the conductive pattern 3a that is hardened after being attached with the solder 6 is alleviated. , conductive pattern 3a
The electrode 4a and the solder 6, which are less likely to peel off and are weak in strength, can reduce stress between the electrode 4a and the solder 6, and can prevent damage to the chip component 4.
即ち、本考案によれば、チップ部品４と筐体５とを半田
６付けする導電パターン３ａに、チップ部品４の半田６
付は部と筐体５の半田６付は部との間においてスリット
状の導電パターン除去部３ｄを形成すると共に接続部３
Ｃを設け、また、この導電パターン３ａを横断するよう
にレジスト７を接続部３ｃ上に形成したものであるから
、絶縁基板２と導電パターン３ａの伸縮度合の違いによ
る影響が緩和されて、導電パターン３ａのはがれが少な
い上に、チップ部品４の電極４ａと半田６付は間の応力
を軽減でき、チップ部品４の破損を無くすることができ
ると共に、レジスト７によって、筐体５とチップ部品４
への半田６ののりを良くすることができる。That is, according to the present invention, the solder 6 of the chip component 4 is applied to the conductive pattern 3a for bonding the chip component 4 and the housing 5 with the solder 6.
A slit-shaped conductive pattern removed portion 3d is formed between the attached portion and the solder 6 attached portion of the housing 5, and the connecting portion 3
In addition, since the resist 7 is formed on the connecting portion 3c so as to cross the conductive pattern 3a, the influence of the difference in the degree of expansion and contraction between the insulating substrate 2 and the conductive pattern 3a is alleviated, and the conductive pattern 3a is In addition to less peeling of the pattern 3a, the stress between the electrode 4a of the chip component 4 and the solder 6 can be reduced, and damage to the chip component 4 can be eliminated. 4
It is possible to improve the adhesion of the solder 6 to the surface.
第１図から第４図は従来例に係わり、第１図は１従来例
の要部断面図、第２図は同平面図、第３図は他の従来例
の要部断面図、第４図は同平面図、第５図、第６図は本
考案に係わり、第５図は要部断面図、第６図はその平面
図である。
１・・・・・・プリント基板、２・・・・・・絶縁基板
、３ａ。
３ｂ・・・・・・導電パターン、３ｃ・・・・・・接続
部、３ｄ・・・・・・導電パターン除去部、４・・・・
・・チップ部品、４ａ・・・・・・電極、５・・・・・
・筐体、６・・・・・・半田、７・・・・・・レジスト
。1 to 4 relate to conventional examples; FIG. 1 is a sectional view of the main part of the first conventional example, FIG. 2 is a plan view of the same, FIG. 3 is a sectional view of the main part of another conventional example, and FIG. 5 and 6 are related to the present invention, FIG. 5 is a sectional view of a main part, and FIG. 6 is a plan view thereof. 1... Printed circuit board, 2... Insulated board, 3a. 3b...conductive pattern, 3c...connecting section, 3d...conductive pattern removal section, 4...
...Chip parts, 4a...Electrode, 5...
- Housing, 6...Solder, 7...Resist.
Claims (1)
プ部品の半田付は部と筐体の半田付は部との間において
スリット状の導電パターン除去部を形成すると共に接続
部を設け、該導電パターンを横断するようにレジストを
前記接続部上に形成したことを特徴とするプリント基板
。A slit-shaped conductive pattern removed portion is formed between the chip component soldering portion and the housing soldering portion, and a connecting portion is provided in the conductive pattern for soldering the chip portion and the housing. A printed circuit board characterized in that a resist is formed on the connection portion so as to cross the conductive pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9730481U JPS6038292Y2 (en) | 1981-06-30 | 1981-06-30 | Printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9730481U JPS6038292Y2 (en) | 1981-06-30 | 1981-06-30 | Printed board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS585372U JPS585372U (en) | 1983-01-13 |
| JPS6038292Y2 true JPS6038292Y2 (en) | 1985-11-15 |
Family
ID=29892116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9730481U Expired JPS6038292Y2 (en) | 1981-06-30 | 1981-06-30 | Printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6038292Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61117529U (en) * | 1984-12-29 | 1986-07-24 | ||
| JP4524291B2 (en) * | 2006-02-20 | 2010-08-11 | 協伸工業株式会社 | Flat type ground terminal and its surface mounting method |
-
1981
- 1981-06-30 JP JP9730481U patent/JPS6038292Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS585372U (en) | 1983-01-13 |
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