JPS61220447A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPS61220447A JPS61220447A JP6066085A JP6066085A JPS61220447A JP S61220447 A JPS61220447 A JP S61220447A JP 6066085 A JP6066085 A JP 6066085A JP 6066085 A JP6066085 A JP 6066085A JP S61220447 A JPS61220447 A JP S61220447A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- terminal
- gap
- semiconductor package
- external lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体パッケージに係り、特に面付実装用でリ
ード端子が底面部内側に曲っている半導体パッケージに
好適な構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor package, and particularly to a structure suitable for a semiconductor package for surface mounting, in which lead terminals are bent inward at the bottom surface.
従来の半導体パッケージは、特開昭５９−１２９４４８
号公報に記載のように、基板とパッケージとの接続部に
おけるストレス緩和策として外部リード端子と絶縁基体
との間に、間隙を形成する構造となっていた。しかし半
田付時における浴隔半田によって間隙が埋められる点に
ついては配置されていなかった。The conventional semiconductor package is disclosed in Japanese Patent Application Laid-Open No. 59-129448.
As described in the publication, the structure is such that a gap is formed between the external lead terminal and the insulating base as a measure to alleviate stress at the connection between the board and the package. However, no provision was made for gaps to be filled by bath solder during soldering.
これを以下図面を用いて詳述する。半導体パッケージと
プリント基板とを接続する手段として、溶融半田による
接続が一般的であるが、通常プリント基板とパッケージ
との材質の違いによる熱膨張係数の差によって、半田付
部にストレスが加わり、極端な場合には半田付部にクラ
ックを生じ、接続の信頼性を損なう結果となる１このた
め従来は、パッケージの外部リードと絶縁基体との間に
間隙を設け、半田付部に加わるストレスをリードの弾性
力で緩和させる方法が、とられている。しかしこの方法
には次のような欠点がある。以Ｆ第１図によって説明す
る。This will be explained in detail below using the drawings. Molten solder is a common method for connecting semiconductor packages and printed circuit boards, but the difference in thermal expansion coefficient due to the difference in materials between the printed circuit board and package usually causes stress to be applied to the soldered parts, causing extreme damage. If this happens, cracks will occur in the soldered parts, impairing the reliability of the connection1.For this reason, conventionally, a gap is provided between the external leads of the package and the insulating base to reduce the stress applied to the soldered parts. A method has been adopted that uses the elastic force of However, this method has the following drawbacks. This will be explained below with reference to FIG.
絶縁基体１には、その上面外周部に外部リード端子５が
取着され、端子５は基体１の上面部から側面部を介して
底面部に達するまで延長されており、かつ端子５の基体
１側面部及び底面部に位置する部位には、間隙６が形成
されている。An external lead terminal 5 is attached to the outer periphery of the upper surface of the insulating base 1, and the terminal 5 extends from the upper surface of the base 1 through the side surface until reaching the bottom surface. A gap 6 is formed at the side and bottom portions.
この間隙６は、端子５の基体１底面部に位置する部位５
ａを揺動自在とし、プリント基板７上の導電部７ａが熱
によって位置変動を生じたとしても、半田付部８には殆
んどストレスは加わらない。しかし半田何時半田が常に
プリント基板７の導電部７４と端子５の底面部位５ａと
の間だけに付着するとは限らない。特に浸漬半田付法の
場合は、半田は端子５と絶縁基体１との間に流れ込み１
間隙６を充填半田８ａで埋めてしまう状態が起こり易い
。この場合もはや間隙６の効果はなくなり、プリント基
板７の導電部７ａの位置変動によるストレスは、直接半
田付部８に加わり、接続の信頼性を極度に低下させるこ
とになる。This gap 6 corresponds to a portion 5 of the terminal 5 located on the bottom surface of the base 1.
A is made swingable, and even if the conductive part 7a on the printed circuit board 7 changes its position due to heat, almost no stress is applied to the soldered part 8. However, the solder does not always adhere only between the conductive portion 74 of the printed circuit board 7 and the bottom surface portion 5a of the terminal 5. Particularly in the case of the immersion soldering method, the solder flows between the terminal 5 and the insulating base 1.
A situation where the gap 6 is easily filled with the filler solder 8a occurs. In this case, the effect of the gap 6 is no longer present, and the stress due to the positional change of the conductive portion 7a of the printed circuit board 7 is applied directly to the soldered portion 8, extremely reducing the reliability of the connection.
本発明の目的は、半導体パッケージとプリント基板との
面付実装方式による半田接続を、より効率の高い状態で
行なうため、特に外部リードが底面の内側に曲ったタイ
プの半導体パッケージに対して、浸漬半田付法を適用が
できる半導体パッケージを提供することにある。An object of the present invention is to perform immersion solder connection between a semiconductor package and a printed circuit board using a surface mounting method in a more efficient manner, especially for a type of semiconductor package in which the external leads are bent inward on the bottom surface. The object of the present invention is to provide a semiconductor package to which a soldering method can be applied.
上記目的を達成するために本発明による半導体パッケー
ジは、絶縁基体の上面部あるいは側面部から側面部を介
して底面部まで延長した外部リード端子を有する半導体
パッケージにおいて、外部リード端子の内面側に半田が
付着しない表面処理を施したことを特徴とする。In order to achieve the above object, a semiconductor package according to the present invention has an external lead terminal extending from the top surface or side surface of an insulating substrate to the bottom surface through the side surface. It is characterized by a surface treatment that prevents adhesion.
以下、本発明の一実施例を第２図により説明する。絶縁
基体１は、その中央部に半導体素子３を収納する凹部を
有し、その凹部に素子３が固定されている。また基体１
には、その上面外周部に外部リード端子５が取着されて
いる。この端子５には、素子３の各電極がワイヤ４を介
して電気的に接続されている。また端子５は。An embodiment of the present invention will be described below with reference to FIG. The insulating substrate 1 has a recessed portion in the center thereof to accommodate the semiconductor element 3, and the element 3 is fixed in the recessed portion. Also, the base 1
An external lead terminal 5 is attached to the outer periphery of the upper surface thereof. Each electrode of the element 3 is electrically connected to this terminal 5 via a wire 4. Also, terminal 5.
基体１の上面部から側面部を介して底面部に達するまで
延長されており、かつ端子５の基体１側面部及び底面部
に位置する部位には、間隙６が形成されている。さらに
端子５の内側に面する部位には、半田が付着しないこと
を意図した表面処理層９が設けられている。この半田が
付着しない表面処理層９を作る手段としては、樹脂コー
ト、アルミ蒸着の他、端子５の材料を表側のみのセレク
トメッキしたもの、銅とアルミのクラツド材を利用する
方法等で達成される。A gap 6 is formed in a portion of the terminal 5 that extends from the top surface of the base 1 through the side surface to the bottom surface, and is located on the side surface and the bottom surface of the base 1 . Furthermore, a surface treatment layer 9 intended to prevent solder from adhering is provided on the portion facing the inside of the terminal 5. In addition to resin coating and aluminum vapor deposition, the surface treatment layer 9 to which solder does not adhere can be created by selectively plating only the front side of the terminal 5, or by using a cladding material of copper and aluminum. Ru.
この表面処理層９は、隙間６に入り込んだ半田が、端子
５に付着し隙間６が半田によって充填されることを防止
するため、半田付が容易となり、特に浸漬半田付法によ
っても間隙６が保証され、プリント基板７の導電部７ａ
が熱によって位置変動を生じても、端子５の底面部５ａ
を揺動させ、常に底面部５αを導電部７ａＫ当接させる
ことができる。This surface treatment layer 9 prevents the solder that has entered the gap 6 from adhering to the terminal 5 and filling the gap 6 with solder, making it easier to solder, and especially when using the immersion soldering method, the gap 6 can be closed. conductive parts 7a of the printed circuit board 7.
Even if the position of the terminal 5 changes due to heat, the bottom surface 5a of the terminal 5
The bottom surface portion 5α can always be brought into contact with the conductive portion 7aK by swinging the conductive portion 7aK.
本発明によれば、外部リードと絶縁基体との間隙が保証
できるので、いかなる半田付方法に対しても適用出来る
効果がある。According to the present invention, since the gap between the external lead and the insulating substrate can be guaranteed, the present invention can be applied to any soldering method.
第１図は、従来の実施例を示す半導体パッケージの断面
図、第２図は本発明の一実施例を示す半導体パッケージ
の断面図。
１・・・絶縁基体、 ２・・絶縁カバー、
６・・・半導体素子、 ４・・・ワイヤ、５
・・・外部リード、 ６・・・間隙。
７・・・プリント基板、 ８・・・半田付部。
９・・・表面処理層。FIG. 1 is a sectional view of a semiconductor package showing a conventional embodiment, and FIG. 2 is a sectional view of a semiconductor package showing an embodiment of the present invention. 1... Insulating base, 2... Insulating cover,
6... Semiconductor element, 4... Wire, 5
...External lead, 6...Gap. 7... Printed circuit board, 8... Soldering part. 9...Surface treatment layer.
Claims (1)
面部まで延長した外部リード端子を有する半導体パッケ
ージにおいて、外部リード端子の内面側に半田が付着し
ない表面処理を施したことを特徴とする半導体パッケー
ジ。A semiconductor package having an external lead terminal extending from the top surface or side surface of an insulating base to the bottom surface via the side surface, characterized in that a surface treatment is applied to the inner surface of the external lead terminal to prevent solder from adhering to the semiconductor package. package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6066085A JPS61220447A (en) | 1985-03-27 | 1985-03-27 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6066085A JPS61220447A (en) | 1985-03-27 | 1985-03-27 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61220447A true JPS61220447A (en) | 1986-09-30 |
Family
ID=13148712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6066085A Pending JPS61220447A (en) | 1985-03-27 | 1985-03-27 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61220447A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989010005A1 (en) * | 1988-04-12 | 1989-10-19 | Bolger Justin C | Pre-formed chip carrier cavity package |
| JPH11251176A (en) * | 1998-03-02 | 1999-09-17 | Murata Mfg Co Ltd | Ceramic electronic component |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4989158A (en) * | 1972-12-29 | 1974-08-26 | ||
| JPS59129448A (en) * | 1983-01-14 | 1984-07-25 | Kyocera Corp | Semiconductor package |
| JPS59219946A (en) * | 1983-05-30 | 1984-12-11 | Hitachi Ltd | Solder overflow preventing device for flat pack part |
-
1985
- 1985-03-27 JP JP6066085A patent/JPS61220447A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4989158A (en) * | 1972-12-29 | 1974-08-26 | ||
| JPS59129448A (en) * | 1983-01-14 | 1984-07-25 | Kyocera Corp | Semiconductor package |
| JPS59219946A (en) * | 1983-05-30 | 1984-12-11 | Hitachi Ltd | Solder overflow preventing device for flat pack part |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989010005A1 (en) * | 1988-04-12 | 1989-10-19 | Bolger Justin C | Pre-formed chip carrier cavity package |
| JPH11251176A (en) * | 1998-03-02 | 1999-09-17 | Murata Mfg Co Ltd | Ceramic electronic component |
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